PPCInstrInfo.cpp revision 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCTargetMachine.h"
19#include "PPCHazardRecognizers.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/MC/MCAsmInfo.h"
30
31#define GET_INSTRINFO_CTOR
32#define GET_INSTRINFO_MC_DESC
33#include "PPCGenInstrInfo.inc"
34
35namespace llvm {
36extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
37extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
38}
39
40using namespace llvm;
41
42PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
45
46/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47/// this target when scheduling the DAG.
48ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49  const TargetMachine *TM,
50  const ScheduleDAG *DAG) const {
51  // Should use subtarget info to pick the right hazard recognizer.  For
52  // now, always return a PPC970 recognizer.
53  const TargetInstrInfo *TII = TM->getInstrInfo();
54  assert(TII && "No InstrInfo?");
55  return new PPCHazardRecognizer970(*TII);
56}
57
58unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
59                                           int &FrameIndex) const {
60  switch (MI->getOpcode()) {
61  default: break;
62  case PPC::LD:
63  case PPC::LWZ:
64  case PPC::LFS:
65  case PPC::LFD:
66    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
67        MI->getOperand(2).isFI()) {
68      FrameIndex = MI->getOperand(2).getIndex();
69      return MI->getOperand(0).getReg();
70    }
71    break;
72  }
73  return 0;
74}
75
76unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
77                                          int &FrameIndex) const {
78  switch (MI->getOpcode()) {
79  default: break;
80  case PPC::STD:
81  case PPC::STW:
82  case PPC::STFS:
83  case PPC::STFD:
84    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
85        MI->getOperand(2).isFI()) {
86      FrameIndex = MI->getOperand(2).getIndex();
87      return MI->getOperand(0).getReg();
88    }
89    break;
90  }
91  return 0;
92}
93
94// commuteInstruction - We can commute rlwimi instructions, but only if the
95// rotate amt is zero.  We also have to munge the immediates a bit.
96MachineInstr *
97PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
98  MachineFunction &MF = *MI->getParent()->getParent();
99
100  // Normal instructions can be commuted the obvious way.
101  if (MI->getOpcode() != PPC::RLWIMI)
102    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
103
104  // Cannot commute if it has a non-zero rotate count.
105  if (MI->getOperand(3).getImm() != 0)
106    return 0;
107
108  // If we have a zero rotate count, we have:
109  //   M = mask(MB,ME)
110  //   Op0 = (Op1 & ~M) | (Op2 & M)
111  // Change this to:
112  //   M = mask((ME+1)&31, (MB-1)&31)
113  //   Op0 = (Op2 & ~M) | (Op1 & M)
114
115  // Swap op1/op2
116  unsigned Reg0 = MI->getOperand(0).getReg();
117  unsigned Reg1 = MI->getOperand(1).getReg();
118  unsigned Reg2 = MI->getOperand(2).getReg();
119  bool Reg1IsKill = MI->getOperand(1).isKill();
120  bool Reg2IsKill = MI->getOperand(2).isKill();
121  bool ChangeReg0 = false;
122  // If machine instrs are no longer in two-address forms, update
123  // destination register as well.
124  if (Reg0 == Reg1) {
125    // Must be two address instruction!
126    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
127           "Expecting a two-address instruction!");
128    Reg2IsKill = false;
129    ChangeReg0 = true;
130  }
131
132  // Masks.
133  unsigned MB = MI->getOperand(4).getImm();
134  unsigned ME = MI->getOperand(5).getImm();
135
136  if (NewMI) {
137    // Create a new instruction.
138    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
139    bool Reg0IsDead = MI->getOperand(0).isDead();
140    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
141      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
142      .addReg(Reg2, getKillRegState(Reg2IsKill))
143      .addReg(Reg1, getKillRegState(Reg1IsKill))
144      .addImm((ME+1) & 31)
145      .addImm((MB-1) & 31);
146  }
147
148  if (ChangeReg0)
149    MI->getOperand(0).setReg(Reg2);
150  MI->getOperand(2).setReg(Reg1);
151  MI->getOperand(1).setReg(Reg2);
152  MI->getOperand(2).setIsKill(Reg1IsKill);
153  MI->getOperand(1).setIsKill(Reg2IsKill);
154
155  // Swap the mask around.
156  MI->getOperand(4).setImm((ME+1) & 31);
157  MI->getOperand(5).setImm((MB-1) & 31);
158  return MI;
159}
160
161void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
162                              MachineBasicBlock::iterator MI) const {
163  DebugLoc DL;
164  BuildMI(MBB, MI, DL, get(PPC::NOP));
165}
166
167
168// Branch analysis.
169bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
170                                 MachineBasicBlock *&FBB,
171                                 SmallVectorImpl<MachineOperand> &Cond,
172                                 bool AllowModify) const {
173  // If the block has no terminators, it just falls into the block after it.
174  MachineBasicBlock::iterator I = MBB.end();
175  if (I == MBB.begin())
176    return false;
177  --I;
178  while (I->isDebugValue()) {
179    if (I == MBB.begin())
180      return false;
181    --I;
182  }
183  if (!isUnpredicatedTerminator(I))
184    return false;
185
186  // Get the last instruction in the block.
187  MachineInstr *LastInst = I;
188
189  // If there is only one terminator instruction, process it.
190  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
191    if (LastInst->getOpcode() == PPC::B) {
192      if (!LastInst->getOperand(0).isMBB())
193        return true;
194      TBB = LastInst->getOperand(0).getMBB();
195      return false;
196    } else if (LastInst->getOpcode() == PPC::BCC) {
197      if (!LastInst->getOperand(2).isMBB())
198        return true;
199      // Block ends with fall-through condbranch.
200      TBB = LastInst->getOperand(2).getMBB();
201      Cond.push_back(LastInst->getOperand(0));
202      Cond.push_back(LastInst->getOperand(1));
203      return false;
204    }
205    // Otherwise, don't know what this is.
206    return true;
207  }
208
209  // Get the instruction before it if it's a terminator.
210  MachineInstr *SecondLastInst = I;
211
212  // If there are three terminators, we don't know what sort of block this is.
213  if (SecondLastInst && I != MBB.begin() &&
214      isUnpredicatedTerminator(--I))
215    return true;
216
217  // If the block ends with PPC::B and PPC:BCC, handle it.
218  if (SecondLastInst->getOpcode() == PPC::BCC &&
219      LastInst->getOpcode() == PPC::B) {
220    if (!SecondLastInst->getOperand(2).isMBB() ||
221        !LastInst->getOperand(0).isMBB())
222      return true;
223    TBB =  SecondLastInst->getOperand(2).getMBB();
224    Cond.push_back(SecondLastInst->getOperand(0));
225    Cond.push_back(SecondLastInst->getOperand(1));
226    FBB = LastInst->getOperand(0).getMBB();
227    return false;
228  }
229
230  // If the block ends with two PPC:Bs, handle it.  The second one is not
231  // executed, so remove it.
232  if (SecondLastInst->getOpcode() == PPC::B &&
233      LastInst->getOpcode() == PPC::B) {
234    if (!SecondLastInst->getOperand(0).isMBB())
235      return true;
236    TBB = SecondLastInst->getOperand(0).getMBB();
237    I = LastInst;
238    if (AllowModify)
239      I->eraseFromParent();
240    return false;
241  }
242
243  // Otherwise, can't handle this.
244  return true;
245}
246
247unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
248  MachineBasicBlock::iterator I = MBB.end();
249  if (I == MBB.begin()) return 0;
250  --I;
251  while (I->isDebugValue()) {
252    if (I == MBB.begin())
253      return 0;
254    --I;
255  }
256  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
257    return 0;
258
259  // Remove the branch.
260  I->eraseFromParent();
261
262  I = MBB.end();
263
264  if (I == MBB.begin()) return 1;
265  --I;
266  if (I->getOpcode() != PPC::BCC)
267    return 1;
268
269  // Remove the branch.
270  I->eraseFromParent();
271  return 2;
272}
273
274unsigned
275PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
276                           MachineBasicBlock *FBB,
277                           const SmallVectorImpl<MachineOperand> &Cond,
278                           DebugLoc DL) const {
279  // Shouldn't be a fall through.
280  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
281  assert((Cond.size() == 2 || Cond.size() == 0) &&
282         "PPC branch conditions have two components!");
283
284  // One-way branch.
285  if (FBB == 0) {
286    if (Cond.empty())   // Unconditional branch
287      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
288    else                // Conditional branch
289      BuildMI(&MBB, DL, get(PPC::BCC))
290        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
291    return 1;
292  }
293
294  // Two-way Conditional Branch.
295  BuildMI(&MBB, DL, get(PPC::BCC))
296    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
297  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
298  return 2;
299}
300
301void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
302                               MachineBasicBlock::iterator I, DebugLoc DL,
303                               unsigned DestReg, unsigned SrcReg,
304                               bool KillSrc) const {
305  unsigned Opc;
306  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
307    Opc = PPC::OR;
308  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
309    Opc = PPC::OR8;
310  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
311    Opc = PPC::FMR;
312  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
313    Opc = PPC::MCRF;
314  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
315    Opc = PPC::VOR;
316  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
317    Opc = PPC::CROR;
318  else
319    llvm_unreachable("Impossible reg-to-reg copy");
320
321  const MCInstrDesc &MCID = get(Opc);
322  if (MCID.getNumOperands() == 3)
323    BuildMI(MBB, I, DL, MCID, DestReg)
324      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
325  else
326    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
327}
328
329bool
330PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
331                                  unsigned SrcReg, bool isKill,
332                                  int FrameIdx,
333                                  const TargetRegisterClass *RC,
334                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
335  DebugLoc DL;
336  if (RC == PPC::GPRCRegisterClass) {
337    if (SrcReg != PPC::LR) {
338      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
339                                         .addReg(SrcReg,
340                                                 getKillRegState(isKill)),
341                                         FrameIdx));
342    } else {
343      // FIXME: this spills LR immediately to memory in one step.  To do this,
344      // we use R11, which we know cannot be used in the prolog/epilog.  This is
345      // a hack.
346      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
347      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
348                                         .addReg(PPC::R11,
349                                                 getKillRegState(isKill)),
350                                         FrameIdx));
351    }
352  } else if (RC == PPC::G8RCRegisterClass) {
353    if (SrcReg != PPC::LR8) {
354      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
355                                         .addReg(SrcReg,
356                                                 getKillRegState(isKill)),
357                                         FrameIdx));
358    } else {
359      // FIXME: this spills LR immediately to memory in one step.  To do this,
360      // we use R11, which we know cannot be used in the prolog/epilog.  This is
361      // a hack.
362      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
363      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
364                                         .addReg(PPC::X11,
365                                                 getKillRegState(isKill)),
366                                         FrameIdx));
367    }
368  } else if (RC == PPC::F8RCRegisterClass) {
369    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
370                                       .addReg(SrcReg,
371                                               getKillRegState(isKill)),
372                                       FrameIdx));
373  } else if (RC == PPC::F4RCRegisterClass) {
374    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
375                                       .addReg(SrcReg,
376                                               getKillRegState(isKill)),
377                                       FrameIdx));
378  } else if (RC == PPC::CRRCRegisterClass) {
379    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
380        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
381      // FIXME (64-bit): Enable
382      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
383                                         .addReg(SrcReg,
384                                                 getKillRegState(isKill)),
385                                         FrameIdx));
386      return true;
387    } else {
388      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
389      // it's possible for the stack frame to be so big the save location is
390      // out of range of immediate offsets, necessitating another register.
391      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
392      // at the moment.
393
394      // We need to store the CR in the low 4-bits of the saved value.  First,
395      // issue a MFCR to save all of the CRBits.
396      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
397                                                           PPC::R2 : PPC::R0;
398      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
399                               .addReg(SrcReg, getKillRegState(isKill)));
400
401      // If the saved register wasn't CR0, shift the bits left so that they are
402      // in CR0's slot.
403      if (SrcReg != PPC::CR0) {
404        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
405        // rlwinm scratch, scratch, ShiftBits, 0, 31.
406        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
407                       .addReg(ScratchReg).addImm(ShiftBits)
408                       .addImm(0).addImm(31));
409      }
410
411      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
412                                         .addReg(ScratchReg,
413                                                 getKillRegState(isKill)),
414                                         FrameIdx));
415    }
416  } else if (RC == PPC::CRBITRCRegisterClass) {
417    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
418    // backend currently only uses CR1EQ as an individual bit, this should
419    // not cause any bug. If we need other uses of CR bits, the following
420    // code may be invalid.
421    unsigned Reg = 0;
422    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
423        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
424      Reg = PPC::CR0;
425    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
426             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
427      Reg = PPC::CR1;
428    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
429             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
430      Reg = PPC::CR2;
431    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
432             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
433      Reg = PPC::CR3;
434    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
435             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
436      Reg = PPC::CR4;
437    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
438             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
439      Reg = PPC::CR5;
440    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
441             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
442      Reg = PPC::CR6;
443    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
444             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
445      Reg = PPC::CR7;
446
447    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
448                               PPC::CRRCRegisterClass, NewMIs);
449
450  } else if (RC == PPC::VRRCRegisterClass) {
451    // We don't have indexed addressing for vector loads.  Emit:
452    // R0 = ADDI FI#
453    // STVX VAL, 0, R0
454    //
455    // FIXME: We use R0 here, because it isn't available for RA.
456    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
457                                       FrameIdx, 0, 0));
458    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
459                     .addReg(SrcReg, getKillRegState(isKill))
460                     .addReg(PPC::R0)
461                     .addReg(PPC::R0));
462  } else {
463    llvm_unreachable("Unknown regclass!");
464  }
465
466  return false;
467}
468
469void
470PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
471                                  MachineBasicBlock::iterator MI,
472                                  unsigned SrcReg, bool isKill, int FrameIdx,
473                                  const TargetRegisterClass *RC,
474                                  const TargetRegisterInfo *TRI) const {
475  MachineFunction &MF = *MBB.getParent();
476  SmallVector<MachineInstr*, 4> NewMIs;
477
478  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
479    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
480    FuncInfo->setSpillsCR();
481  }
482
483  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
484    MBB.insert(MI, NewMIs[i]);
485
486  const MachineFrameInfo &MFI = *MF.getFrameInfo();
487  MachineMemOperand *MMO =
488    MF.getMachineMemOperand(
489                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
490                            MachineMemOperand::MOStore,
491                            MFI.getObjectSize(FrameIdx),
492                            MFI.getObjectAlignment(FrameIdx));
493  NewMIs.back()->addMemOperand(MF, MMO);
494}
495
496void
497PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
498                                   unsigned DestReg, int FrameIdx,
499                                   const TargetRegisterClass *RC,
500                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
501  if (RC == PPC::GPRCRegisterClass) {
502    if (DestReg != PPC::LR) {
503      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
504                                                 DestReg), FrameIdx));
505    } else {
506      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
507                                                 PPC::R11), FrameIdx));
508      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
509    }
510  } else if (RC == PPC::G8RCRegisterClass) {
511    if (DestReg != PPC::LR8) {
512      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
513                                         FrameIdx));
514    } else {
515      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
516                                                 PPC::R11), FrameIdx));
517      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
518    }
519  } else if (RC == PPC::F8RCRegisterClass) {
520    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
521                                       FrameIdx));
522  } else if (RC == PPC::F4RCRegisterClass) {
523    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
524                                       FrameIdx));
525  } else if (RC == PPC::CRRCRegisterClass) {
526    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
527    // it's possible for the stack frame to be so big the save location is
528    // out of range of immediate offsets, necessitating another register.
529    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
530    // at the moment.
531    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
532                                                          PPC::R2 : PPC::R0;
533    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
534                                       ScratchReg), FrameIdx));
535
536    // If the reloaded register isn't CR0, shift the bits right so that they are
537    // in the right CR's slot.
538    if (DestReg != PPC::CR0) {
539      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
540      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
541      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
542                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
543                    .addImm(31));
544    }
545
546    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
547                     .addReg(ScratchReg));
548  } else if (RC == PPC::CRBITRCRegisterClass) {
549
550    unsigned Reg = 0;
551    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
552        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
553      Reg = PPC::CR0;
554    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
555             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
556      Reg = PPC::CR1;
557    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
558             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
559      Reg = PPC::CR2;
560    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
561             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
562      Reg = PPC::CR3;
563    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
564             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
565      Reg = PPC::CR4;
566    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
567             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
568      Reg = PPC::CR5;
569    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
570             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
571      Reg = PPC::CR6;
572    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
573             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
574      Reg = PPC::CR7;
575
576    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
577                                PPC::CRRCRegisterClass, NewMIs);
578
579  } else if (RC == PPC::VRRCRegisterClass) {
580    // We don't have indexed addressing for vector loads.  Emit:
581    // R0 = ADDI FI#
582    // Dest = LVX 0, R0
583    //
584    // FIXME: We use R0 here, because it isn't available for RA.
585    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
586                                       FrameIdx, 0, 0));
587    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
588                     .addReg(PPC::R0));
589  } else {
590    llvm_unreachable("Unknown regclass!");
591  }
592}
593
594void
595PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
596                                   MachineBasicBlock::iterator MI,
597                                   unsigned DestReg, int FrameIdx,
598                                   const TargetRegisterClass *RC,
599                                   const TargetRegisterInfo *TRI) const {
600  MachineFunction &MF = *MBB.getParent();
601  SmallVector<MachineInstr*, 4> NewMIs;
602  DebugLoc DL;
603  if (MI != MBB.end()) DL = MI->getDebugLoc();
604  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
605  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
606    MBB.insert(MI, NewMIs[i]);
607
608  const MachineFrameInfo &MFI = *MF.getFrameInfo();
609  MachineMemOperand *MMO =
610    MF.getMachineMemOperand(
611                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
612                            MachineMemOperand::MOLoad,
613                            MFI.getObjectSize(FrameIdx),
614                            MFI.getObjectAlignment(FrameIdx));
615  NewMIs.back()->addMemOperand(MF, MMO);
616}
617
618MachineInstr*
619PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
620                                       int FrameIx, uint64_t Offset,
621                                       const MDNode *MDPtr,
622                                       DebugLoc DL) const {
623  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
624  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
625  return &*MIB;
626}
627
628bool PPCInstrInfo::
629ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
630  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
631  // Leave the CR# the same, but invert the condition.
632  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
633  return false;
634}
635
636/// GetInstSize - Return the number of bytes of code the specified
637/// instruction may be.  This returns the maximum number of bytes.
638///
639unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
640  switch (MI->getOpcode()) {
641  case PPC::INLINEASM: {       // Inline Asm: Variable size.
642    const MachineFunction *MF = MI->getParent()->getParent();
643    const char *AsmStr = MI->getOperand(0).getSymbolName();
644    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
645  }
646  case PPC::PROLOG_LABEL:
647  case PPC::EH_LABEL:
648  case PPC::GC_LABEL:
649  case PPC::DBG_VALUE:
650    return 0;
651  default:
652    return 4; // PowerPC instructions are all 4 bytes
653  }
654}
655