PPCInstrInfo.cpp revision 0404cd97e4f6ebfe4f8057d4e21119d77654dff2 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23using namespace llvm;
24
25extern cl::opt<bool> EnablePPCRS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
26
27PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
28  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
29    RI(*TM.getSubtargetImpl(), *this) {}
30
31/// getPointerRegClass - Return the register class to use to hold pointers.
32/// This is used for addressing modes.
33const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
34  if (TM.getSubtargetImpl()->isPPC64())
35    return &PPC::G8RCRegClass;
36  else
37    return &PPC::GPRCRegClass;
38}
39
40
41bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
42                               unsigned& sourceReg,
43                               unsigned& destReg) const {
44  unsigned oc = MI.getOpcode();
45  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
46      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
47    assert(MI.getNumOperands() >= 3 &&
48           MI.getOperand(0).isRegister() &&
49           MI.getOperand(1).isRegister() &&
50           MI.getOperand(2).isRegister() &&
51           "invalid PPC OR instruction!");
52    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
53      sourceReg = MI.getOperand(1).getReg();
54      destReg = MI.getOperand(0).getReg();
55      return true;
56    }
57  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
58    assert(MI.getNumOperands() >= 3 &&
59           MI.getOperand(0).isRegister() &&
60           MI.getOperand(2).isImmediate() &&
61           "invalid PPC ADDI instruction!");
62    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
63      sourceReg = MI.getOperand(1).getReg();
64      destReg = MI.getOperand(0).getReg();
65      return true;
66    }
67  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
68    assert(MI.getNumOperands() >= 3 &&
69           MI.getOperand(0).isRegister() &&
70           MI.getOperand(1).isRegister() &&
71           MI.getOperand(2).isImmediate() &&
72           "invalid PPC ORI instruction!");
73    if (MI.getOperand(2).getImm() == 0) {
74      sourceReg = MI.getOperand(1).getReg();
75      destReg = MI.getOperand(0).getReg();
76      return true;
77    }
78  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
79             oc == PPC::FMRSD) {      // fmr r1, r2
80    assert(MI.getNumOperands() >= 2 &&
81           MI.getOperand(0).isRegister() &&
82           MI.getOperand(1).isRegister() &&
83           "invalid PPC FMR instruction");
84    sourceReg = MI.getOperand(1).getReg();
85    destReg = MI.getOperand(0).getReg();
86    return true;
87  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
88    assert(MI.getNumOperands() >= 2 &&
89           MI.getOperand(0).isRegister() &&
90           MI.getOperand(1).isRegister() &&
91           "invalid PPC MCRF instruction");
92    sourceReg = MI.getOperand(1).getReg();
93    destReg = MI.getOperand(0).getReg();
94    return true;
95  }
96  return false;
97}
98
99unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
100                                           int &FrameIndex) const {
101  switch (MI->getOpcode()) {
102  default: break;
103  case PPC::LD:
104  case PPC::LWZ:
105  case PPC::LFS:
106  case PPC::LFD:
107    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
108        MI->getOperand(2).isFI()) {
109      FrameIndex = MI->getOperand(2).getIndex();
110      return MI->getOperand(0).getReg();
111    }
112    break;
113  }
114  return 0;
115}
116
117unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
118                                          int &FrameIndex) const {
119  switch (MI->getOpcode()) {
120  default: break;
121  case PPC::STD:
122  case PPC::STW:
123  case PPC::STFS:
124  case PPC::STFD:
125    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
126        MI->getOperand(2).isFI()) {
127      FrameIndex = MI->getOperand(2).getIndex();
128      return MI->getOperand(0).getReg();
129    }
130    break;
131  }
132  return 0;
133}
134
135// commuteInstruction - We can commute rlwimi instructions, but only if the
136// rotate amt is zero.  We also have to munge the immediates a bit.
137MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
138  // Normal instructions can be commuted the obvious way.
139  if (MI->getOpcode() != PPC::RLWIMI)
140    return TargetInstrInfoImpl::commuteInstruction(MI);
141
142  // Cannot commute if it has a non-zero rotate count.
143  if (MI->getOperand(3).getImm() != 0)
144    return 0;
145
146  // If we have a zero rotate count, we have:
147  //   M = mask(MB,ME)
148  //   Op0 = (Op1 & ~M) | (Op2 & M)
149  // Change this to:
150  //   M = mask((ME+1)&31, (MB-1)&31)
151  //   Op0 = (Op2 & ~M) | (Op1 & M)
152
153  // Swap op1/op2
154  unsigned Reg0 = MI->getOperand(0).getReg();
155  unsigned Reg1 = MI->getOperand(1).getReg();
156  unsigned Reg2 = MI->getOperand(2).getReg();
157  bool Reg1IsKill = MI->getOperand(1).isKill();
158  bool Reg2IsKill = MI->getOperand(2).isKill();
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    MI->getOperand(0).setReg(Reg2);
166    Reg2IsKill = false;
167  }
168  MI->getOperand(2).setReg(Reg1);
169  MI->getOperand(1).setReg(Reg2);
170  MI->getOperand(2).setIsKill(Reg1IsKill);
171  MI->getOperand(1).setIsKill(Reg2IsKill);
172
173  // Swap the mask around.
174  unsigned MB = MI->getOperand(4).getImm();
175  unsigned ME = MI->getOperand(5).getImm();
176  MI->getOperand(4).setImm((ME+1) & 31);
177  MI->getOperand(5).setImm((MB-1) & 31);
178  return MI;
179}
180
181void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
182                              MachineBasicBlock::iterator MI) const {
183  BuildMI(MBB, MI, get(PPC::NOP));
184}
185
186
187// Branch analysis.
188bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
189                                 MachineBasicBlock *&FBB,
190                                 std::vector<MachineOperand> &Cond) const {
191  // If the block has no terminators, it just falls into the block after it.
192  MachineBasicBlock::iterator I = MBB.end();
193  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
194    return false;
195
196  // Get the last instruction in the block.
197  MachineInstr *LastInst = I;
198
199  // If there is only one terminator instruction, process it.
200  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
201    if (LastInst->getOpcode() == PPC::B) {
202      TBB = LastInst->getOperand(0).getMBB();
203      return false;
204    } else if (LastInst->getOpcode() == PPC::BCC) {
205      // Block ends with fall-through condbranch.
206      TBB = LastInst->getOperand(2).getMBB();
207      Cond.push_back(LastInst->getOperand(0));
208      Cond.push_back(LastInst->getOperand(1));
209      return false;
210    }
211    // Otherwise, don't know what this is.
212    return true;
213  }
214
215  // Get the instruction before it if it's a terminator.
216  MachineInstr *SecondLastInst = I;
217
218  // If there are three terminators, we don't know what sort of block this is.
219  if (SecondLastInst && I != MBB.begin() &&
220      isUnpredicatedTerminator(--I))
221    return true;
222
223  // If the block ends with PPC::B and PPC:BCC, handle it.
224  if (SecondLastInst->getOpcode() == PPC::BCC &&
225      LastInst->getOpcode() == PPC::B) {
226    TBB =  SecondLastInst->getOperand(2).getMBB();
227    Cond.push_back(SecondLastInst->getOperand(0));
228    Cond.push_back(SecondLastInst->getOperand(1));
229    FBB = LastInst->getOperand(0).getMBB();
230    return false;
231  }
232
233  // If the block ends with two PPC:Bs, handle it.  The second one is not
234  // executed, so remove it.
235  if (SecondLastInst->getOpcode() == PPC::B &&
236      LastInst->getOpcode() == PPC::B) {
237    TBB = SecondLastInst->getOperand(0).getMBB();
238    I = LastInst;
239    I->eraseFromParent();
240    return false;
241  }
242
243  // Otherwise, can't handle this.
244  return true;
245}
246
247unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
248  MachineBasicBlock::iterator I = MBB.end();
249  if (I == MBB.begin()) return 0;
250  --I;
251  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
252    return 0;
253
254  // Remove the branch.
255  I->eraseFromParent();
256
257  I = MBB.end();
258
259  if (I == MBB.begin()) return 1;
260  --I;
261  if (I->getOpcode() != PPC::BCC)
262    return 1;
263
264  // Remove the branch.
265  I->eraseFromParent();
266  return 2;
267}
268
269unsigned
270PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
271                           MachineBasicBlock *FBB,
272                           const std::vector<MachineOperand> &Cond) const {
273  // Shouldn't be a fall through.
274  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
275  assert((Cond.size() == 2 || Cond.size() == 0) &&
276         "PPC branch conditions have two components!");
277
278  // One-way branch.
279  if (FBB == 0) {
280    if (Cond.empty())   // Unconditional branch
281      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
282    else                // Conditional branch
283      BuildMI(&MBB, get(PPC::BCC))
284        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
285    return 1;
286  }
287
288  // Two-way Conditional Branch.
289  BuildMI(&MBB, get(PPC::BCC))
290    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
291  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
292  return 2;
293}
294
295void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
296                                   MachineBasicBlock::iterator MI,
297                                   unsigned DestReg, unsigned SrcReg,
298                                   const TargetRegisterClass *DestRC,
299                                   const TargetRegisterClass *SrcRC) const {
300  if (DestRC != SrcRC) {
301    cerr << "Not yet supported!";
302    abort();
303  }
304
305  if (DestRC == PPC::GPRCRegisterClass) {
306    BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
307  } else if (DestRC == PPC::G8RCRegisterClass) {
308    BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
309  } else if (DestRC == PPC::F4RCRegisterClass) {
310    BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
311  } else if (DestRC == PPC::F8RCRegisterClass) {
312    BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
313  } else if (DestRC == PPC::CRRCRegisterClass) {
314    BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
315  } else if (DestRC == PPC::VRRCRegisterClass) {
316    BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
317  } else if (DestRC == PPC::CRBITRCRegisterClass) {
318    BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
319  } else {
320    cerr << "Attempt to copy register that is not GPR or FPR";
321    abort();
322  }
323}
324
325static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
326                                unsigned SrcReg, bool isKill, int FrameIdx,
327                                const TargetRegisterClass *RC,
328                                SmallVectorImpl<MachineInstr*> &NewMIs) {
329  if (RC == PPC::GPRCRegisterClass) {
330    if (SrcReg != PPC::LR) {
331      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
332                                .addReg(SrcReg, false, false, isKill), FrameIdx));
333    } else {
334      // FIXME: this spills LR immediately to memory in one step.  To do this,
335      // we use R11, which we know cannot be used in the prolog/epilog.  This is
336      // a hack.
337      NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
338      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
339                              .addReg(PPC::R11, false, false, isKill), FrameIdx));
340    }
341  } else if (RC == PPC::G8RCRegisterClass) {
342    if (SrcReg != PPC::LR8) {
343      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
344                                .addReg(SrcReg, false, false, isKill), FrameIdx));
345    } else {
346      // FIXME: this spills LR immediately to memory in one step.  To do this,
347      // we use R11, which we know cannot be used in the prolog/epilog.  This is
348      // a hack.
349      NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
350      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
351                              .addReg(PPC::X11, false, false, isKill), FrameIdx));
352    }
353  } else if (RC == PPC::F8RCRegisterClass) {
354    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
355                                .addReg(SrcReg, false, false, isKill), FrameIdx));
356  } else if (RC == PPC::F4RCRegisterClass) {
357    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
358                                .addReg(SrcReg, false, false, isKill), FrameIdx));
359  } else if (RC == PPC::CRRCRegisterClass) {
360    if (EnablePPCRS) {  // FIXME (64-bit): Enable
361      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
362                                         .addReg(SrcReg, false, false, isKill),
363					 FrameIdx));
364      return true;
365    } else {
366      // FIXME: We use R0 here, because it isn't available for RA.  We need to
367      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
368      // to save all of the CRBits.
369      NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
370
371      // If the saved register wasn't CR0, shift the bits left so that they are
372      // in CR0's slot.
373      if (SrcReg != PPC::CR0) {
374        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
375        // rlwinm r0, r0, ShiftBits, 0, 31.
376        NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
377                         .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
378      }
379
380      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
381                                         .addReg(PPC::R0, false, false, isKill),
382                                         FrameIdx));
383    }
384  } else if (RC == PPC::CRBITRCRegisterClass) {
385    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
386    // backend currently only uses CR1EQ as an individual bit, this should
387    // not cause any bug. If we need other uses of CR bits, the following
388    // code may be invalid.
389    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
390      return StoreRegToStackSlot(TII, PPC::CR0, isKill, FrameIdx,
391                                 PPC::CRRCRegisterClass, NewMIs);
392    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
393      return StoreRegToStackSlot(TII, PPC::CR1, isKill, FrameIdx,
394                                 PPC::CRRCRegisterClass, NewMIs);
395    if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
396      return StoreRegToStackSlot(TII, PPC::CR2, isKill, FrameIdx,
397                                 PPC::CRRCRegisterClass, NewMIs);
398    if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
399      return StoreRegToStackSlot(TII, PPC::CR3, isKill, FrameIdx,
400                                 PPC::CRRCRegisterClass, NewMIs);
401    if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
402      return StoreRegToStackSlot(TII, PPC::CR4, isKill, FrameIdx,
403                                 PPC::CRRCRegisterClass, NewMIs);
404    if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
405      return StoreRegToStackSlot(TII, PPC::CR5, isKill, FrameIdx,
406                                 PPC::CRRCRegisterClass, NewMIs);
407    if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
408      return StoreRegToStackSlot(TII, PPC::CR6, isKill, FrameIdx,
409                                 PPC::CRRCRegisterClass, NewMIs);
410    if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
411      return StoreRegToStackSlot(TII, PPC::CR7, isKill, FrameIdx,
412                                 PPC::CRRCRegisterClass, NewMIs);
413  } else if (RC == PPC::VRRCRegisterClass) {
414    // We don't have indexed addressing for vector loads.  Emit:
415    // R0 = ADDI FI#
416    // STVX VAL, 0, R0
417    //
418    // FIXME: We use R0 here, because it isn't available for RA.
419    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
420                                       FrameIdx, 0, 0));
421    NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
422           .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
423  } else {
424    assert(0 && "Unknown regclass!");
425    abort();
426  }
427
428  return false;
429}
430
431void
432PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
433                                  MachineBasicBlock::iterator MI,
434                                  unsigned SrcReg, bool isKill, int FrameIdx,
435                                  const TargetRegisterClass *RC) const {
436  SmallVector<MachineInstr*, 4> NewMIs;
437
438  if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
439    PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
440    FuncInfo->setSpillsCR();
441  }
442
443  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
444    MBB.insert(MI, NewMIs[i]);
445}
446
447void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
448                                  bool isKill,
449                                  SmallVectorImpl<MachineOperand> &Addr,
450                                  const TargetRegisterClass *RC,
451                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
452  if (Addr[0].isFrameIndex()) {
453    if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(),
454                            RC, NewMIs)) {
455      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
456      FuncInfo->setSpillsCR();
457    }
458
459    return;
460  }
461
462  unsigned Opc = 0;
463  if (RC == PPC::GPRCRegisterClass) {
464    Opc = PPC::STW;
465  } else if (RC == PPC::G8RCRegisterClass) {
466    Opc = PPC::STD;
467  } else if (RC == PPC::F8RCRegisterClass) {
468    Opc = PPC::STFD;
469  } else if (RC == PPC::F4RCRegisterClass) {
470    Opc = PPC::STFS;
471  } else if (RC == PPC::VRRCRegisterClass) {
472    Opc = PPC::STVX;
473  } else {
474    assert(0 && "Unknown regclass!");
475    abort();
476  }
477  MachineInstrBuilder MIB = BuildMI(get(Opc))
478    .addReg(SrcReg, false, false, isKill);
479  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
480    MachineOperand &MO = Addr[i];
481    if (MO.isRegister())
482      MIB.addReg(MO.getReg());
483    else if (MO.isImmediate())
484      MIB.addImm(MO.getImm());
485    else
486      MIB.addFrameIndex(MO.getIndex());
487  }
488  NewMIs.push_back(MIB);
489  return;
490}
491
492static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
493                                 unsigned DestReg, int FrameIdx,
494                                 const TargetRegisterClass *RC,
495                                 SmallVectorImpl<MachineInstr*> &NewMIs) {
496  if (RC == PPC::GPRCRegisterClass) {
497    if (DestReg != PPC::LR) {
498      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
499                                         FrameIdx));
500    } else {
501      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
502                                         FrameIdx));
503      NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
504    }
505  } else if (RC == PPC::G8RCRegisterClass) {
506    if (DestReg != PPC::LR8) {
507      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
508                                         FrameIdx));
509    } else {
510      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
511                                         FrameIdx));
512      NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
513    }
514  } else if (RC == PPC::F8RCRegisterClass) {
515    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
516                                       FrameIdx));
517  } else if (RC == PPC::F4RCRegisterClass) {
518    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
519                                       FrameIdx));
520  } else if (RC == PPC::CRRCRegisterClass) {
521    // FIXME: We use R0 here, because it isn't available for RA.
522    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
523                                       FrameIdx));
524
525    // If the reloaded register isn't CR0, shift the bits right so that they are
526    // in the right CR's slot.
527    if (DestReg != PPC::CR0) {
528      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
529      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
530      NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
531                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
532    }
533
534    NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
535  } else if (RC == PPC::CRBITRCRegisterClass) {
536    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
537      return LoadRegFromStackSlot(TII, PPC::CR0, FrameIdx,
538                                  PPC::CRRCRegisterClass, NewMIs);
539    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
540      return LoadRegFromStackSlot(TII, PPC::CR1, FrameIdx,
541                                  PPC::CRRCRegisterClass, NewMIs);
542    if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
543      return LoadRegFromStackSlot(TII, PPC::CR2, FrameIdx,
544                                  PPC::CRRCRegisterClass, NewMIs);
545    if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
546      return LoadRegFromStackSlot(TII, PPC::CR3, FrameIdx,
547                                  PPC::CRRCRegisterClass, NewMIs);
548    if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
549      return LoadRegFromStackSlot(TII, PPC::CR4, FrameIdx,
550                                  PPC::CRRCRegisterClass, NewMIs);
551    if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
552      return LoadRegFromStackSlot(TII, PPC::CR5, FrameIdx,
553                                  PPC::CRRCRegisterClass, NewMIs);
554    if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
555      return LoadRegFromStackSlot(TII, PPC::CR6, FrameIdx,
556                                  PPC::CRRCRegisterClass, NewMIs);
557    if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
558      return LoadRegFromStackSlot(TII, PPC::CR7, FrameIdx,
559                                  PPC::CRRCRegisterClass, NewMIs);
560  } else if (RC == PPC::VRRCRegisterClass) {
561    // We don't have indexed addressing for vector loads.  Emit:
562    // R0 = ADDI FI#
563    // Dest = LVX 0, R0
564    //
565    // FIXME: We use R0 here, because it isn't available for RA.
566    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
567                                       FrameIdx, 0, 0));
568    NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
569                     .addReg(PPC::R0));
570  } else {
571    assert(0 && "Unknown regclass!");
572    abort();
573  }
574}
575
576void
577PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
578                                   MachineBasicBlock::iterator MI,
579                                   unsigned DestReg, int FrameIdx,
580                                   const TargetRegisterClass *RC) const {
581  SmallVector<MachineInstr*, 4> NewMIs;
582  LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs);
583  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
584    MBB.insert(MI, NewMIs[i]);
585}
586
587void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
588                                   SmallVectorImpl<MachineOperand> &Addr,
589                                   const TargetRegisterClass *RC,
590                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
591  if (Addr[0].isFrameIndex()) {
592    LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs);
593    return;
594  }
595
596  unsigned Opc = 0;
597  if (RC == PPC::GPRCRegisterClass) {
598    assert(DestReg != PPC::LR && "Can't handle this yet!");
599    Opc = PPC::LWZ;
600  } else if (RC == PPC::G8RCRegisterClass) {
601    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
602    Opc = PPC::LD;
603  } else if (RC == PPC::F8RCRegisterClass) {
604    Opc = PPC::LFD;
605  } else if (RC == PPC::F4RCRegisterClass) {
606    Opc = PPC::LFS;
607  } else if (RC == PPC::VRRCRegisterClass) {
608    Opc = PPC::LVX;
609  } else {
610    assert(0 && "Unknown regclass!");
611    abort();
612  }
613  MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
614  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
615    MachineOperand &MO = Addr[i];
616    if (MO.isRegister())
617      MIB.addReg(MO.getReg());
618    else if (MO.isImmediate())
619      MIB.addImm(MO.getImm());
620    else
621      MIB.addFrameIndex(MO.getIndex());
622  }
623  NewMIs.push_back(MIB);
624  return;
625}
626
627/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
628/// copy instructions, turning them into load/store instructions.
629MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
630                                              MachineInstr *MI,
631                                              SmallVectorImpl<unsigned> &Ops,
632                                              int FrameIndex) const {
633  if (Ops.size() != 1) return NULL;
634
635  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
636  // it takes more than one instruction to store it.
637  unsigned Opc = MI->getOpcode();
638  unsigned OpNum = Ops[0];
639
640  MachineInstr *NewMI = NULL;
641  if ((Opc == PPC::OR &&
642       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
643    if (OpNum == 0) {  // move -> store
644      unsigned InReg = MI->getOperand(1).getReg();
645      NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
646                                FrameIndex);
647    } else {           // move -> load
648      unsigned OutReg = MI->getOperand(0).getReg();
649      NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
650                                FrameIndex);
651    }
652  } else if ((Opc == PPC::OR8 &&
653              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
654    if (OpNum == 0) {  // move -> store
655      unsigned InReg = MI->getOperand(1).getReg();
656      NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
657                                FrameIndex);
658    } else {           // move -> load
659      unsigned OutReg = MI->getOperand(0).getReg();
660      NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
661    }
662  } else if (Opc == PPC::FMRD) {
663    if (OpNum == 0) {  // move -> store
664      unsigned InReg = MI->getOperand(1).getReg();
665      NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
666                                FrameIndex);
667    } else {           // move -> load
668      unsigned OutReg = MI->getOperand(0).getReg();
669      NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
670    }
671  } else if (Opc == PPC::FMRS) {
672    if (OpNum == 0) {  // move -> store
673      unsigned InReg = MI->getOperand(1).getReg();
674      NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
675                                FrameIndex);
676    } else {           // move -> load
677      unsigned OutReg = MI->getOperand(0).getReg();
678      NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
679    }
680  }
681
682  if (NewMI)
683    NewMI->copyKillDeadInfo(MI);
684  return NewMI;
685}
686
687bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
688                                        SmallVectorImpl<unsigned> &Ops) const {
689  if (Ops.size() != 1) return false;
690
691  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
692  // it takes more than one instruction to store it.
693  unsigned Opc = MI->getOpcode();
694
695  if ((Opc == PPC::OR &&
696       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
697    return true;
698  else if ((Opc == PPC::OR8 &&
699              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
700    return true;
701  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
702    return true;
703
704  return false;
705}
706
707
708bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
709  if (MBB.empty()) return false;
710
711  switch (MBB.back().getOpcode()) {
712  case PPC::BLR:   // Return.
713  case PPC::B:     // Uncond branch.
714  case PPC::BCTR:  // Indirect branch.
715    return true;
716  default: return false;
717  }
718}
719
720bool PPCInstrInfo::
721ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
722  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
723  // Leave the CR# the same, but invert the condition.
724  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
725  return false;
726}
727