PPCInstrInfo.cpp revision 21b5541814d57d0a31f353948e4e933dbb1af6a4 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
34                               unsigned& sourceReg,
35                               unsigned& destReg,
36                               unsigned& sourceSubIdx,
37                               unsigned& destSubIdx) const {
38  sourceSubIdx = destSubIdx = 0; // No sub-registers.
39
40  unsigned oc = MI.getOpcode();
41  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
43    assert(MI.getNumOperands() >= 3 &&
44           MI.getOperand(0).isReg() &&
45           MI.getOperand(1).isReg() &&
46           MI.getOperand(2).isReg() &&
47           "invalid PPC OR instruction!");
48    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49      sourceReg = MI.getOperand(1).getReg();
50      destReg = MI.getOperand(0).getReg();
51      return true;
52    }
53  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
54    assert(MI.getNumOperands() >= 3 &&
55           MI.getOperand(0).isReg() &&
56           MI.getOperand(2).isImm() &&
57           "invalid PPC ADDI instruction!");
58    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59      sourceReg = MI.getOperand(1).getReg();
60      destReg = MI.getOperand(0).getReg();
61      return true;
62    }
63  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
64    assert(MI.getNumOperands() >= 3 &&
65           MI.getOperand(0).isReg() &&
66           MI.getOperand(1).isReg() &&
67           MI.getOperand(2).isImm() &&
68           "invalid PPC ORI instruction!");
69    if (MI.getOperand(2).getImm() == 0) {
70      sourceReg = MI.getOperand(1).getReg();
71      destReg = MI.getOperand(0).getReg();
72      return true;
73    }
74  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75             oc == PPC::FMRSD) {      // fmr r1, r2
76    assert(MI.getNumOperands() >= 2 &&
77           MI.getOperand(0).isReg() &&
78           MI.getOperand(1).isReg() &&
79           "invalid PPC FMR instruction");
80    sourceReg = MI.getOperand(1).getReg();
81    destReg = MI.getOperand(0).getReg();
82    return true;
83  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC MCRF instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  }
92  return false;
93}
94
95unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                           int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::LD:
100  case PPC::LWZ:
101  case PPC::LFS:
102  case PPC::LFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                          int &FrameIndex) const {
115  switch (MI->getOpcode()) {
116  default: break;
117  case PPC::STD:
118  case PPC::STW:
119  case PPC::STFS:
120  case PPC::STFD:
121    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122        MI->getOperand(2).isFI()) {
123      FrameIndex = MI->getOperand(2).getIndex();
124      return MI->getOperand(0).getReg();
125    }
126    break;
127  }
128  return 0;
129}
130
131// commuteInstruction - We can commute rlwimi instructions, but only if the
132// rotate amt is zero.  We also have to munge the immediates a bit.
133MachineInstr *
134PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135  MachineFunction &MF = *MI->getParent()->getParent();
136
137  // Normal instructions can be commuted the obvious way.
138  if (MI->getOpcode() != PPC::RLWIMI)
139    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
140
141  // Cannot commute if it has a non-zero rotate count.
142  if (MI->getOperand(3).getImm() != 0)
143    return 0;
144
145  // If we have a zero rotate count, we have:
146  //   M = mask(MB,ME)
147  //   Op0 = (Op1 & ~M) | (Op2 & M)
148  // Change this to:
149  //   M = mask((ME+1)&31, (MB-1)&31)
150  //   Op0 = (Op2 & ~M) | (Op1 & M)
151
152  // Swap op1/op2
153  unsigned Reg0 = MI->getOperand(0).getReg();
154  unsigned Reg1 = MI->getOperand(1).getReg();
155  unsigned Reg2 = MI->getOperand(2).getReg();
156  bool Reg1IsKill = MI->getOperand(1).isKill();
157  bool Reg2IsKill = MI->getOperand(2).isKill();
158  bool ChangeReg0 = false;
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    Reg2IsKill = false;
166    ChangeReg0 = true;
167  }
168
169  // Masks.
170  unsigned MB = MI->getOperand(4).getImm();
171  unsigned ME = MI->getOperand(5).getImm();
172
173  if (NewMI) {
174    // Create a new instruction.
175    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176    bool Reg0IsDead = MI->getOperand(0).isDead();
177    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178      .addReg(Reg0, true, false, false, Reg0IsDead)
179      .addReg(Reg2, false, false, Reg2IsKill)
180      .addReg(Reg1, false, false, Reg1IsKill)
181      .addImm((ME+1) & 31)
182      .addImm((MB-1) & 31);
183  }
184
185  if (ChangeReg0)
186    MI->getOperand(0).setReg(Reg2);
187  MI->getOperand(2).setReg(Reg1);
188  MI->getOperand(1).setReg(Reg2);
189  MI->getOperand(2).setIsKill(Reg1IsKill);
190  MI->getOperand(1).setIsKill(Reg2IsKill);
191
192  // Swap the mask around.
193  MI->getOperand(4).setImm((ME+1) & 31);
194  MI->getOperand(5).setImm((MB-1) & 31);
195  return MI;
196}
197
198void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                              MachineBasicBlock::iterator MI) const {
200  DebugLoc DL = DebugLoc::getUnknownLoc();
201  if (MI != MBB.end()) DL = MI->getDebugLoc();
202
203  BuildMI(MBB, MI, DL, get(PPC::NOP));
204}
205
206
207// Branch analysis.
208bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                 MachineBasicBlock *&FBB,
210                                 SmallVectorImpl<MachineOperand> &Cond,
211                                 bool AllowModify) const {
212  // If the block has no terminators, it just falls into the block after it.
213  MachineBasicBlock::iterator I = MBB.end();
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
215    return false;
216
217  // Get the last instruction in the block.
218  MachineInstr *LastInst = I;
219
220  // If there is only one terminator instruction, process it.
221  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
222    if (LastInst->getOpcode() == PPC::B) {
223      TBB = LastInst->getOperand(0).getMBB();
224      return false;
225    } else if (LastInst->getOpcode() == PPC::BCC) {
226      // Block ends with fall-through condbranch.
227      TBB = LastInst->getOperand(2).getMBB();
228      Cond.push_back(LastInst->getOperand(0));
229      Cond.push_back(LastInst->getOperand(1));
230      return false;
231    }
232    // Otherwise, don't know what this is.
233    return true;
234  }
235
236  // Get the instruction before it if it's a terminator.
237  MachineInstr *SecondLastInst = I;
238
239  // If there are three terminators, we don't know what sort of block this is.
240  if (SecondLastInst && I != MBB.begin() &&
241      isUnpredicatedTerminator(--I))
242    return true;
243
244  // If the block ends with PPC::B and PPC:BCC, handle it.
245  if (SecondLastInst->getOpcode() == PPC::BCC &&
246      LastInst->getOpcode() == PPC::B) {
247    TBB =  SecondLastInst->getOperand(2).getMBB();
248    Cond.push_back(SecondLastInst->getOperand(0));
249    Cond.push_back(SecondLastInst->getOperand(1));
250    FBB = LastInst->getOperand(0).getMBB();
251    return false;
252  }
253
254  // If the block ends with two PPC:Bs, handle it.  The second one is not
255  // executed, so remove it.
256  if (SecondLastInst->getOpcode() == PPC::B &&
257      LastInst->getOpcode() == PPC::B) {
258    TBB = SecondLastInst->getOperand(0).getMBB();
259    I = LastInst;
260    if (AllowModify)
261      I->eraseFromParent();
262    return false;
263  }
264
265  // Otherwise, can't handle this.
266  return true;
267}
268
269unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
270  MachineBasicBlock::iterator I = MBB.end();
271  if (I == MBB.begin()) return 0;
272  --I;
273  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
274    return 0;
275
276  // Remove the branch.
277  I->eraseFromParent();
278
279  I = MBB.end();
280
281  if (I == MBB.begin()) return 1;
282  --I;
283  if (I->getOpcode() != PPC::BCC)
284    return 1;
285
286  // Remove the branch.
287  I->eraseFromParent();
288  return 2;
289}
290
291unsigned
292PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
293                           MachineBasicBlock *FBB,
294                           const SmallVectorImpl<MachineOperand> &Cond) const {
295  // Shouldn't be a fall through.
296  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
297  assert((Cond.size() == 2 || Cond.size() == 0) &&
298         "PPC branch conditions have two components!");
299
300  // One-way branch.
301  if (FBB == 0) {
302    if (Cond.empty())   // Unconditional branch
303      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
304    else                // Conditional branch
305      BuildMI(&MBB, get(PPC::BCC))
306        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
307    return 1;
308  }
309
310  // Two-way Conditional Branch.
311  BuildMI(&MBB, get(PPC::BCC))
312    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
313  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
314  return 2;
315}
316
317bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
318                                   MachineBasicBlock::iterator MI,
319                                   unsigned DestReg, unsigned SrcReg,
320                                   const TargetRegisterClass *DestRC,
321                                   const TargetRegisterClass *SrcRC) const {
322  if (DestRC != SrcRC) {
323    // Not yet supported!
324    return false;
325  }
326
327  DebugLoc DL = DebugLoc::getUnknownLoc();
328  if (MI != MBB.end()) DL = MI->getDebugLoc();
329
330  if (DestRC == PPC::GPRCRegisterClass) {
331    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
332  } else if (DestRC == PPC::G8RCRegisterClass) {
333    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
334  } else if (DestRC == PPC::F4RCRegisterClass) {
335    BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
336  } else if (DestRC == PPC::F8RCRegisterClass) {
337    BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
338  } else if (DestRC == PPC::CRRCRegisterClass) {
339    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
340  } else if (DestRC == PPC::VRRCRegisterClass) {
341    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
342  } else if (DestRC == PPC::CRBITRCRegisterClass) {
343    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
344  } else {
345    // Attempt to copy register that is not GPR or FPR
346    return false;
347  }
348
349  return true;
350}
351
352bool
353PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
354                                  unsigned SrcReg, bool isKill,
355                                  int FrameIdx,
356                                  const TargetRegisterClass *RC,
357                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
358  DebugLoc DL = DebugLoc::getUnknownLoc();
359  if (RC == PPC::GPRCRegisterClass) {
360    if (SrcReg != PPC::LR) {
361      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
362                                         .addReg(SrcReg, false, false, isKill),
363                                         FrameIdx));
364    } else {
365      // FIXME: this spills LR immediately to memory in one step.  To do this,
366      // we use R11, which we know cannot be used in the prolog/epilog.  This is
367      // a hack.
368      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
369      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
370                                         .addReg(PPC::R11, false, false, isKill),
371                                         FrameIdx));
372    }
373  } else if (RC == PPC::G8RCRegisterClass) {
374    if (SrcReg != PPC::LR8) {
375      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
376                              .addReg(SrcReg, false, false, isKill), FrameIdx));
377    } else {
378      // FIXME: this spills LR immediately to memory in one step.  To do this,
379      // we use R11, which we know cannot be used in the prolog/epilog.  This is
380      // a hack.
381      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
382      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
383                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
384    }
385  } else if (RC == PPC::F8RCRegisterClass) {
386    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
387                              .addReg(SrcReg, false, false, isKill), FrameIdx));
388  } else if (RC == PPC::F4RCRegisterClass) {
389    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
390                              .addReg(SrcReg, false, false, isKill), FrameIdx));
391  } else if (RC == PPC::CRRCRegisterClass) {
392    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
393        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
394      // FIXME (64-bit): Enable
395      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
396                                         .addReg(SrcReg, false, false, isKill),
397                                         FrameIdx));
398      return true;
399    } else {
400      // FIXME: We use R0 here, because it isn't available for RA.  We need to
401      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
402      // to save all of the CRBits.
403      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
404
405      // If the saved register wasn't CR0, shift the bits left so that they are
406      // in CR0's slot.
407      if (SrcReg != PPC::CR0) {
408        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
409        // rlwinm r0, r0, ShiftBits, 0, 31.
410        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
411                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
412      }
413
414      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
415                                         .addReg(PPC::R0, false, false, isKill),
416                                         FrameIdx));
417    }
418  } else if (RC == PPC::CRBITRCRegisterClass) {
419    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
420    // backend currently only uses CR1EQ as an individual bit, this should
421    // not cause any bug. If we need other uses of CR bits, the following
422    // code may be invalid.
423    unsigned Reg = 0;
424    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
425      Reg = PPC::CR0;
426    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
427      Reg = PPC::CR1;
428    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
429      Reg = PPC::CR2;
430    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
431      Reg = PPC::CR3;
432    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
433      Reg = PPC::CR4;
434    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
435      Reg = PPC::CR5;
436    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
437      Reg = PPC::CR6;
438    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
439      Reg = PPC::CR7;
440
441    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
442                               PPC::CRRCRegisterClass, NewMIs);
443
444  } else if (RC == PPC::VRRCRegisterClass) {
445    // We don't have indexed addressing for vector loads.  Emit:
446    // R0 = ADDI FI#
447    // STVX VAL, 0, R0
448    //
449    // FIXME: We use R0 here, because it isn't available for RA.
450    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
451                                       FrameIdx, 0, 0));
452    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
453         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
454  } else {
455    assert(0 && "Unknown regclass!");
456    abort();
457  }
458
459  return false;
460}
461
462void
463PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
464                                  MachineBasicBlock::iterator MI,
465                                  unsigned SrcReg, bool isKill, int FrameIdx,
466                                  const TargetRegisterClass *RC) const {
467  MachineFunction &MF = *MBB.getParent();
468  SmallVector<MachineInstr*, 4> NewMIs;
469
470  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
471    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
472    FuncInfo->setSpillsCR();
473  }
474
475  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
476    MBB.insert(MI, NewMIs[i]);
477}
478
479void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
480                                  bool isKill,
481                                  SmallVectorImpl<MachineOperand> &Addr,
482                                  const TargetRegisterClass *RC,
483                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
484  if (Addr[0].isFI()) {
485    if (StoreRegToStackSlot(MF, SrcReg, isKill,
486                            Addr[0].getIndex(), RC, NewMIs)) {
487      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
488      FuncInfo->setSpillsCR();
489    }
490
491    return;
492  }
493
494  DebugLoc DL = DebugLoc::getUnknownLoc();
495  unsigned Opc = 0;
496  if (RC == PPC::GPRCRegisterClass) {
497    Opc = PPC::STW;
498  } else if (RC == PPC::G8RCRegisterClass) {
499    Opc = PPC::STD;
500  } else if (RC == PPC::F8RCRegisterClass) {
501    Opc = PPC::STFD;
502  } else if (RC == PPC::F4RCRegisterClass) {
503    Opc = PPC::STFS;
504  } else if (RC == PPC::VRRCRegisterClass) {
505    Opc = PPC::STVX;
506  } else {
507    assert(0 && "Unknown regclass!");
508    abort();
509  }
510  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
511    .addReg(SrcReg, false, false, isKill);
512  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
513    MachineOperand &MO = Addr[i];
514    if (MO.isReg())
515      MIB.addReg(MO.getReg());
516    else if (MO.isImm())
517      MIB.addImm(MO.getImm());
518    else
519      MIB.addFrameIndex(MO.getIndex());
520  }
521  NewMIs.push_back(MIB);
522  return;
523}
524
525void
526PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
527                                   unsigned DestReg, int FrameIdx,
528                                   const TargetRegisterClass *RC,
529                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
530  if (RC == PPC::GPRCRegisterClass) {
531    if (DestReg != PPC::LR) {
532      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
533                                                 DestReg), FrameIdx));
534    } else {
535      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
536                                                 PPC::R11), FrameIdx));
537      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
538    }
539  } else if (RC == PPC::G8RCRegisterClass) {
540    if (DestReg != PPC::LR8) {
541      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
542                                         FrameIdx));
543    } else {
544      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
545                                                 PPC::R11), FrameIdx));
546      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
547    }
548  } else if (RC == PPC::F8RCRegisterClass) {
549    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
550                                       FrameIdx));
551  } else if (RC == PPC::F4RCRegisterClass) {
552    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
553                                       FrameIdx));
554  } else if (RC == PPC::CRRCRegisterClass) {
555    // FIXME: We use R0 here, because it isn't available for RA.
556    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
557                                       FrameIdx));
558
559    // If the reloaded register isn't CR0, shift the bits right so that they are
560    // in the right CR's slot.
561    if (DestReg != PPC::CR0) {
562      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
563      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
564      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
565                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
566    }
567
568    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
569  } else if (RC == PPC::CRBITRCRegisterClass) {
570
571    unsigned Reg = 0;
572    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
573      Reg = PPC::CR0;
574    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
575      Reg = PPC::CR1;
576    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
577      Reg = PPC::CR2;
578    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
579      Reg = PPC::CR3;
580    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
581      Reg = PPC::CR4;
582    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
583      Reg = PPC::CR5;
584    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
585      Reg = PPC::CR6;
586    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
587      Reg = PPC::CR7;
588
589    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
590                                PPC::CRRCRegisterClass, NewMIs);
591
592  } else if (RC == PPC::VRRCRegisterClass) {
593    // We don't have indexed addressing for vector loads.  Emit:
594    // R0 = ADDI FI#
595    // Dest = LVX 0, R0
596    //
597    // FIXME: We use R0 here, because it isn't available for RA.
598    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
599                                       FrameIdx, 0, 0));
600    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
601                     .addReg(PPC::R0));
602  } else {
603    assert(0 && "Unknown regclass!");
604    abort();
605  }
606}
607
608void
609PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
610                                   MachineBasicBlock::iterator MI,
611                                   unsigned DestReg, int FrameIdx,
612                                   const TargetRegisterClass *RC) const {
613  MachineFunction &MF = *MBB.getParent();
614  SmallVector<MachineInstr*, 4> NewMIs;
615  DebugLoc DL = DebugLoc::getUnknownLoc();
616  if (MI != MBB.end()) DL = MI->getDebugLoc();
617  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
618  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
619    MBB.insert(MI, NewMIs[i]);
620}
621
622void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
623                                   SmallVectorImpl<MachineOperand> &Addr,
624                                   const TargetRegisterClass *RC,
625                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
626  if (Addr[0].isFI()) {
627    LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
628                         DestReg, Addr[0].getIndex(), RC, NewMIs);
629    return;
630  }
631
632  unsigned Opc = 0;
633  if (RC == PPC::GPRCRegisterClass) {
634    assert(DestReg != PPC::LR && "Can't handle this yet!");
635    Opc = PPC::LWZ;
636  } else if (RC == PPC::G8RCRegisterClass) {
637    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
638    Opc = PPC::LD;
639  } else if (RC == PPC::F8RCRegisterClass) {
640    Opc = PPC::LFD;
641  } else if (RC == PPC::F4RCRegisterClass) {
642    Opc = PPC::LFS;
643  } else if (RC == PPC::VRRCRegisterClass) {
644    Opc = PPC::LVX;
645  } else {
646    assert(0 && "Unknown regclass!");
647    abort();
648  }
649  DebugLoc DL = DebugLoc::getUnknownLoc();
650  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
651  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
652    MachineOperand &MO = Addr[i];
653    if (MO.isReg())
654      MIB.addReg(MO.getReg());
655    else if (MO.isImm())
656      MIB.addImm(MO.getImm());
657    else
658      MIB.addFrameIndex(MO.getIndex());
659  }
660  NewMIs.push_back(MIB);
661  return;
662}
663
664/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
665/// copy instructions, turning them into load/store instructions.
666MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
667                                                  MachineInstr *MI,
668                                           const SmallVectorImpl<unsigned> &Ops,
669                                                  int FrameIndex) const {
670  if (Ops.size() != 1) return NULL;
671
672  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
673  // it takes more than one instruction to store it.
674  unsigned Opc = MI->getOpcode();
675  unsigned OpNum = Ops[0];
676
677  MachineInstr *NewMI = NULL;
678  if ((Opc == PPC::OR &&
679       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
680    if (OpNum == 0) {  // move -> store
681      unsigned InReg = MI->getOperand(1).getReg();
682      bool isKill = MI->getOperand(1).isKill();
683      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
684                                .addReg(InReg, false, false, isKill),
685                                FrameIndex);
686    } else {           // move -> load
687      unsigned OutReg = MI->getOperand(0).getReg();
688      bool isDead = MI->getOperand(0).isDead();
689      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
690                                .addReg(OutReg, true, false, false, isDead),
691                                FrameIndex);
692    }
693  } else if ((Opc == PPC::OR8 &&
694              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
695    if (OpNum == 0) {  // move -> store
696      unsigned InReg = MI->getOperand(1).getReg();
697      bool isKill = MI->getOperand(1).isKill();
698      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
699                                .addReg(InReg, false, false, isKill),
700                                FrameIndex);
701    } else {           // move -> load
702      unsigned OutReg = MI->getOperand(0).getReg();
703      bool isDead = MI->getOperand(0).isDead();
704      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
705                                .addReg(OutReg, true, false, false, isDead),
706                                FrameIndex);
707    }
708  } else if (Opc == PPC::FMRD) {
709    if (OpNum == 0) {  // move -> store
710      unsigned InReg = MI->getOperand(1).getReg();
711      bool isKill = MI->getOperand(1).isKill();
712      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
713                                .addReg(InReg, false, false, isKill),
714                                FrameIndex);
715    } else {           // move -> load
716      unsigned OutReg = MI->getOperand(0).getReg();
717      bool isDead = MI->getOperand(0).isDead();
718      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
719                                .addReg(OutReg, true, false, false, isDead),
720                                FrameIndex);
721    }
722  } else if (Opc == PPC::FMRS) {
723    if (OpNum == 0) {  // move -> store
724      unsigned InReg = MI->getOperand(1).getReg();
725      bool isKill = MI->getOperand(1).isKill();
726      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
727                                .addReg(InReg, false, false, isKill),
728                                FrameIndex);
729    } else {           // move -> load
730      unsigned OutReg = MI->getOperand(0).getReg();
731      bool isDead = MI->getOperand(0).isDead();
732      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
733                                .addReg(OutReg, true, false, false, isDead),
734                                FrameIndex);
735    }
736  }
737
738  return NewMI;
739}
740
741bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
742                                  const SmallVectorImpl<unsigned> &Ops) const {
743  if (Ops.size() != 1) return false;
744
745  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
746  // it takes more than one instruction to store it.
747  unsigned Opc = MI->getOpcode();
748
749  if ((Opc == PPC::OR &&
750       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
751    return true;
752  else if ((Opc == PPC::OR8 &&
753              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
754    return true;
755  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
756    return true;
757
758  return false;
759}
760
761
762bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
763  if (MBB.empty()) return false;
764
765  switch (MBB.back().getOpcode()) {
766  case PPC::BLR:   // Return.
767  case PPC::B:     // Uncond branch.
768  case PPC::BCTR:  // Indirect branch.
769    return true;
770  default: return false;
771  }
772}
773
774bool PPCInstrInfo::
775ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
776  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
777  // Leave the CR# the same, but invert the condition.
778  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
779  return false;
780}
781
782/// GetInstSize - Return the number of bytes of code the specified
783/// instruction may be.  This returns the maximum number of bytes.
784///
785unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
786  switch (MI->getOpcode()) {
787  case PPC::INLINEASM: {       // Inline Asm: Variable size.
788    const MachineFunction *MF = MI->getParent()->getParent();
789    const char *AsmStr = MI->getOperand(0).getSymbolName();
790    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
791  }
792  case PPC::DBG_LABEL:
793  case PPC::EH_LABEL:
794  case PPC::GC_LABEL:
795    return 0;
796  default:
797    return 4; // PowerPC instructions are all 4 bytes
798  }
799}
800