PPCInstrInfo.cpp revision 5f07d5224ddc32f405d7e19de8e58e91ab2816bc
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCInstrInfo.h" 15#include "PPCInstrBuilder.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPredicates.h" 18#include "PPCGenInstrInfo.inc" 19#include "PPCTargetMachine.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Support/CommandLine.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26#include "llvm/MC/MCAsmInfo.h" 27 28namespace llvm { 29extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 30extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 31} 32 33using namespace llvm; 34 35PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 36 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 37 RI(*TM.getSubtargetImpl(), *this) {} 38 39bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 40 unsigned& sourceReg, 41 unsigned& destReg, 42 unsigned& sourceSubIdx, 43 unsigned& destSubIdx) const { 44 sourceSubIdx = destSubIdx = 0; // No sub-registers. 45 46 unsigned oc = MI.getOpcode(); 47 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 48 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 49 assert(MI.getNumOperands() >= 3 && 50 MI.getOperand(0).isReg() && 51 MI.getOperand(1).isReg() && 52 MI.getOperand(2).isReg() && 53 "invalid PPC OR instruction!"); 54 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 55 sourceReg = MI.getOperand(1).getReg(); 56 destReg = MI.getOperand(0).getReg(); 57 return true; 58 } 59 } else if (oc == PPC::ADDI) { // addi r1, r2, 0 60 assert(MI.getNumOperands() >= 3 && 61 MI.getOperand(0).isReg() && 62 MI.getOperand(2).isImm() && 63 "invalid PPC ADDI instruction!"); 64 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) { 65 sourceReg = MI.getOperand(1).getReg(); 66 destReg = MI.getOperand(0).getReg(); 67 return true; 68 } 69 } else if (oc == PPC::ORI) { // ori r1, r2, 0 70 assert(MI.getNumOperands() >= 3 && 71 MI.getOperand(0).isReg() && 72 MI.getOperand(1).isReg() && 73 MI.getOperand(2).isImm() && 74 "invalid PPC ORI instruction!"); 75 if (MI.getOperand(2).getImm() == 0) { 76 sourceReg = MI.getOperand(1).getReg(); 77 destReg = MI.getOperand(0).getReg(); 78 return true; 79 } 80 } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2 81 assert(MI.getNumOperands() >= 2 && 82 MI.getOperand(0).isReg() && 83 MI.getOperand(1).isReg() && 84 "invalid PPC FMR instruction"); 85 sourceReg = MI.getOperand(1).getReg(); 86 destReg = MI.getOperand(0).getReg(); 87 return true; 88 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 89 assert(MI.getNumOperands() >= 2 && 90 MI.getOperand(0).isReg() && 91 MI.getOperand(1).isReg() && 92 "invalid PPC MCRF instruction"); 93 sourceReg = MI.getOperand(1).getReg(); 94 destReg = MI.getOperand(0).getReg(); 95 return true; 96 } 97 return false; 98} 99 100unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 101 int &FrameIndex) const { 102 switch (MI->getOpcode()) { 103 default: break; 104 case PPC::LD: 105 case PPC::LWZ: 106 case PPC::LFS: 107 case PPC::LFD: 108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 109 MI->getOperand(2).isFI()) { 110 FrameIndex = MI->getOperand(2).getIndex(); 111 return MI->getOperand(0).getReg(); 112 } 113 break; 114 } 115 return 0; 116} 117 118unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 119 int &FrameIndex) const { 120 switch (MI->getOpcode()) { 121 default: break; 122 case PPC::STD: 123 case PPC::STW: 124 case PPC::STFS: 125 case PPC::STFD: 126 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 127 MI->getOperand(2).isFI()) { 128 FrameIndex = MI->getOperand(2).getIndex(); 129 return MI->getOperand(0).getReg(); 130 } 131 break; 132 } 133 return 0; 134} 135 136// commuteInstruction - We can commute rlwimi instructions, but only if the 137// rotate amt is zero. We also have to munge the immediates a bit. 138MachineInstr * 139PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 140 MachineFunction &MF = *MI->getParent()->getParent(); 141 142 // Normal instructions can be commuted the obvious way. 143 if (MI->getOpcode() != PPC::RLWIMI) 144 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 145 146 // Cannot commute if it has a non-zero rotate count. 147 if (MI->getOperand(3).getImm() != 0) 148 return 0; 149 150 // If we have a zero rotate count, we have: 151 // M = mask(MB,ME) 152 // Op0 = (Op1 & ~M) | (Op2 & M) 153 // Change this to: 154 // M = mask((ME+1)&31, (MB-1)&31) 155 // Op0 = (Op2 & ~M) | (Op1 & M) 156 157 // Swap op1/op2 158 unsigned Reg0 = MI->getOperand(0).getReg(); 159 unsigned Reg1 = MI->getOperand(1).getReg(); 160 unsigned Reg2 = MI->getOperand(2).getReg(); 161 bool Reg1IsKill = MI->getOperand(1).isKill(); 162 bool Reg2IsKill = MI->getOperand(2).isKill(); 163 bool ChangeReg0 = false; 164 // If machine instrs are no longer in two-address forms, update 165 // destination register as well. 166 if (Reg0 == Reg1) { 167 // Must be two address instruction! 168 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 169 "Expecting a two-address instruction!"); 170 Reg2IsKill = false; 171 ChangeReg0 = true; 172 } 173 174 // Masks. 175 unsigned MB = MI->getOperand(4).getImm(); 176 unsigned ME = MI->getOperand(5).getImm(); 177 178 if (NewMI) { 179 // Create a new instruction. 180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 181 bool Reg0IsDead = MI->getOperand(0).isDead(); 182 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 183 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 184 .addReg(Reg2, getKillRegState(Reg2IsKill)) 185 .addReg(Reg1, getKillRegState(Reg1IsKill)) 186 .addImm((ME+1) & 31) 187 .addImm((MB-1) & 31); 188 } 189 190 if (ChangeReg0) 191 MI->getOperand(0).setReg(Reg2); 192 MI->getOperand(2).setReg(Reg1); 193 MI->getOperand(1).setReg(Reg2); 194 MI->getOperand(2).setIsKill(Reg1IsKill); 195 MI->getOperand(1).setIsKill(Reg2IsKill); 196 197 // Swap the mask around. 198 MI->getOperand(4).setImm((ME+1) & 31); 199 MI->getOperand(5).setImm((MB-1) & 31); 200 return MI; 201} 202 203void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 204 MachineBasicBlock::iterator MI) const { 205 DebugLoc DL; 206 BuildMI(MBB, MI, DL, get(PPC::NOP)); 207} 208 209 210// Branch analysis. 211bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 212 MachineBasicBlock *&FBB, 213 SmallVectorImpl<MachineOperand> &Cond, 214 bool AllowModify) const { 215 // If the block has no terminators, it just falls into the block after it. 216 MachineBasicBlock::iterator I = MBB.end(); 217 if (I == MBB.begin()) 218 return false; 219 --I; 220 while (I->isDebugValue()) { 221 if (I == MBB.begin()) 222 return false; 223 --I; 224 } 225 if (!isUnpredicatedTerminator(I)) 226 return false; 227 228 // Get the last instruction in the block. 229 MachineInstr *LastInst = I; 230 231 // If there is only one terminator instruction, process it. 232 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 233 if (LastInst->getOpcode() == PPC::B) { 234 if (!LastInst->getOperand(0).isMBB()) 235 return true; 236 TBB = LastInst->getOperand(0).getMBB(); 237 return false; 238 } else if (LastInst->getOpcode() == PPC::BCC) { 239 if (!LastInst->getOperand(2).isMBB()) 240 return true; 241 // Block ends with fall-through condbranch. 242 TBB = LastInst->getOperand(2).getMBB(); 243 Cond.push_back(LastInst->getOperand(0)); 244 Cond.push_back(LastInst->getOperand(1)); 245 return false; 246 } 247 // Otherwise, don't know what this is. 248 return true; 249 } 250 251 // Get the instruction before it if it's a terminator. 252 MachineInstr *SecondLastInst = I; 253 254 // If there are three terminators, we don't know what sort of block this is. 255 if (SecondLastInst && I != MBB.begin() && 256 isUnpredicatedTerminator(--I)) 257 return true; 258 259 // If the block ends with PPC::B and PPC:BCC, handle it. 260 if (SecondLastInst->getOpcode() == PPC::BCC && 261 LastInst->getOpcode() == PPC::B) { 262 if (!SecondLastInst->getOperand(2).isMBB() || 263 !LastInst->getOperand(0).isMBB()) 264 return true; 265 TBB = SecondLastInst->getOperand(2).getMBB(); 266 Cond.push_back(SecondLastInst->getOperand(0)); 267 Cond.push_back(SecondLastInst->getOperand(1)); 268 FBB = LastInst->getOperand(0).getMBB(); 269 return false; 270 } 271 272 // If the block ends with two PPC:Bs, handle it. The second one is not 273 // executed, so remove it. 274 if (SecondLastInst->getOpcode() == PPC::B && 275 LastInst->getOpcode() == PPC::B) { 276 if (!SecondLastInst->getOperand(0).isMBB()) 277 return true; 278 TBB = SecondLastInst->getOperand(0).getMBB(); 279 I = LastInst; 280 if (AllowModify) 281 I->eraseFromParent(); 282 return false; 283 } 284 285 // Otherwise, can't handle this. 286 return true; 287} 288 289unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 290 MachineBasicBlock::iterator I = MBB.end(); 291 if (I == MBB.begin()) return 0; 292 --I; 293 while (I->isDebugValue()) { 294 if (I == MBB.begin()) 295 return 0; 296 --I; 297 } 298 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 299 return 0; 300 301 // Remove the branch. 302 I->eraseFromParent(); 303 304 I = MBB.end(); 305 306 if (I == MBB.begin()) return 1; 307 --I; 308 if (I->getOpcode() != PPC::BCC) 309 return 1; 310 311 // Remove the branch. 312 I->eraseFromParent(); 313 return 2; 314} 315 316unsigned 317PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 318 MachineBasicBlock *FBB, 319 const SmallVectorImpl<MachineOperand> &Cond) const { 320 // FIXME this should probably have a DebugLoc argument 321 DebugLoc dl; 322 // Shouldn't be a fall through. 323 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 324 assert((Cond.size() == 2 || Cond.size() == 0) && 325 "PPC branch conditions have two components!"); 326 327 // One-way branch. 328 if (FBB == 0) { 329 if (Cond.empty()) // Unconditional branch 330 BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); 331 else // Conditional branch 332 BuildMI(&MBB, dl, get(PPC::BCC)) 333 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 334 return 1; 335 } 336 337 // Two-way Conditional Branch. 338 BuildMI(&MBB, dl, get(PPC::BCC)) 339 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 340 BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); 341 return 2; 342} 343 344bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 345 MachineBasicBlock::iterator MI, 346 unsigned DestReg, unsigned SrcReg, 347 const TargetRegisterClass *DestRC, 348 const TargetRegisterClass *SrcRC, 349 DebugLoc DL) const { 350 if (DestRC != SrcRC) { 351 // Not yet supported! 352 return false; 353 } 354 355 if (DestRC == PPC::GPRCRegisterClass) { 356 BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 357 } else if (DestRC == PPC::G8RCRegisterClass) { 358 BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 359 } else if (DestRC == PPC::F4RCRegisterClass || 360 DestRC == PPC::F8RCRegisterClass) { 361 BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg); 362 } else if (DestRC == PPC::CRRCRegisterClass) { 363 BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg); 364 } else if (DestRC == PPC::VRRCRegisterClass) { 365 BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 366 } else if (DestRC == PPC::CRBITRCRegisterClass) { 367 BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); 368 } else { 369 // Attempt to copy register that is not GPR or FPR 370 return false; 371 } 372 373 return true; 374} 375 376bool 377PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 378 unsigned SrcReg, bool isKill, 379 int FrameIdx, 380 const TargetRegisterClass *RC, 381 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 382 DebugLoc DL; 383 if (RC == PPC::GPRCRegisterClass) { 384 if (SrcReg != PPC::LR) { 385 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 386 .addReg(SrcReg, 387 getKillRegState(isKill)), 388 FrameIdx)); 389 } else { 390 // FIXME: this spills LR immediately to memory in one step. To do this, 391 // we use R11, which we know cannot be used in the prolog/epilog. This is 392 // a hack. 393 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 394 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 395 .addReg(PPC::R11, 396 getKillRegState(isKill)), 397 FrameIdx)); 398 } 399 } else if (RC == PPC::G8RCRegisterClass) { 400 if (SrcReg != PPC::LR8) { 401 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 402 .addReg(SrcReg, 403 getKillRegState(isKill)), 404 FrameIdx)); 405 } else { 406 // FIXME: this spills LR immediately to memory in one step. To do this, 407 // we use R11, which we know cannot be used in the prolog/epilog. This is 408 // a hack. 409 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 410 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 411 .addReg(PPC::X11, 412 getKillRegState(isKill)), 413 FrameIdx)); 414 } 415 } else if (RC == PPC::F8RCRegisterClass) { 416 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 417 .addReg(SrcReg, 418 getKillRegState(isKill)), 419 FrameIdx)); 420 } else if (RC == PPC::F4RCRegisterClass) { 421 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 422 .addReg(SrcReg, 423 getKillRegState(isKill)), 424 FrameIdx)); 425 } else if (RC == PPC::CRRCRegisterClass) { 426 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 427 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 428 // FIXME (64-bit): Enable 429 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 430 .addReg(SrcReg, 431 getKillRegState(isKill)), 432 FrameIdx)); 433 return true; 434 } else { 435 // FIXME: We need a scatch reg here. The trouble with using R0 is that 436 // it's possible for the stack frame to be so big the save location is 437 // out of range of immediate offsets, necessitating another register. 438 // We hack this on Darwin by reserving R2. It's probably broken on Linux 439 // at the moment. 440 441 // We need to store the CR in the low 4-bits of the saved value. First, 442 // issue a MFCR to save all of the CRBits. 443 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 444 PPC::R2 : PPC::R0; 445 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 446 .addReg(SrcReg, getKillRegState(isKill))); 447 448 // If the saved register wasn't CR0, shift the bits left so that they are 449 // in CR0's slot. 450 if (SrcReg != PPC::CR0) { 451 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 452 // rlwinm scratch, scratch, ShiftBits, 0, 31. 453 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 454 .addReg(ScratchReg).addImm(ShiftBits) 455 .addImm(0).addImm(31)); 456 } 457 458 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 459 .addReg(ScratchReg, 460 getKillRegState(isKill)), 461 FrameIdx)); 462 } 463 } else if (RC == PPC::CRBITRCRegisterClass) { 464 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 465 // backend currently only uses CR1EQ as an individual bit, this should 466 // not cause any bug. If we need other uses of CR bits, the following 467 // code may be invalid. 468 unsigned Reg = 0; 469 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 470 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 471 Reg = PPC::CR0; 472 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 473 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 474 Reg = PPC::CR1; 475 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 476 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 477 Reg = PPC::CR2; 478 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 479 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 480 Reg = PPC::CR3; 481 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 482 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 483 Reg = PPC::CR4; 484 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 485 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 486 Reg = PPC::CR5; 487 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 488 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 489 Reg = PPC::CR6; 490 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 491 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 492 Reg = PPC::CR7; 493 494 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 495 PPC::CRRCRegisterClass, NewMIs); 496 497 } else if (RC == PPC::VRRCRegisterClass) { 498 // We don't have indexed addressing for vector loads. Emit: 499 // R0 = ADDI FI# 500 // STVX VAL, 0, R0 501 // 502 // FIXME: We use R0 here, because it isn't available for RA. 503 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 504 FrameIdx, 0, 0)); 505 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 506 .addReg(SrcReg, getKillRegState(isKill)) 507 .addReg(PPC::R0) 508 .addReg(PPC::R0)); 509 } else { 510 llvm_unreachable("Unknown regclass!"); 511 } 512 513 return false; 514} 515 516void 517PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 518 MachineBasicBlock::iterator MI, 519 unsigned SrcReg, bool isKill, int FrameIdx, 520 const TargetRegisterClass *RC, 521 const TargetRegisterInfo *TRI) const { 522 MachineFunction &MF = *MBB.getParent(); 523 SmallVector<MachineInstr*, 4> NewMIs; 524 525 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 526 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 527 FuncInfo->setSpillsCR(); 528 } 529 530 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 531 MBB.insert(MI, NewMIs[i]); 532} 533 534void 535PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 536 unsigned DestReg, int FrameIdx, 537 const TargetRegisterClass *RC, 538 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 539 if (RC == PPC::GPRCRegisterClass) { 540 if (DestReg != PPC::LR) { 541 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 542 DestReg), FrameIdx)); 543 } else { 544 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 545 PPC::R11), FrameIdx)); 546 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 547 } 548 } else if (RC == PPC::G8RCRegisterClass) { 549 if (DestReg != PPC::LR8) { 550 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 551 FrameIdx)); 552 } else { 553 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 554 PPC::R11), FrameIdx)); 555 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 556 } 557 } else if (RC == PPC::F8RCRegisterClass) { 558 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 559 FrameIdx)); 560 } else if (RC == PPC::F4RCRegisterClass) { 561 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 562 FrameIdx)); 563 } else if (RC == PPC::CRRCRegisterClass) { 564 // FIXME: We need a scatch reg here. The trouble with using R0 is that 565 // it's possible for the stack frame to be so big the save location is 566 // out of range of immediate offsets, necessitating another register. 567 // We hack this on Darwin by reserving R2. It's probably broken on Linux 568 // at the moment. 569 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 570 PPC::R2 : PPC::R0; 571 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 572 ScratchReg), FrameIdx)); 573 574 // If the reloaded register isn't CR0, shift the bits right so that they are 575 // in the right CR's slot. 576 if (DestReg != PPC::CR0) { 577 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 578 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 579 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 580 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 581 .addImm(31)); 582 } 583 584 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 585 .addReg(ScratchReg)); 586 } else if (RC == PPC::CRBITRCRegisterClass) { 587 588 unsigned Reg = 0; 589 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 590 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 591 Reg = PPC::CR0; 592 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 593 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 594 Reg = PPC::CR1; 595 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 596 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 597 Reg = PPC::CR2; 598 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 599 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 600 Reg = PPC::CR3; 601 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 602 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 603 Reg = PPC::CR4; 604 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 605 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 606 Reg = PPC::CR5; 607 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 608 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 609 Reg = PPC::CR6; 610 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 611 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 612 Reg = PPC::CR7; 613 614 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 615 PPC::CRRCRegisterClass, NewMIs); 616 617 } else if (RC == PPC::VRRCRegisterClass) { 618 // We don't have indexed addressing for vector loads. Emit: 619 // R0 = ADDI FI# 620 // Dest = LVX 0, R0 621 // 622 // FIXME: We use R0 here, because it isn't available for RA. 623 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 624 FrameIdx, 0, 0)); 625 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 626 .addReg(PPC::R0)); 627 } else { 628 llvm_unreachable("Unknown regclass!"); 629 } 630} 631 632void 633PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 634 MachineBasicBlock::iterator MI, 635 unsigned DestReg, int FrameIdx, 636 const TargetRegisterClass *RC, 637 const TargetRegisterInfo *TRI) const { 638 MachineFunction &MF = *MBB.getParent(); 639 SmallVector<MachineInstr*, 4> NewMIs; 640 DebugLoc DL; 641 if (MI != MBB.end()) DL = MI->getDebugLoc(); 642 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 643 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 644 MBB.insert(MI, NewMIs[i]); 645} 646 647MachineInstr* 648PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 649 int FrameIx, uint64_t Offset, 650 const MDNode *MDPtr, 651 DebugLoc DL) const { 652 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 653 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 654 return &*MIB; 655} 656 657/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 658/// copy instructions, turning them into load/store instructions. 659MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 660 MachineInstr *MI, 661 const SmallVectorImpl<unsigned> &Ops, 662 int FrameIndex) const { 663 if (Ops.size() != 1) return NULL; 664 665 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 666 // it takes more than one instruction to store it. 667 unsigned Opc = MI->getOpcode(); 668 unsigned OpNum = Ops[0]; 669 670 MachineInstr *NewMI = NULL; 671 if ((Opc == PPC::OR && 672 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 673 if (OpNum == 0) { // move -> store 674 unsigned InReg = MI->getOperand(1).getReg(); 675 bool isKill = MI->getOperand(1).isKill(); 676 bool isUndef = MI->getOperand(1).isUndef(); 677 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) 678 .addReg(InReg, 679 getKillRegState(isKill) | 680 getUndefRegState(isUndef)), 681 FrameIndex); 682 } else { // move -> load 683 unsigned OutReg = MI->getOperand(0).getReg(); 684 bool isDead = MI->getOperand(0).isDead(); 685 bool isUndef = MI->getOperand(0).isUndef(); 686 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) 687 .addReg(OutReg, 688 RegState::Define | 689 getDeadRegState(isDead) | 690 getUndefRegState(isUndef)), 691 FrameIndex); 692 } 693 } else if ((Opc == PPC::OR8 && 694 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 695 if (OpNum == 0) { // move -> store 696 unsigned InReg = MI->getOperand(1).getReg(); 697 bool isKill = MI->getOperand(1).isKill(); 698 bool isUndef = MI->getOperand(1).isUndef(); 699 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) 700 .addReg(InReg, 701 getKillRegState(isKill) | 702 getUndefRegState(isUndef)), 703 FrameIndex); 704 } else { // move -> load 705 unsigned OutReg = MI->getOperand(0).getReg(); 706 bool isDead = MI->getOperand(0).isDead(); 707 bool isUndef = MI->getOperand(0).isUndef(); 708 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) 709 .addReg(OutReg, 710 RegState::Define | 711 getDeadRegState(isDead) | 712 getUndefRegState(isUndef)), 713 FrameIndex); 714 } 715 } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) { 716 // The register may be F4RC or F8RC, and that determines the memory op. 717 unsigned OrigReg = MI->getOperand(OpNum).getReg(); 718 // We cannot tell the register class from a physreg alone. 719 if (TargetRegisterInfo::isPhysicalRegister(OrigReg)) 720 return NULL; 721 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg); 722 const bool is64 = RC == PPC::F8RCRegisterClass; 723 724 if (OpNum == 0) { // move -> store 725 unsigned InReg = MI->getOperand(1).getReg(); 726 bool isKill = MI->getOperand(1).isKill(); 727 bool isUndef = MI->getOperand(1).isUndef(); 728 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), 729 get(is64 ? PPC::STFD : PPC::STFS)) 730 .addReg(InReg, 731 getKillRegState(isKill) | 732 getUndefRegState(isUndef)), 733 FrameIndex); 734 } else { // move -> load 735 unsigned OutReg = MI->getOperand(0).getReg(); 736 bool isDead = MI->getOperand(0).isDead(); 737 bool isUndef = MI->getOperand(0).isUndef(); 738 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), 739 get(is64 ? PPC::LFD : PPC::LFS)) 740 .addReg(OutReg, 741 RegState::Define | 742 getDeadRegState(isDead) | 743 getUndefRegState(isUndef)), 744 FrameIndex); 745 } 746 } 747 748 return NewMI; 749} 750 751bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 752 const SmallVectorImpl<unsigned> &Ops) const { 753 if (Ops.size() != 1) return false; 754 755 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 756 // it takes more than one instruction to store it. 757 unsigned Opc = MI->getOpcode(); 758 759 if ((Opc == PPC::OR && 760 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 761 return true; 762 else if ((Opc == PPC::OR8 && 763 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 764 return true; 765 else if (Opc == PPC::FMR || Opc == PPC::FMRSD) 766 return true; 767 768 return false; 769} 770 771 772bool PPCInstrInfo:: 773ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 774 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 775 // Leave the CR# the same, but invert the condition. 776 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 777 return false; 778} 779 780/// GetInstSize - Return the number of bytes of code the specified 781/// instruction may be. This returns the maximum number of bytes. 782/// 783unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 784 switch (MI->getOpcode()) { 785 case PPC::INLINEASM: { // Inline Asm: Variable size. 786 const MachineFunction *MF = MI->getParent()->getParent(); 787 const char *AsmStr = MI->getOperand(0).getSymbolName(); 788 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 789 } 790 case PPC::DBG_LABEL: 791 case PPC::EH_LABEL: 792 case PPC::GC_LABEL: 793 case PPC::DBG_VALUE: 794 return 0; 795 default: 796 return 4; // PowerPC instructions are all 4 bytes 797 } 798} 799