PPCInstrInfo.cpp revision 09fdc7baae1b6905fe18df48e2278e74d4e39ccd 
1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCTargetMachine.h"
19#include "PPCHazardRecognizers.h"
20#include "MCTargetDesc/PPCPredicates.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/ADT/STLExtras.h"
32
33#define GET_INSTRINFO_CTOR
34#include "PPCGenInstrInfo.inc"
35
36namespace llvm {
37extern cl::opt<bool> DisablePPC32RS;
38extern cl::opt<bool> DisablePPC64RS;
39}
40
41using namespace llvm;
42
43static cl::
44opt<bool> EnableCTRLoopAnal("enable-ppc-ctrloop-analysis", cl::Hidden,
45            cl::desc("Enable analysis for CTR loops (experimental)"));
46
47PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
48  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
49    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
50
51/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
52/// this target when scheduling the DAG.
53ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
54  const TargetMachine *TM,
55  const ScheduleDAG *DAG) const {
56  unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
57  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) {
58    const InstrItineraryData *II = TM->getInstrItineraryData();
59    return new PPCScoreboardHazardRecognizer(II, DAG);
60  }
61
62  return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
63}
64
65/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
66/// to use for this target when scheduling the DAG.
67ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
68  const InstrItineraryData *II,
69  const ScheduleDAG *DAG) const {
70  unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
71
72  // Most subtargets use a PPC970 recognizer.
73  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) {
74    const TargetInstrInfo *TII = TM.getInstrInfo();
75    assert(TII && "No InstrInfo?");
76
77    return new PPCHazardRecognizer970(*TII);
78  }
79
80  return new PPCScoreboardHazardRecognizer(II, DAG);
81}
82unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
83                                           int &FrameIndex) const {
84  switch (MI->getOpcode()) {
85  default: break;
86  case PPC::LD:
87  case PPC::LWZ:
88  case PPC::LFS:
89  case PPC::LFD:
90    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
91        MI->getOperand(2).isFI()) {
92      FrameIndex = MI->getOperand(2).getIndex();
93      return MI->getOperand(0).getReg();
94    }
95    break;
96  }
97  return 0;
98}
99
100unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101                                          int &FrameIndex) const {
102  switch (MI->getOpcode()) {
103  default: break;
104  case PPC::STD:
105  case PPC::STW:
106  case PPC::STFS:
107  case PPC::STFD:
108    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109        MI->getOperand(2).isFI()) {
110      FrameIndex = MI->getOperand(2).getIndex();
111      return MI->getOperand(0).getReg();
112    }
113    break;
114  }
115  return 0;
116}
117
118// commuteInstruction - We can commute rlwimi instructions, but only if the
119// rotate amt is zero.  We also have to munge the immediates a bit.
120MachineInstr *
121PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
122  MachineFunction &MF = *MI->getParent()->getParent();
123
124  // Normal instructions can be commuted the obvious way.
125  if (MI->getOpcode() != PPC::RLWIMI)
126    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
127
128  // Cannot commute if it has a non-zero rotate count.
129  if (MI->getOperand(3).getImm() != 0)
130    return 0;
131
132  // If we have a zero rotate count, we have:
133  //   M = mask(MB,ME)
134  //   Op0 = (Op1 & ~M) | (Op2 & M)
135  // Change this to:
136  //   M = mask((ME+1)&31, (MB-1)&31)
137  //   Op0 = (Op2 & ~M) | (Op1 & M)
138
139  // Swap op1/op2
140  unsigned Reg0 = MI->getOperand(0).getReg();
141  unsigned Reg1 = MI->getOperand(1).getReg();
142  unsigned Reg2 = MI->getOperand(2).getReg();
143  bool Reg1IsKill = MI->getOperand(1).isKill();
144  bool Reg2IsKill = MI->getOperand(2).isKill();
145  bool ChangeReg0 = false;
146  // If machine instrs are no longer in two-address forms, update
147  // destination register as well.
148  if (Reg0 == Reg1) {
149    // Must be two address instruction!
150    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
151           "Expecting a two-address instruction!");
152    Reg2IsKill = false;
153    ChangeReg0 = true;
154  }
155
156  // Masks.
157  unsigned MB = MI->getOperand(4).getImm();
158  unsigned ME = MI->getOperand(5).getImm();
159
160  if (NewMI) {
161    // Create a new instruction.
162    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
163    bool Reg0IsDead = MI->getOperand(0).isDead();
164    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
165      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
166      .addReg(Reg2, getKillRegState(Reg2IsKill))
167      .addReg(Reg1, getKillRegState(Reg1IsKill))
168      .addImm((ME+1) & 31)
169      .addImm((MB-1) & 31);
170  }
171
172  if (ChangeReg0)
173    MI->getOperand(0).setReg(Reg2);
174  MI->getOperand(2).setReg(Reg1);
175  MI->getOperand(1).setReg(Reg2);
176  MI->getOperand(2).setIsKill(Reg1IsKill);
177  MI->getOperand(1).setIsKill(Reg2IsKill);
178
179  // Swap the mask around.
180  MI->getOperand(4).setImm((ME+1) & 31);
181  MI->getOperand(5).setImm((MB-1) & 31);
182  return MI;
183}
184
185void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
186                              MachineBasicBlock::iterator MI) const {
187  DebugLoc DL;
188  BuildMI(MBB, MI, DL, get(PPC::NOP));
189}
190
191
192// Branch analysis.
193// Note: If the condition register is set to CTR or CTR8 then this is a
194// BDNZ (imm == 1) or BDZ (imm == 0) branch.
195bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
196                                 MachineBasicBlock *&FBB,
197                                 SmallVectorImpl<MachineOperand> &Cond,
198                                 bool AllowModify) const {
199  bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
200
201  // If the block has no terminators, it just falls into the block after it.
202  MachineBasicBlock::iterator I = MBB.end();
203  if (I == MBB.begin())
204    return false;
205  --I;
206  while (I->isDebugValue()) {
207    if (I == MBB.begin())
208      return false;
209    --I;
210  }
211  if (!isUnpredicatedTerminator(I))
212    return false;
213
214  // Get the last instruction in the block.
215  MachineInstr *LastInst = I;
216
217  // If there is only one terminator instruction, process it.
218  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
219    if (LastInst->getOpcode() == PPC::B) {
220      if (!LastInst->getOperand(0).isMBB())
221        return true;
222      TBB = LastInst->getOperand(0).getMBB();
223      return false;
224    } else if (LastInst->getOpcode() == PPC::BCC) {
225      if (!LastInst->getOperand(2).isMBB())
226        return true;
227      // Block ends with fall-through condbranch.
228      TBB = LastInst->getOperand(2).getMBB();
229      Cond.push_back(LastInst->getOperand(0));
230      Cond.push_back(LastInst->getOperand(1));
231      return false;
232    } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
233               LastInst->getOpcode() == PPC::BDNZ) {
234      if (!LastInst->getOperand(0).isMBB())
235        return true;
236      if (!EnableCTRLoopAnal)
237        return true;
238      TBB = LastInst->getOperand(0).getMBB();
239      Cond.push_back(MachineOperand::CreateImm(1));
240      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
241                                               true));
242      return false;
243    } else if (LastInst->getOpcode() == PPC::BDZ8 ||
244               LastInst->getOpcode() == PPC::BDZ) {
245      if (!LastInst->getOperand(0).isMBB())
246        return true;
247      if (!EnableCTRLoopAnal)
248        return true;
249      TBB = LastInst->getOperand(0).getMBB();
250      Cond.push_back(MachineOperand::CreateImm(0));
251      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
252                                               true));
253      return false;
254    }
255
256    // Otherwise, don't know what this is.
257    return true;
258  }
259
260  // Get the instruction before it if it's a terminator.
261  MachineInstr *SecondLastInst = I;
262
263  // If there are three terminators, we don't know what sort of block this is.
264  if (SecondLastInst && I != MBB.begin() &&
265      isUnpredicatedTerminator(--I))
266    return true;
267
268  // If the block ends with PPC::B and PPC:BCC, handle it.
269  if (SecondLastInst->getOpcode() == PPC::BCC &&
270      LastInst->getOpcode() == PPC::B) {
271    if (!SecondLastInst->getOperand(2).isMBB() ||
272        !LastInst->getOperand(0).isMBB())
273      return true;
274    TBB =  SecondLastInst->getOperand(2).getMBB();
275    Cond.push_back(SecondLastInst->getOperand(0));
276    Cond.push_back(SecondLastInst->getOperand(1));
277    FBB = LastInst->getOperand(0).getMBB();
278    return false;
279  } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
280              SecondLastInst->getOpcode() == PPC::BDNZ) &&
281      LastInst->getOpcode() == PPC::B) {
282    if (!SecondLastInst->getOperand(0).isMBB() ||
283        !LastInst->getOperand(0).isMBB())
284      return true;
285    if (!EnableCTRLoopAnal)
286      return true;
287    TBB = SecondLastInst->getOperand(0).getMBB();
288    Cond.push_back(MachineOperand::CreateImm(1));
289    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
290                                             true));
291    FBB = LastInst->getOperand(0).getMBB();
292    return false;
293  } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
294              SecondLastInst->getOpcode() == PPC::BDZ) &&
295      LastInst->getOpcode() == PPC::B) {
296    if (!SecondLastInst->getOperand(0).isMBB() ||
297        !LastInst->getOperand(0).isMBB())
298      return true;
299    if (!EnableCTRLoopAnal)
300      return true;
301    TBB = SecondLastInst->getOperand(0).getMBB();
302    Cond.push_back(MachineOperand::CreateImm(0));
303    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
304                                             true));
305    FBB = LastInst->getOperand(0).getMBB();
306    return false;
307  }
308
309  // If the block ends with two PPC:Bs, handle it.  The second one is not
310  // executed, so remove it.
311  if (SecondLastInst->getOpcode() == PPC::B &&
312      LastInst->getOpcode() == PPC::B) {
313    if (!SecondLastInst->getOperand(0).isMBB())
314      return true;
315    TBB = SecondLastInst->getOperand(0).getMBB();
316    I = LastInst;
317    if (AllowModify)
318      I->eraseFromParent();
319    return false;
320  }
321
322  // Otherwise, can't handle this.
323  return true;
324}
325
326unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
327  MachineBasicBlock::iterator I = MBB.end();
328  if (I == MBB.begin()) return 0;
329  --I;
330  while (I->isDebugValue()) {
331    if (I == MBB.begin())
332      return 0;
333    --I;
334  }
335  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
336      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
337      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
338    return 0;
339
340  // Remove the branch.
341  I->eraseFromParent();
342
343  I = MBB.end();
344
345  if (I == MBB.begin()) return 1;
346  --I;
347  if (I->getOpcode() != PPC::BCC &&
348      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
349      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
350    return 1;
351
352  // Remove the branch.
353  I->eraseFromParent();
354  return 2;
355}
356
357unsigned
358PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
359                           MachineBasicBlock *FBB,
360                           const SmallVectorImpl<MachineOperand> &Cond,
361                           DebugLoc DL) const {
362  // Shouldn't be a fall through.
363  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
364  assert((Cond.size() == 2 || Cond.size() == 0) &&
365         "PPC branch conditions have two components!");
366
367  bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
368
369  // One-way branch.
370  if (FBB == 0) {
371    if (Cond.empty())   // Unconditional branch
372      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
373    else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
374      BuildMI(&MBB, DL, get(Cond[0].getImm() ?
375                              (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
376                              (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
377    else                // Conditional branch
378      BuildMI(&MBB, DL, get(PPC::BCC))
379        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
380    return 1;
381  }
382
383  // Two-way Conditional Branch.
384  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
385    BuildMI(&MBB, DL, get(Cond[0].getImm() ?
386                            (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
387                            (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
388  else
389    BuildMI(&MBB, DL, get(PPC::BCC))
390      .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
391  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
392  return 2;
393}
394
395void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
396                               MachineBasicBlock::iterator I, DebugLoc DL,
397                               unsigned DestReg, unsigned SrcReg,
398                               bool KillSrc) const {
399  unsigned Opc;
400  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
401    Opc = PPC::OR;
402  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
403    Opc = PPC::OR8;
404  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
405    Opc = PPC::FMR;
406  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
407    Opc = PPC::MCRF;
408  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
409    Opc = PPC::VOR;
410  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
411    Opc = PPC::CROR;
412  else
413    llvm_unreachable("Impossible reg-to-reg copy");
414
415  const MCInstrDesc &MCID = get(Opc);
416  if (MCID.getNumOperands() == 3)
417    BuildMI(MBB, I, DL, MCID, DestReg)
418      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
419  else
420    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
421}
422
423// This function returns true if a CR spill is necessary and false otherwise.
424bool
425PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
426                                  unsigned SrcReg, bool isKill,
427                                  int FrameIdx,
428                                  const TargetRegisterClass *RC,
429                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
430  DebugLoc DL;
431  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
432    if (SrcReg != PPC::LR) {
433      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
434                                         .addReg(SrcReg,
435                                                 getKillRegState(isKill)),
436                                         FrameIdx));
437    } else {
438      // FIXME: this spills LR immediately to memory in one step.  To do this,
439      // we use R11, which we know cannot be used in the prolog/epilog.  This is
440      // a hack.
441      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
442      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
443                                         .addReg(PPC::R11,
444                                                 getKillRegState(isKill)),
445                                         FrameIdx));
446    }
447  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
448    if (SrcReg != PPC::LR8) {
449      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
450                                         .addReg(SrcReg,
451                                                 getKillRegState(isKill)),
452                                         FrameIdx));
453    } else {
454      // FIXME: this spills LR immediately to memory in one step.  To do this,
455      // we use X11, which we know cannot be used in the prolog/epilog.  This is
456      // a hack.
457      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
458      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
459                                         .addReg(PPC::X11,
460                                                 getKillRegState(isKill)),
461                                         FrameIdx));
462    }
463  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
464    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
465                                       .addReg(SrcReg,
466                                               getKillRegState(isKill)),
467                                       FrameIdx));
468  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
469    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
470                                       .addReg(SrcReg,
471                                               getKillRegState(isKill)),
472                                       FrameIdx));
473  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
474    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
475        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
476      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
477                                         .addReg(SrcReg,
478                                                 getKillRegState(isKill)),
479                                         FrameIdx));
480      return true;
481    } else {
482      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
483      // it's possible for the stack frame to be so big the save location is
484      // out of range of immediate offsets, necessitating another register.
485      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
486      // at the moment.
487
488      bool is64Bit = TM.getSubtargetImpl()->isPPC64();
489      // We need to store the CR in the low 4-bits of the saved value.  First,
490      // issue a MFCR to save all of the CRBits.
491      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
492                              (is64Bit ? PPC::X2 : PPC::R2) :
493                              (is64Bit ? PPC::X0 : PPC::R0);
494      NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
495                                             PPC::MFCRpseud), ScratchReg)
496                               .addReg(SrcReg, getKillRegState(isKill)));
497
498      // If the saved register wasn't CR0, shift the bits left so that they are
499      // in CR0's slot.
500      if (SrcReg != PPC::CR0) {
501        unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
502        // rlwinm scratch, scratch, ShiftBits, 0, 31.
503        NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
504                           PPC::RLWINM), ScratchReg)
505                       .addReg(ScratchReg).addImm(ShiftBits)
506                       .addImm(0).addImm(31));
507      }
508
509      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
510                                           PPC::STW8 : PPC::STW))
511                                         .addReg(ScratchReg,
512                                                 getKillRegState(isKill)),
513                                         FrameIdx));
514    }
515  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
516    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
517    // backend currently only uses CR1EQ as an individual bit, this should
518    // not cause any bug. If we need other uses of CR bits, the following
519    // code may be invalid.
520    unsigned Reg = 0;
521    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
522        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
523      Reg = PPC::CR0;
524    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
525             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
526      Reg = PPC::CR1;
527    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
528             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
529      Reg = PPC::CR2;
530    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
531             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
532      Reg = PPC::CR3;
533    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
534             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
535      Reg = PPC::CR4;
536    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
537             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
538      Reg = PPC::CR5;
539    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
540             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
541      Reg = PPC::CR6;
542    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
543             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
544      Reg = PPC::CR7;
545
546    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
547                               &PPC::CRRCRegClass, NewMIs);
548
549  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
550    // We don't have indexed addressing for vector loads.  Emit:
551    // R0 = ADDI FI#
552    // STVX VAL, 0, R0
553    //
554    // FIXME: We use R0 here, because it isn't available for RA.
555    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
556                                       FrameIdx, 0, 0));
557    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
558                     .addReg(SrcReg, getKillRegState(isKill))
559                     .addReg(PPC::R0)
560                     .addReg(PPC::R0));
561  } else {
562    llvm_unreachable("Unknown regclass!");
563  }
564
565  return false;
566}
567
568void
569PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
570                                  MachineBasicBlock::iterator MI,
571                                  unsigned SrcReg, bool isKill, int FrameIdx,
572                                  const TargetRegisterClass *RC,
573                                  const TargetRegisterInfo *TRI) const {
574  MachineFunction &MF = *MBB.getParent();
575  SmallVector<MachineInstr*, 4> NewMIs;
576
577  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
578    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
579    FuncInfo->setSpillsCR();
580  }
581
582  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
583    MBB.insert(MI, NewMIs[i]);
584
585  const MachineFrameInfo &MFI = *MF.getFrameInfo();
586  MachineMemOperand *MMO =
587    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
588                            MachineMemOperand::MOStore,
589                            MFI.getObjectSize(FrameIdx),
590                            MFI.getObjectAlignment(FrameIdx));
591  NewMIs.back()->addMemOperand(MF, MMO);
592}
593
594bool
595PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
596                                   unsigned DestReg, int FrameIdx,
597                                   const TargetRegisterClass *RC,
598                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
599  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
600    if (DestReg != PPC::LR) {
601      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
602                                                 DestReg), FrameIdx));
603    } else {
604      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
605                                                 PPC::R11), FrameIdx));
606      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
607    }
608  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
609    if (DestReg != PPC::LR8) {
610      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
611                                         FrameIdx));
612    } else {
613      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
614                                                 PPC::X11), FrameIdx));
615      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
616    }
617  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
618    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
619                                       FrameIdx));
620  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
621    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
622                                       FrameIdx));
623  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
624    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
625        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
626      NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
627                                                 get(PPC::RESTORE_CR), DestReg)
628                                         , FrameIdx));
629      return true;
630    } else {
631      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
632      // it's possible for the stack frame to be so big the save location is
633      // out of range of immediate offsets, necessitating another register.
634      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
635      // at the moment.
636      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
637                                                            PPC::R2 : PPC::R0;
638      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
639                                         ScratchReg), FrameIdx));
640
641      // If the reloaded register isn't CR0, shift the bits right so that they are
642      // in the right CR's slot.
643      if (DestReg != PPC::CR0) {
644        unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
645        // rlwinm r11, r11, 32-ShiftBits, 0, 31.
646        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
647                      .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
648                      .addImm(31));
649      }
650
651      NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
652                         PPC::MTCRF8 : PPC::MTCRF), DestReg)
653                       .addReg(ScratchReg));
654    }
655  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
656
657    unsigned Reg = 0;
658    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
659        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
660      Reg = PPC::CR0;
661    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
662             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
663      Reg = PPC::CR1;
664    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
665             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
666      Reg = PPC::CR2;
667    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
668             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
669      Reg = PPC::CR3;
670    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
671             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
672      Reg = PPC::CR4;
673    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
674             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
675      Reg = PPC::CR5;
676    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
677             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
678      Reg = PPC::CR6;
679    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
680             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
681      Reg = PPC::CR7;
682
683    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
684                                &PPC::CRRCRegClass, NewMIs);
685
686  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
687    // We don't have indexed addressing for vector loads.  Emit:
688    // R0 = ADDI FI#
689    // Dest = LVX 0, R0
690    //
691    // FIXME: We use R0 here, because it isn't available for RA.
692    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
693                                       FrameIdx, 0, 0));
694    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
695                     .addReg(PPC::R0));
696  } else {
697    llvm_unreachable("Unknown regclass!");
698  }
699
700  return false;
701}
702
703void
704PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
705                                   MachineBasicBlock::iterator MI,
706                                   unsigned DestReg, int FrameIdx,
707                                   const TargetRegisterClass *RC,
708                                   const TargetRegisterInfo *TRI) const {
709  MachineFunction &MF = *MBB.getParent();
710  SmallVector<MachineInstr*, 4> NewMIs;
711  DebugLoc DL;
712  if (MI != MBB.end()) DL = MI->getDebugLoc();
713  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
714    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
715    FuncInfo->setSpillsCR();
716  }
717  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
718    MBB.insert(MI, NewMIs[i]);
719
720  const MachineFrameInfo &MFI = *MF.getFrameInfo();
721  MachineMemOperand *MMO =
722    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
723                            MachineMemOperand::MOLoad,
724                            MFI.getObjectSize(FrameIdx),
725                            MFI.getObjectAlignment(FrameIdx));
726  NewMIs.back()->addMemOperand(MF, MMO);
727}
728
729MachineInstr*
730PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
731                                       int FrameIx, uint64_t Offset,
732                                       const MDNode *MDPtr,
733                                       DebugLoc DL) const {
734  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
735  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
736  return &*MIB;
737}
738
739bool PPCInstrInfo::
740ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
741  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
742  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
743    Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
744  else
745    // Leave the CR# the same, but invert the condition.
746    Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
747  return false;
748}
749
750/// GetInstSize - Return the number of bytes of code the specified
751/// instruction may be.  This returns the maximum number of bytes.
752///
753unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
754  switch (MI->getOpcode()) {
755  case PPC::INLINEASM: {       // Inline Asm: Variable size.
756    const MachineFunction *MF = MI->getParent()->getParent();
757    const char *AsmStr = MI->getOperand(0).getSymbolName();
758    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
759  }
760  case PPC::PROLOG_LABEL:
761  case PPC::EH_LABEL:
762  case PPC::GC_LABEL:
763  case PPC::DBG_VALUE:
764    return 0;
765  case PPC::BL8_NOP_ELF:
766  case PPC::BLA8_NOP_ELF:
767    return 8;
768  default:
769    return 4; // PowerPC instructions are all 4 bytes
770  }
771}
772