PPCInstrInfo.cpp revision 8e5f2c6f65841542e2a7092553fe42a00048e4c7 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33/// getPointerRegClass - Return the register class to use to hold pointers.
34/// This is used for addressing modes.
35const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
36  if (TM.getSubtargetImpl()->isPPC64())
37    return &PPC::G8RCRegClass;
38  else
39    return &PPC::GPRCRegClass;
40}
41
42
43bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
44                               unsigned& sourceReg,
45                               unsigned& destReg) const {
46  unsigned oc = MI.getOpcode();
47  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
49    assert(MI.getNumOperands() >= 3 &&
50           MI.getOperand(0).isRegister() &&
51           MI.getOperand(1).isRegister() &&
52           MI.getOperand(2).isRegister() &&
53           "invalid PPC OR instruction!");
54    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55      sourceReg = MI.getOperand(1).getReg();
56      destReg = MI.getOperand(0).getReg();
57      return true;
58    }
59  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
60    assert(MI.getNumOperands() >= 3 &&
61           MI.getOperand(0).isRegister() &&
62           MI.getOperand(2).isImmediate() &&
63           "invalid PPC ADDI instruction!");
64    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
65      sourceReg = MI.getOperand(1).getReg();
66      destReg = MI.getOperand(0).getReg();
67      return true;
68    }
69  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
70    assert(MI.getNumOperands() >= 3 &&
71           MI.getOperand(0).isRegister() &&
72           MI.getOperand(1).isRegister() &&
73           MI.getOperand(2).isImmediate() &&
74           "invalid PPC ORI instruction!");
75    if (MI.getOperand(2).getImm() == 0) {
76      sourceReg = MI.getOperand(1).getReg();
77      destReg = MI.getOperand(0).getReg();
78      return true;
79    }
80  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
81             oc == PPC::FMRSD) {      // fmr r1, r2
82    assert(MI.getNumOperands() >= 2 &&
83           MI.getOperand(0).isRegister() &&
84           MI.getOperand(1).isRegister() &&
85           "invalid PPC FMR instruction");
86    sourceReg = MI.getOperand(1).getReg();
87    destReg = MI.getOperand(0).getReg();
88    return true;
89  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
90    assert(MI.getNumOperands() >= 2 &&
91           MI.getOperand(0).isRegister() &&
92           MI.getOperand(1).isRegister() &&
93           "invalid PPC MCRF instruction");
94    sourceReg = MI.getOperand(1).getReg();
95    destReg = MI.getOperand(0).getReg();
96    return true;
97  }
98  return false;
99}
100
101unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
102                                           int &FrameIndex) const {
103  switch (MI->getOpcode()) {
104  default: break;
105  case PPC::LD:
106  case PPC::LWZ:
107  case PPC::LFS:
108  case PPC::LFD:
109    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110        MI->getOperand(2).isFI()) {
111      FrameIndex = MI->getOperand(2).getIndex();
112      return MI->getOperand(0).getReg();
113    }
114    break;
115  }
116  return 0;
117}
118
119unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
120                                          int &FrameIndex) const {
121  switch (MI->getOpcode()) {
122  default: break;
123  case PPC::STD:
124  case PPC::STW:
125  case PPC::STFS:
126  case PPC::STFD:
127    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
128        MI->getOperand(2).isFI()) {
129      FrameIndex = MI->getOperand(2).getIndex();
130      return MI->getOperand(0).getReg();
131    }
132    break;
133  }
134  return 0;
135}
136
137// commuteInstruction - We can commute rlwimi instructions, but only if the
138// rotate amt is zero.  We also have to munge the immediates a bit.
139MachineInstr *
140PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
141  MachineFunction &MF = *MI->getParent()->getParent();
142
143  // Normal instructions can be commuted the obvious way.
144  if (MI->getOpcode() != PPC::RLWIMI)
145    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
146
147  // Cannot commute if it has a non-zero rotate count.
148  if (MI->getOperand(3).getImm() != 0)
149    return 0;
150
151  // If we have a zero rotate count, we have:
152  //   M = mask(MB,ME)
153  //   Op0 = (Op1 & ~M) | (Op2 & M)
154  // Change this to:
155  //   M = mask((ME+1)&31, (MB-1)&31)
156  //   Op0 = (Op2 & ~M) | (Op1 & M)
157
158  // Swap op1/op2
159  unsigned Reg0 = MI->getOperand(0).getReg();
160  unsigned Reg1 = MI->getOperand(1).getReg();
161  unsigned Reg2 = MI->getOperand(2).getReg();
162  bool Reg1IsKill = MI->getOperand(1).isKill();
163  bool Reg2IsKill = MI->getOperand(2).isKill();
164  bool ChangeReg0 = false;
165  // If machine instrs are no longer in two-address forms, update
166  // destination register as well.
167  if (Reg0 == Reg1) {
168    // Must be two address instruction!
169    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
170           "Expecting a two-address instruction!");
171    Reg2IsKill = false;
172    ChangeReg0 = true;
173  }
174
175  // Masks.
176  unsigned MB = MI->getOperand(4).getImm();
177  unsigned ME = MI->getOperand(5).getImm();
178
179  if (NewMI) {
180    // Create a new instruction.
181    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
182    bool Reg0IsDead = MI->getOperand(0).isDead();
183    return BuildMI(MF, MI->getDesc())
184      .addReg(Reg0, true, false, false, Reg0IsDead)
185      .addReg(Reg2, false, false, Reg2IsKill)
186      .addReg(Reg1, false, false, Reg1IsKill)
187      .addImm((ME+1) & 31)
188      .addImm((MB-1) & 31);
189  }
190
191  if (ChangeReg0)
192    MI->getOperand(0).setReg(Reg2);
193  MI->getOperand(2).setReg(Reg1);
194  MI->getOperand(1).setReg(Reg2);
195  MI->getOperand(2).setIsKill(Reg1IsKill);
196  MI->getOperand(1).setIsKill(Reg2IsKill);
197
198  // Swap the mask around.
199  MI->getOperand(4).setImm((ME+1) & 31);
200  MI->getOperand(5).setImm((MB-1) & 31);
201  return MI;
202}
203
204void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
205                              MachineBasicBlock::iterator MI) const {
206  BuildMI(MBB, MI, get(PPC::NOP));
207}
208
209
210// Branch analysis.
211bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212                                 MachineBasicBlock *&FBB,
213                                 std::vector<MachineOperand> &Cond) const {
214  // If the block has no terminators, it just falls into the block after it.
215  MachineBasicBlock::iterator I = MBB.end();
216  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
217    return false;
218
219  // Get the last instruction in the block.
220  MachineInstr *LastInst = I;
221
222  // If there is only one terminator instruction, process it.
223  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224    if (LastInst->getOpcode() == PPC::B) {
225      TBB = LastInst->getOperand(0).getMBB();
226      return false;
227    } else if (LastInst->getOpcode() == PPC::BCC) {
228      // Block ends with fall-through condbranch.
229      TBB = LastInst->getOperand(2).getMBB();
230      Cond.push_back(LastInst->getOperand(0));
231      Cond.push_back(LastInst->getOperand(1));
232      return false;
233    }
234    // Otherwise, don't know what this is.
235    return true;
236  }
237
238  // Get the instruction before it if it's a terminator.
239  MachineInstr *SecondLastInst = I;
240
241  // If there are three terminators, we don't know what sort of block this is.
242  if (SecondLastInst && I != MBB.begin() &&
243      isUnpredicatedTerminator(--I))
244    return true;
245
246  // If the block ends with PPC::B and PPC:BCC, handle it.
247  if (SecondLastInst->getOpcode() == PPC::BCC &&
248      LastInst->getOpcode() == PPC::B) {
249    TBB =  SecondLastInst->getOperand(2).getMBB();
250    Cond.push_back(SecondLastInst->getOperand(0));
251    Cond.push_back(SecondLastInst->getOperand(1));
252    FBB = LastInst->getOperand(0).getMBB();
253    return false;
254  }
255
256  // If the block ends with two PPC:Bs, handle it.  The second one is not
257  // executed, so remove it.
258  if (SecondLastInst->getOpcode() == PPC::B &&
259      LastInst->getOpcode() == PPC::B) {
260    TBB = SecondLastInst->getOperand(0).getMBB();
261    I = LastInst;
262    I->eraseFromParent();
263    return false;
264  }
265
266  // Otherwise, can't handle this.
267  return true;
268}
269
270unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
271  MachineBasicBlock::iterator I = MBB.end();
272  if (I == MBB.begin()) return 0;
273  --I;
274  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
275    return 0;
276
277  // Remove the branch.
278  I->eraseFromParent();
279
280  I = MBB.end();
281
282  if (I == MBB.begin()) return 1;
283  --I;
284  if (I->getOpcode() != PPC::BCC)
285    return 1;
286
287  // Remove the branch.
288  I->eraseFromParent();
289  return 2;
290}
291
292unsigned
293PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
294                           MachineBasicBlock *FBB,
295                           const std::vector<MachineOperand> &Cond) const {
296  // Shouldn't be a fall through.
297  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
298  assert((Cond.size() == 2 || Cond.size() == 0) &&
299         "PPC branch conditions have two components!");
300
301  // One-way branch.
302  if (FBB == 0) {
303    if (Cond.empty())   // Unconditional branch
304      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
305    else                // Conditional branch
306      BuildMI(&MBB, get(PPC::BCC))
307        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
308    return 1;
309  }
310
311  // Two-way Conditional Branch.
312  BuildMI(&MBB, get(PPC::BCC))
313    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
314  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
315  return 2;
316}
317
318void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
319                                   MachineBasicBlock::iterator MI,
320                                   unsigned DestReg, unsigned SrcReg,
321                                   const TargetRegisterClass *DestRC,
322                                   const TargetRegisterClass *SrcRC) const {
323  if (DestRC != SrcRC) {
324    cerr << "Not yet supported!";
325    abort();
326  }
327
328  if (DestRC == PPC::GPRCRegisterClass) {
329    BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
330  } else if (DestRC == PPC::G8RCRegisterClass) {
331    BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
332  } else if (DestRC == PPC::F4RCRegisterClass) {
333    BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
334  } else if (DestRC == PPC::F8RCRegisterClass) {
335    BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
336  } else if (DestRC == PPC::CRRCRegisterClass) {
337    BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
338  } else if (DestRC == PPC::VRRCRegisterClass) {
339    BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
340  } else if (DestRC == PPC::CRBITRCRegisterClass) {
341    BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
342  } else {
343    cerr << "Attempt to copy register that is not GPR or FPR";
344    abort();
345  }
346}
347
348bool
349PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
350                                  unsigned SrcReg, bool isKill,
351                                  int FrameIdx,
352                                  const TargetRegisterClass *RC,
353                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
354  if (RC == PPC::GPRCRegisterClass) {
355    if (SrcReg != PPC::LR) {
356      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
357                                         .addReg(SrcReg, false, false, isKill),
358                                         FrameIdx));
359    } else {
360      // FIXME: this spills LR immediately to memory in one step.  To do this,
361      // we use R11, which we know cannot be used in the prolog/epilog.  This is
362      // a hack.
363      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
364      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
365                                         .addReg(PPC::R11, false, false, isKill),
366                                         FrameIdx));
367    }
368  } else if (RC == PPC::G8RCRegisterClass) {
369    if (SrcReg != PPC::LR8) {
370      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
371                              .addReg(SrcReg, false, false, isKill), FrameIdx));
372    } else {
373      // FIXME: this spills LR immediately to memory in one step.  To do this,
374      // we use R11, which we know cannot be used in the prolog/epilog.  This is
375      // a hack.
376      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
377      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
378                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
379    }
380  } else if (RC == PPC::F8RCRegisterClass) {
381    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
382                              .addReg(SrcReg, false, false, isKill), FrameIdx));
383  } else if (RC == PPC::F4RCRegisterClass) {
384    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
385                              .addReg(SrcReg, false, false, isKill), FrameIdx));
386  } else if (RC == PPC::CRRCRegisterClass) {
387    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
388        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
389      // FIXME (64-bit): Enable
390      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
391                                         .addReg(SrcReg, false, false, isKill),
392                                         FrameIdx));
393      return true;
394    } else {
395      // FIXME: We use R0 here, because it isn't available for RA.  We need to
396      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
397      // to save all of the CRBits.
398      NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
399
400      // If the saved register wasn't CR0, shift the bits left so that they are
401      // in CR0's slot.
402      if (SrcReg != PPC::CR0) {
403        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
404        // rlwinm r0, r0, ShiftBits, 0, 31.
405        NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
406                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
407      }
408
409      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
410                                         .addReg(PPC::R0, false, false, isKill),
411                                         FrameIdx));
412    }
413  } else if (RC == PPC::CRBITRCRegisterClass) {
414    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
415    // backend currently only uses CR1EQ as an individual bit, this should
416    // not cause any bug. If we need other uses of CR bits, the following
417    // code may be invalid.
418    unsigned Reg = 0;
419    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
420      Reg = PPC::CR0;
421    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
422      Reg = PPC::CR1;
423    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
424      Reg = PPC::CR2;
425    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
426      Reg = PPC::CR3;
427    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
428      Reg = PPC::CR4;
429    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
430      Reg = PPC::CR5;
431    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
432      Reg = PPC::CR6;
433    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
434      Reg = PPC::CR7;
435
436    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
437                               PPC::CRRCRegisterClass, NewMIs);
438
439  } else if (RC == PPC::VRRCRegisterClass) {
440    // We don't have indexed addressing for vector loads.  Emit:
441    // R0 = ADDI FI#
442    // STVX VAL, 0, R0
443    //
444    // FIXME: We use R0 here, because it isn't available for RA.
445    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
446                                       FrameIdx, 0, 0));
447    NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
448         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
449  } else {
450    assert(0 && "Unknown regclass!");
451    abort();
452  }
453
454  return false;
455}
456
457void
458PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
459                                  MachineBasicBlock::iterator MI,
460                                  unsigned SrcReg, bool isKill, int FrameIdx,
461                                  const TargetRegisterClass *RC) const {
462  MachineFunction &MF = *MBB.getParent();
463  SmallVector<MachineInstr*, 4> NewMIs;
464
465  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
466    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
467    FuncInfo->setSpillsCR();
468  }
469
470  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
471    MBB.insert(MI, NewMIs[i]);
472}
473
474void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
475                                  bool isKill,
476                                  SmallVectorImpl<MachineOperand> &Addr,
477                                  const TargetRegisterClass *RC,
478                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
479  if (Addr[0].isFrameIndex()) {
480    if (StoreRegToStackSlot(MF, SrcReg, isKill,
481                            Addr[0].getIndex(), RC, NewMIs)) {
482      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
483      FuncInfo->setSpillsCR();
484    }
485
486    return;
487  }
488
489  unsigned Opc = 0;
490  if (RC == PPC::GPRCRegisterClass) {
491    Opc = PPC::STW;
492  } else if (RC == PPC::G8RCRegisterClass) {
493    Opc = PPC::STD;
494  } else if (RC == PPC::F8RCRegisterClass) {
495    Opc = PPC::STFD;
496  } else if (RC == PPC::F4RCRegisterClass) {
497    Opc = PPC::STFS;
498  } else if (RC == PPC::VRRCRegisterClass) {
499    Opc = PPC::STVX;
500  } else {
501    assert(0 && "Unknown regclass!");
502    abort();
503  }
504  MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
505    .addReg(SrcReg, false, false, isKill);
506  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
507    MachineOperand &MO = Addr[i];
508    if (MO.isRegister())
509      MIB.addReg(MO.getReg());
510    else if (MO.isImmediate())
511      MIB.addImm(MO.getImm());
512    else
513      MIB.addFrameIndex(MO.getIndex());
514  }
515  NewMIs.push_back(MIB);
516  return;
517}
518
519void
520PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
521                                   unsigned DestReg, int FrameIdx,
522                                   const TargetRegisterClass *RC,
523                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
524  if (RC == PPC::GPRCRegisterClass) {
525    if (DestReg != PPC::LR) {
526      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
527                                         FrameIdx));
528    } else {
529      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
530                                         FrameIdx));
531      NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
532    }
533  } else if (RC == PPC::G8RCRegisterClass) {
534    if (DestReg != PPC::LR8) {
535      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
536                                         FrameIdx));
537    } else {
538      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
539                                         FrameIdx));
540      NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
541    }
542  } else if (RC == PPC::F8RCRegisterClass) {
543    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
544                                       FrameIdx));
545  } else if (RC == PPC::F4RCRegisterClass) {
546    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
547                                       FrameIdx));
548  } else if (RC == PPC::CRRCRegisterClass) {
549    // FIXME: We use R0 here, because it isn't available for RA.
550    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
551                                       FrameIdx));
552
553    // If the reloaded register isn't CR0, shift the bits right so that they are
554    // in the right CR's slot.
555    if (DestReg != PPC::CR0) {
556      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
557      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
558      NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
559                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
560    }
561
562    NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
563  } else if (RC == PPC::CRBITRCRegisterClass) {
564
565    unsigned Reg = 0;
566    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
567      Reg = PPC::CR0;
568    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
569      Reg = PPC::CR1;
570    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
571      Reg = PPC::CR2;
572    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
573      Reg = PPC::CR3;
574    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
575      Reg = PPC::CR4;
576    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
577      Reg = PPC::CR5;
578    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
579      Reg = PPC::CR6;
580    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
581      Reg = PPC::CR7;
582
583    return LoadRegFromStackSlot(MF, Reg, FrameIdx,
584                                PPC::CRRCRegisterClass, NewMIs);
585
586  } else if (RC == PPC::VRRCRegisterClass) {
587    // We don't have indexed addressing for vector loads.  Emit:
588    // R0 = ADDI FI#
589    // Dest = LVX 0, R0
590    //
591    // FIXME: We use R0 here, because it isn't available for RA.
592    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
593                                       FrameIdx, 0, 0));
594    NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
595                     .addReg(PPC::R0));
596  } else {
597    assert(0 && "Unknown regclass!");
598    abort();
599  }
600}
601
602void
603PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
604                                   MachineBasicBlock::iterator MI,
605                                   unsigned DestReg, int FrameIdx,
606                                   const TargetRegisterClass *RC) const {
607  MachineFunction &MF = *MBB.getParent();
608  SmallVector<MachineInstr*, 4> NewMIs;
609  LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
610  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
611    MBB.insert(MI, NewMIs[i]);
612}
613
614void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
615                                   SmallVectorImpl<MachineOperand> &Addr,
616                                   const TargetRegisterClass *RC,
617                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
618  if (Addr[0].isFrameIndex()) {
619    LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
620    return;
621  }
622
623  unsigned Opc = 0;
624  if (RC == PPC::GPRCRegisterClass) {
625    assert(DestReg != PPC::LR && "Can't handle this yet!");
626    Opc = PPC::LWZ;
627  } else if (RC == PPC::G8RCRegisterClass) {
628    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
629    Opc = PPC::LD;
630  } else if (RC == PPC::F8RCRegisterClass) {
631    Opc = PPC::LFD;
632  } else if (RC == PPC::F4RCRegisterClass) {
633    Opc = PPC::LFS;
634  } else if (RC == PPC::VRRCRegisterClass) {
635    Opc = PPC::LVX;
636  } else {
637    assert(0 && "Unknown regclass!");
638    abort();
639  }
640  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
641  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
642    MachineOperand &MO = Addr[i];
643    if (MO.isRegister())
644      MIB.addReg(MO.getReg());
645    else if (MO.isImmediate())
646      MIB.addImm(MO.getImm());
647    else
648      MIB.addFrameIndex(MO.getIndex());
649  }
650  NewMIs.push_back(MIB);
651  return;
652}
653
654/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
655/// copy instructions, turning them into load/store instructions.
656MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
657                                              MachineInstr *MI,
658                                              SmallVectorImpl<unsigned> &Ops,
659                                              int FrameIndex) const {
660  if (Ops.size() != 1) return NULL;
661
662  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
663  // it takes more than one instruction to store it.
664  unsigned Opc = MI->getOpcode();
665  unsigned OpNum = Ops[0];
666
667  MachineInstr *NewMI = NULL;
668  if ((Opc == PPC::OR &&
669       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
670    if (OpNum == 0) {  // move -> store
671      unsigned InReg = MI->getOperand(1).getReg();
672      bool isKill = MI->getOperand(1).isKill();
673      NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
674                                .addReg(InReg, false, false, isKill),
675                                FrameIndex);
676    } else {           // move -> load
677      unsigned OutReg = MI->getOperand(0).getReg();
678      bool isDead = MI->getOperand(0).isDead();
679      NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
680                                .addReg(OutReg, true, false, false, isDead),
681                                FrameIndex);
682    }
683  } else if ((Opc == PPC::OR8 &&
684              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
685    if (OpNum == 0) {  // move -> store
686      unsigned InReg = MI->getOperand(1).getReg();
687      bool isKill = MI->getOperand(1).isKill();
688      NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
689                                .addReg(InReg, false, false, isKill),
690                                FrameIndex);
691    } else {           // move -> load
692      unsigned OutReg = MI->getOperand(0).getReg();
693      bool isDead = MI->getOperand(0).isDead();
694      NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
695                                .addReg(OutReg, true, false, false, isDead),
696                                FrameIndex);
697    }
698  } else if (Opc == PPC::FMRD) {
699    if (OpNum == 0) {  // move -> store
700      unsigned InReg = MI->getOperand(1).getReg();
701      bool isKill = MI->getOperand(1).isKill();
702      NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
703                                .addReg(InReg, false, false, isKill),
704                                FrameIndex);
705    } else {           // move -> load
706      unsigned OutReg = MI->getOperand(0).getReg();
707      bool isDead = MI->getOperand(0).isDead();
708      NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
709                                .addReg(OutReg, true, false, false, isDead),
710                                FrameIndex);
711    }
712  } else if (Opc == PPC::FMRS) {
713    if (OpNum == 0) {  // move -> store
714      unsigned InReg = MI->getOperand(1).getReg();
715      bool isKill = MI->getOperand(1).isKill();
716      NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
717                                .addReg(InReg, false, false, isKill),
718                                FrameIndex);
719    } else {           // move -> load
720      unsigned OutReg = MI->getOperand(0).getReg();
721      bool isDead = MI->getOperand(0).isDead();
722      NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
723                                .addReg(OutReg, true, false, false, isDead),
724                                FrameIndex);
725    }
726  }
727
728  return NewMI;
729}
730
731bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
732                                        SmallVectorImpl<unsigned> &Ops) const {
733  if (Ops.size() != 1) return false;
734
735  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
736  // it takes more than one instruction to store it.
737  unsigned Opc = MI->getOpcode();
738
739  if ((Opc == PPC::OR &&
740       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
741    return true;
742  else if ((Opc == PPC::OR8 &&
743              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
744    return true;
745  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
746    return true;
747
748  return false;
749}
750
751
752bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
753  if (MBB.empty()) return false;
754
755  switch (MBB.back().getOpcode()) {
756  case PPC::BLR:   // Return.
757  case PPC::B:     // Uncond branch.
758  case PPC::BCTR:  // Indirect branch.
759    return true;
760  default: return false;
761  }
762}
763
764bool PPCInstrInfo::
765ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
766  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
767  // Leave the CR# the same, but invert the condition.
768  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
769  return false;
770}
771
772/// GetInstSize - Return the number of bytes of code the specified
773/// instruction may be.  This returns the maximum number of bytes.
774///
775unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
776  switch (MI->getOpcode()) {
777  case PPC::INLINEASM: {       // Inline Asm: Variable size.
778    const MachineFunction *MF = MI->getParent()->getParent();
779    const char *AsmStr = MI->getOperand(0).getSymbolName();
780    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
781  }
782  case PPC::DBG_LABEL:
783  case PPC::EH_LABEL:
784  case PPC::GC_LABEL:
785    return 0;
786  default:
787    return 4; // PowerPC instructions are all 4 bytes
788  }
789}
790