PPCInstrInfo.cpp revision 880d0f6018b6928bdcad291be60c801238619955
121e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1416e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCInstrInfo.h" 15f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson#include "PPCInstrBuilder.h" 167194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "PPCMachineFunctionInfo.h" 17df4ed6350b2a51f71c0980e86c9078f4046ea706Chris Lattner#include "PPCPredicates.h" 184c7b43b43fdf943c7298718e15ab5d6dfe345be7Chris Lattner#include "PPCGenInstrInfo.inc" 19b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner#include "PPCTargetMachine.h" 20718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 21f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 22880d0f6018b6928bdcad291be60c801238619955Bill Wendling#include "llvm/Support/CommandLine.h" 23f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanusing namespace llvm; 24f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 25880d0f6018b6928bdcad291be60c801238619955Bill Wendlingextern cl::opt<bool> EnablePPCRS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 26880d0f6018b6928bdcad291be60c801238619955Bill Wendling 27b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris LattnerPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 28641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 297ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng RI(*TM.getSubtargetImpl(), *this) {} 30b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 31b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner/// getPointerRegClass - Return the register class to use to hold pointers. 32b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner/// This is used for addressing modes. 33b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattnerconst TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { 34b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner if (TM.getSubtargetImpl()->isPPC64()) 35b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner return &PPC::G8RCRegClass; 36b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner else 37b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner return &PPC::GPRCRegClass; 38b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner} 39b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 40f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 4121e463b2bf864671a87ebe386cb100ef9349a540Nate Begemanbool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 4221e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman unsigned& sourceReg, 4321e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman unsigned& destReg) const { 44cc8cd0cbf12c12916d4b38ef0de5be5501c8270eChris Lattner unsigned oc = MI.getOpcode(); 45b410dc99774d52b4491750dab10b91cca1d661d8Chris Lattner if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 4614c09b81ead8fe8b754fca2d0a8237cb810b37d6Chris Lattner oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 471e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 48f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 49f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(1).isRegister() && 50f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(2).isRegister() && 51f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC OR instruction!"); 52f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 53f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 54f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 55f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 56f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 57f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } else if (oc == PPC::ADDI) { // addi r1, r2, 0 581e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 59f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 60f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(2).isImmediate() && 61f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC ADDI instruction!"); 629a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) { 63f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 64f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 65f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 66f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 67cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } else if (oc == PPC::ORI) { // ori r1, r2, 0 681e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 69cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(0).isRegister() && 70cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(1).isRegister() && 71cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(2).isImmediate() && 72cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman "invalid PPC ORI instruction!"); 739a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI.getOperand(2).getImm() == 0) { 74cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman sourceReg = MI.getOperand(1).getReg(); 75cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman destReg = MI.getOperand(0).getReg(); 76cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman return true; 77cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } 78eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2Chris Lattner } else if (oc == PPC::FMRS || oc == PPC::FMRD || 79eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2Chris Lattner oc == PPC::FMRSD) { // fmr r1, r2 801e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 81f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 82f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(1).isRegister() && 83f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC FMR instruction"); 84f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 85f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 86f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 877af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 881e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 897af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman MI.getOperand(0).isRegister() && 907af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman MI.getOperand(1).isRegister() && 917af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman "invalid PPC MCRF instruction"); 927af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman sourceReg = MI.getOperand(1).getReg(); 937af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman destReg = MI.getOperand(0).getReg(); 947af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman return true; 95f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 96f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return false; 97f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 98043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 99408396014742a05cad1c91949d2226169e3f9d80Chris Lattnerunsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 1009c09c9ec9dab61450800b42cbf746164aa076b88Chris Lattner int &FrameIndex) const { 101408396014742a05cad1c91949d2226169e3f9d80Chris Lattner switch (MI->getOpcode()) { 102408396014742a05cad1c91949d2226169e3f9d80Chris Lattner default: break; 103408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LD: 104408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LWZ: 105408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFS: 106408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFD: 1078aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 1088aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner MI->getOperand(2).isFI()) { 1098aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 110408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return MI->getOperand(0).getReg(); 111408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 112408396014742a05cad1c91949d2226169e3f9d80Chris Lattner break; 113408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 114408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return 0; 1156524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 116408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 1176524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattnerunsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 1186524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner int &FrameIndex) const { 1196524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner switch (MI->getOpcode()) { 1206524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner default: break; 1213b478b31e297208ef2c9f74750a8a603eb3726fbNate Begeman case PPC::STD: 1226524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STW: 1236524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFS: 1246524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFD: 1258aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 1268aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner MI->getOperand(2).isFI()) { 1278aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 1286524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return MI->getOperand(0).getReg(); 1296524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1306524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner break; 1316524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1326524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return 0; 1336524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 134408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 135043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// commuteInstruction - We can commute rlwimi instructions, but only if the 136043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// rotate amt is zero. We also have to munge the immediates a bit. 13721e463b2bf864671a87ebe386cb100ef9349a540Nate BegemanMachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 138043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Normal instructions can be commuted the obvious way. 139043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner if (MI->getOpcode() != PPC::RLWIMI) 140264e6fec9f3962cb269031d6d84cee9f896e0286Chris Lattner return TargetInstrInfoImpl::commuteInstruction(MI); 141043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 142043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Cannot commute if it has a non-zero rotate count. 1439a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI->getOperand(3).getImm() != 0) 144043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return 0; 145043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 146043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // If we have a zero rotate count, we have: 147043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask(MB,ME) 148043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op1 & ~M) | (Op2 & M) 149043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Change this to: 150043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask((ME+1)&31, (MB-1)&31) 151043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op2 & ~M) | (Op1 & M) 152043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 153043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap op1/op2 154a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng unsigned Reg0 = MI->getOperand(0).getReg(); 155043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 156043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 1576ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg1IsKill = MI->getOperand(1).isKill(); 1586ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg2IsKill = MI->getOperand(2).isKill(); 159a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // If machine instrs are no longer in two-address forms, update 160a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // destination register as well. 161a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng if (Reg0 == Reg1) { 162a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 163a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 164a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 165a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng MI->getOperand(0).setReg(Reg2); 166a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 167a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 168e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(2).setReg(Reg1); 169e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(1).setReg(Reg2); 170f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 171f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 172043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 173043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap the mask around. 1749a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner unsigned MB = MI->getOperand(4).getImm(); 1759a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner unsigned ME = MI->getOperand(5).getImm(); 1769a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(4).setImm((ME+1) & 31); 1779a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(5).setImm((MB-1) & 31); 178043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return MI; 179043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner} 180bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 181bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattnervoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 182bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const { 183c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, MI, get(PPC::NOP)); 184bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner} 185c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 186c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 187c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner// Branch analysis. 188c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 189c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 190c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner std::vector<MachineOperand> &Cond) const { 191c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If the block has no terminators, it just falls into the block after it. 192c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 193bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 194c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 195c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 196c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the last instruction in the block. 197c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *LastInst = I; 198c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 199c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there is only one terminator instruction, process it. 200bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 201c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (LastInst->getOpcode() == PPC::B) { 2028aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(0).getMBB(); 203c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 204289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner } else if (LastInst->getOpcode() == PPC::BCC) { 205c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Block ends with fall-through condbranch. 2068aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(2).getMBB(); 207c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(0)); 208c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(1)); 2097c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 210c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 211c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, don't know what this is. 212c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 213c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 214c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 215c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the instruction before it if it's a terminator. 216c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *SecondLastInst = I; 217c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 218c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there are three terminators, we don't know what sort of block this is. 219c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (SecondLastInst && I != MBB.begin() && 220bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng isUnpredicatedTerminator(--I)) 221c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 222c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 223289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner // If the block ends with PPC::B and PPC:BCC, handle it. 224289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (SecondLastInst->getOpcode() == PPC::BCC && 225c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner LastInst->getOpcode() == PPC::B) { 2268aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(2).getMBB(); 227c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(0)); 228c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(1)); 2298aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FBB = LastInst->getOperand(0).getMBB(); 230c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 231c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 232c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 23313e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // If the block ends with two PPC:Bs, handle it. The second one is not 23413e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // executed, so remove it. 23513e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen if (SecondLastInst->getOpcode() == PPC::B && 23613e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen LastInst->getOpcode() == PPC::B) { 2378aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(0).getMBB(); 23813e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I = LastInst; 23913e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I->eraseFromParent(); 24013e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen return false; 24113e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen } 24213e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen 243c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, can't handle this. 244c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 245c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 246c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 247b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 248c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 249b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 0; 250c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 251289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 252b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 253c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 254c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 255c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 256c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 257c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I = MBB.end(); 258c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 259b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 1; 260c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 261289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::BCC) 262b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 263c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 264c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 265c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 266b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 267c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 268c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 269b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned 270b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan ChengPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 271b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 272b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng const std::vector<MachineOperand> &Cond) const { 2732dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner // Shouldn't be a fall through. 2742dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 27554108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner assert((Cond.size() == 2 || Cond.size() == 0) && 27654108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner "PPC branch conditions have two components!"); 2772dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner 27854108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner // One-way branch. 2792dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner if (FBB == 0) { 28054108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner if (Cond.empty()) // Unconditional branch 281c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::B)).addMBB(TBB); 28254108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner else // Conditional branch 283c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::BCC)) 28418258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 285b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 2862dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner } 287c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 288879d09cf130f3760a08865913c04d9ff328fad5fChris Lattner // Two-way Conditional Branch. 289c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::BCC)) 29018258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 291c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::B)).addMBB(FBB); 292b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 293c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 294c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 295d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Andersonvoid PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 296d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 297d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 298d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 299d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 300d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 301d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson cerr << "Not yet supported!"; 302d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson abort(); 303d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 304d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 305d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == PPC::GPRCRegisterClass) { 306d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 307d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::G8RCRegisterClass) { 308d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 309d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::F4RCRegisterClass) { 310d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); 311d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::F8RCRegisterClass) { 312d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); 313d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::CRRCRegisterClass) { 314d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); 315d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::VRRCRegisterClass) { 316d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 317d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else { 318d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson cerr << "Attempt to copy register that is not GPR or FPR"; 319d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson abort(); 320d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 321d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 322d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 3237194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingstatic bool StoreRegToStackSlot(const TargetInstrInfo &TII, 324f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIdx, 325f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 326880d0f6018b6928bdcad291be60c801238619955Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) { 327f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 328f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR) { 329f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 330f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 331f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 332f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 333f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 334f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 335f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11)); 336f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 337f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R11, false, false, isKill), FrameIdx)); 338f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 339f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 340f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR8) { 341f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 342f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 343f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 344f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 345f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 346f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 347f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11)); 348f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 349f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::X11, false, false, isKill), FrameIdx)); 350f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 351f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 352f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD)) 353f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 354f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 355f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) 356f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 357f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 358880d0f6018b6928bdcad291be60c801238619955Bill Wendling if (EnablePPCRS) { // FIXME (64-bit): Enable 3597194aaf738a1b89441635340403f1c5b06ae18efBill Wendling NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) 3607194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addReg(SrcReg, false, false, isKill), 3617194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIdx)); 3627194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return true; 3637194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } else { 3647194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // FIXME: We use R0 here, because it isn't available for RA. We need to 3657194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // store the CR in the low 4-bits of the saved value. First, issue a MFCR 3667194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // to save all of the CRBits. 3677194aaf738a1b89441635340403f1c5b06ae18efBill Wendling NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); 368f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 3697194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // If the saved register wasn't CR0, shift the bits left so that they are 3707194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // in CR0's slot. 3717194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (SrcReg != PPC::CR0) { 3727194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 3737194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // rlwinm r0, r0, ShiftBits, 0, 31. 3747194aaf738a1b89441635340403f1c5b06ae18efBill Wendling NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 3757194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); 3767194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 377f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 3787194aaf738a1b89441635340403f1c5b06ae18efBill Wendling NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 3797194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addReg(PPC::R0, false, false, isKill), 3807194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIdx)); 3817194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 382f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 383f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 384f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 385f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // STVX VAL, 0, R0 386f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 387f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 388f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 389f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 390f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::STVX)) 391f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); 392f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 393f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 394f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 395f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 3967194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return false; 398f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 399f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 400f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 401f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 4027194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 4037194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned SrcReg, bool isKill, int FrameIdx, 4047194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC) const { 405f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 4067194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 407880d0f6018b6928bdcad291be60c801238619955Bill Wendling if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 4087194aaf738a1b89441635340403f1c5b06ae18efBill Wendling PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>(); 4097194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FuncInfo->setSpillsCR(); 4107194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 4117194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 412f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 413f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 414f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 415f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 416f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 4177194aaf738a1b89441635340403f1c5b06ae18efBill Wendling bool isKill, 4187194aaf738a1b89441635340403f1c5b06ae18efBill Wendling SmallVectorImpl<MachineOperand> &Addr, 4197194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC, 4207194aaf738a1b89441635340403f1c5b06ae18efBill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const{ 421f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (Addr[0].isFrameIndex()) { 422880d0f6018b6928bdcad291be60c801238619955Bill Wendling if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), 423880d0f6018b6928bdcad291be60c801238619955Bill Wendling RC, NewMIs)) { 4247194aaf738a1b89441635340403f1c5b06ae18efBill Wendling PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 4257194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FuncInfo->setSpillsCR(); 4267194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 4277194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 428f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 429f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 430f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 431f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 432f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 433f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STW; 434f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 435f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STD; 436f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 437f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STFD; 438f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 439f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STFS; 440f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 441f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STVX; 442f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 443f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 444f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 445f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 446f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineInstrBuilder MIB = BuildMI(get(Opc)) 447f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 448f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 449f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 450f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (MO.isRegister()) 451f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 452f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (MO.isImmediate()) 453f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 454f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 455f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 456f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 457f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 458f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 459f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 460f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 461f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonstatic void LoadRegFromStackSlot(const TargetInstrInfo &TII, 462f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIdx, 463f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 464f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) { 465f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 466f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR) { 467f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg), 468f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 469f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 470f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11), 471f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 472f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11)); 473f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 474f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 475f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR8) { 476f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg), 477f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 478f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 479f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11), 480f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 481f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11)); 482f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 483f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 484f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg), 485f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 486f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 487f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg), 488f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 489f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 490f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 491f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0), 492f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 493f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 494f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // If the reloaded register isn't CR0, shift the bits right so that they are 495f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // in the right CR's slot. 496f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::CR0) { 497f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 498f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // rlwinm r11, r11, 32-ShiftBits, 0, 31. 499f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 500f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); 501f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 502f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 503f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0)); 504f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 505f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 506f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 507f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // Dest = LVX 0, R0 508f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 509f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 510f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 511f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 512f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0) 513f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0)); 514f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 515f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 516f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 517f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 518f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 519f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 520f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 521f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 5227194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 5237194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned DestReg, int FrameIdx, 5247194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC) const { 525f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 526f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs); 527f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 528f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 529f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 530f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 531f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 5327194aaf738a1b89441635340403f1c5b06ae18efBill Wendling SmallVectorImpl<MachineOperand> &Addr, 5337194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC, 5347194aaf738a1b89441635340403f1c5b06ae18efBill Wendling SmallVectorImpl<MachineInstr*> &NewMIs)const{ 535f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (Addr[0].isFrameIndex()) { 536f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs); 537f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 538f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 539f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 540f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 541f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 542f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(DestReg != PPC::LR && "Can't handle this yet!"); 543f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LWZ; 544f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 545f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(DestReg != PPC::LR8 && "Can't handle this yet!"); 546f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LD; 547f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 548f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LFD; 549f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 550f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LFS; 551f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 552f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LVX; 553f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 554f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 555f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 556f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 557f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); 558f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 559f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 560f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (MO.isRegister()) 561f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 562f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (MO.isImmediate()) 563f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 564f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 565f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 566f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 567f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 568f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 569f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 570f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 57143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 57243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// copy instructions, turning them into load/store instructions. 5735fd79d0560570fed977788a86fa038b898564dfaEvan ChengMachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, 5745fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr *MI, 57543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<unsigned> &Ops, 57643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson int FrameIndex) const { 57743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 57843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 57943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 58043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 58143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 58243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 58343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 58443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 58543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 58643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 58743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 58843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 58943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg), 59043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 59143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 59243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 59343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg), 59443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 59543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 59643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if ((Opc == PPC::OR8 && 59743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 59843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 59943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 60043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg), 60143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 60243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 60343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 60443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex); 60543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 60643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if (Opc == PPC::FMRD) { 60743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 60843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 60943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg), 61043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 61143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 61243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 61343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex); 61443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 61543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if (Opc == PPC::FMRS) { 61643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 61743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 61843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg), 61943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 62043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 62143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 62243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex); 62343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 62443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 62543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 62643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (NewMI) 62743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI->copyKillDeadInfo(MI); 62843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 62943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 63043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 63143dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonbool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI, 6325fd79d0560570fed977788a86fa038b898564dfaEvan Cheng SmallVectorImpl<unsigned> &Ops) const { 63343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return false; 63443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 63543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 63643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 63743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 63843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 63943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 64043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 64143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 64243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else if ((Opc == PPC::OR8 && 64343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 64443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 64543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else if (Opc == PPC::FMRD || Opc == PPC::FMRS) 64643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 64743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 64843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 64943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 65043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 651f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 652ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattnerbool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 653ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner if (MBB.empty()) return false; 654ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner 655ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner switch (MBB.back().getOpcode()) { 656126f17a17625876adb63f06d043fc1b1e4f0361cEvan Cheng case PPC::BLR: // Return. 657ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner case PPC::B: // Uncond branch. 658ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner case PPC::BCTR: // Indirect branch. 659ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner return true; 660ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner default: return false; 661ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner } 662ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner} 663ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner 664c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo:: 665c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris LattnerReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 6667c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 6677c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner // Leave the CR# the same, but invert the condition. 66818258c640466274c26e89016e361ec411ff78520Chris Lattner Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 6697c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 670c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 671