PPCInstrInfo.cpp revision cc8cd0cbf12c12916d4b38ef0de5be5501c8270e
121e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1416e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCInstrInfo.h" 15f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson#include "PPCInstrBuilder.h" 16df4ed6350b2a51f71c0980e86c9078f4046ea706Chris Lattner#include "PPCPredicates.h" 174c7b43b43fdf943c7298718e15ab5d6dfe345be7Chris Lattner#include "PPCGenInstrInfo.inc" 18b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner#include "PPCTargetMachine.h" 19718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 20f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 21f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukmanusing namespace llvm; 22f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 23b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris LattnerPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 24641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 257ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng RI(*TM.getSubtargetImpl(), *this) {} 26b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 27b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner/// getPointerRegClass - Return the register class to use to hold pointers. 28b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner/// This is used for addressing modes. 29b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattnerconst TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { 30b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner if (TM.getSubtargetImpl()->isPPC64()) 31b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner return &PPC::G8RCRegClass; 32b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner else 33b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner return &PPC::GPRCRegClass; 34b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner} 35b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 36f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 3721e463b2bf864671a87ebe386cb100ef9349a540Nate Begemanbool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 3821e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman unsigned& sourceReg, 3921e463b2bf864671a87ebe386cb100ef9349a540Nate Begeman unsigned& destReg) const { 40cc8cd0cbf12c12916d4b38ef0de5be5501c8270eChris Lattner unsigned oc = MI.getOpcode(); 41b410dc99774d52b4491750dab10b91cca1d661d8Chris Lattner if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 4214c09b81ead8fe8b754fca2d0a8237cb810b37d6Chris Lattner oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 431e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 44f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 45f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(1).isRegister() && 46f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(2).isRegister() && 47f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC OR instruction!"); 48f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 49f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 50f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 51f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 52f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 53f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } else if (oc == PPC::ADDI) { // addi r1, r2, 0 541e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 55f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 56f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(2).isImmediate() && 57f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC ADDI instruction!"); 589a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) { 59f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 60f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 61f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 62f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 63cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } else if (oc == PPC::ORI) { // ori r1, r2, 0 641e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 3 && 65cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(0).isRegister() && 66cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(1).isRegister() && 67cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman MI.getOperand(2).isImmediate() && 68cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman "invalid PPC ORI instruction!"); 699a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI.getOperand(2).getImm() == 0) { 70cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman sourceReg = MI.getOperand(1).getReg(); 71cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman destReg = MI.getOperand(0).getReg(); 72cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman return true; 73cb90de37a720b0b00d6303b49b8df6d5ac5f34f9Nate Begeman } 74eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2Chris Lattner } else if (oc == PPC::FMRS || oc == PPC::FMRD || 75eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2Chris Lattner oc == PPC::FMRSD) { // fmr r1, r2 761e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 77f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(0).isRegister() && 78f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MI.getOperand(1).isRegister() && 79f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman "invalid PPC FMR instruction"); 80f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman sourceReg = MI.getOperand(1).getReg(); 81f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman destReg = MI.getOperand(0).getReg(); 82f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return true; 837af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 841e341729dd003ca33ecea4abf13134f20062c5f8Evan Cheng assert(MI.getNumOperands() >= 2 && 857af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman MI.getOperand(0).isRegister() && 867af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman MI.getOperand(1).isRegister() && 877af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman "invalid PPC MCRF instruction"); 887af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman sourceReg = MI.getOperand(1).getReg(); 897af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman destReg = MI.getOperand(0).getReg(); 907af0248af47fbd86ec65d308adda22ec367accc4Nate Begeman return true; 91f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 92f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman return false; 93f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 94043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 95408396014742a05cad1c91949d2226169e3f9d80Chris Lattnerunsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 969c09c9ec9dab61450800b42cbf746164aa076b88Chris Lattner int &FrameIndex) const { 97408396014742a05cad1c91949d2226169e3f9d80Chris Lattner switch (MI->getOpcode()) { 98408396014742a05cad1c91949d2226169e3f9d80Chris Lattner default: break; 99408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LD: 100408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LWZ: 101408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFS: 102408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFD: 1038aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 1048aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner MI->getOperand(2).isFI()) { 1058aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 106408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return MI->getOperand(0).getReg(); 107408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 108408396014742a05cad1c91949d2226169e3f9d80Chris Lattner break; 109408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 110408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return 0; 1116524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 112408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 1136524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattnerunsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 1146524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner int &FrameIndex) const { 1156524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner switch (MI->getOpcode()) { 1166524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner default: break; 1173b478b31e297208ef2c9f74750a8a603eb3726fbNate Begeman case PPC::STD: 1186524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STW: 1196524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFS: 1206524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFD: 1218aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 1228aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner MI->getOperand(2).isFI()) { 1238aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 1246524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return MI->getOperand(0).getReg(); 1256524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1266524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner break; 1276524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1286524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return 0; 1296524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 130408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 131043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// commuteInstruction - We can commute rlwimi instructions, but only if the 132043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// rotate amt is zero. We also have to munge the immediates a bit. 13321e463b2bf864671a87ebe386cb100ef9349a540Nate BegemanMachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 134043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Normal instructions can be commuted the obvious way. 135043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner if (MI->getOpcode() != PPC::RLWIMI) 136264e6fec9f3962cb269031d6d84cee9f896e0286Chris Lattner return TargetInstrInfoImpl::commuteInstruction(MI); 137043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 138043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Cannot commute if it has a non-zero rotate count. 1399a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI->getOperand(3).getImm() != 0) 140043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return 0; 141043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 142043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // If we have a zero rotate count, we have: 143043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask(MB,ME) 144043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op1 & ~M) | (Op2 & M) 145043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Change this to: 146043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask((ME+1)&31, (MB-1)&31) 147043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op2 & ~M) | (Op1 & M) 148043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 149043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap op1/op2 150043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 151043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 1526ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg1IsKill = MI->getOperand(1).isKill(); 1536ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg2IsKill = MI->getOperand(2).isKill(); 154e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(2).setReg(Reg1); 155e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(1).setReg(Reg2); 156f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 157f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 158043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 159043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap the mask around. 1609a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner unsigned MB = MI->getOperand(4).getImm(); 1619a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner unsigned ME = MI->getOperand(5).getImm(); 1629a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(4).setImm((ME+1) & 31); 1639a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(5).setImm((MB-1) & 31); 164043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return MI; 165043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner} 166bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 167bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattnervoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 168bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const { 169c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(MBB, MI, get(PPC::NOP)); 170bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner} 171c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 172c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 173c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner// Branch analysis. 174c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 175c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 176c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner std::vector<MachineOperand> &Cond) const { 177c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If the block has no terminators, it just falls into the block after it. 178c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 179bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) 180c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 181c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 182c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the last instruction in the block. 183c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *LastInst = I; 184c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 185c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there is only one terminator instruction, process it. 186bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 187c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (LastInst->getOpcode() == PPC::B) { 1888aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(0).getMBB(); 189c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 190289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner } else if (LastInst->getOpcode() == PPC::BCC) { 191c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Block ends with fall-through condbranch. 1928aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(2).getMBB(); 193c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(0)); 194c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(1)); 1957c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 196c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 197c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, don't know what this is. 198c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 199c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 200c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 201c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the instruction before it if it's a terminator. 202c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *SecondLastInst = I; 203c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 204c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there are three terminators, we don't know what sort of block this is. 205c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (SecondLastInst && I != MBB.begin() && 206bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng isUnpredicatedTerminator(--I)) 207c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 208c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 209289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner // If the block ends with PPC::B and PPC:BCC, handle it. 210289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (SecondLastInst->getOpcode() == PPC::BCC && 211c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner LastInst->getOpcode() == PPC::B) { 2128aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(2).getMBB(); 213c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(0)); 214c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(1)); 2158aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FBB = LastInst->getOperand(0).getMBB(); 216c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 217c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 218c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 21913e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // If the block ends with two PPC:Bs, handle it. The second one is not 22013e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // executed, so remove it. 22113e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen if (SecondLastInst->getOpcode() == PPC::B && 22213e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen LastInst->getOpcode() == PPC::B) { 2238aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(0).getMBB(); 22413e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I = LastInst; 22513e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I->eraseFromParent(); 22613e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen return false; 22713e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen } 22813e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen 229c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, can't handle this. 230c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 231c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 232c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 233b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 234c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 235b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 0; 236c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 237289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 238b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 239c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 240c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 241c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 242c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 243c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I = MBB.end(); 244c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 245b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 1; 246c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 247289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::BCC) 248b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 249c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 250c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 251c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 252b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 253c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 254c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 255b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned 256b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan ChengPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 257b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 258b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng const std::vector<MachineOperand> &Cond) const { 2592dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner // Shouldn't be a fall through. 2602dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 26154108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner assert((Cond.size() == 2 || Cond.size() == 0) && 26254108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner "PPC branch conditions have two components!"); 2632dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner 26454108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner // One-way branch. 2652dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner if (FBB == 0) { 26654108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner if (Cond.empty()) // Unconditional branch 267c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::B)).addMBB(TBB); 26854108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner else // Conditional branch 269c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::BCC)) 27018258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 271b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 2722dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner } 273c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 274879d09cf130f3760a08865913c04d9ff328fad5fChris Lattner // Two-way Conditional Branch. 275c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::BCC)) 27618258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 277c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(PPC::B)).addMBB(FBB); 278b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 279c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 280c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 281d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Andersonvoid PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 282d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 283d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 284d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 285d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 286d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 287d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson cerr << "Not yet supported!"; 288d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson abort(); 289d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 290d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 291d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == PPC::GPRCRegisterClass) { 292d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 293d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::G8RCRegisterClass) { 294d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 295d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::F4RCRegisterClass) { 296d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); 297d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::F8RCRegisterClass) { 298d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); 299d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::CRRCRegisterClass) { 300d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); 301d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else if (DestRC == PPC::VRRCRegisterClass) { 302d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 303d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } else { 304d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson cerr << "Attempt to copy register that is not GPR or FPR"; 305d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson abort(); 306d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 307d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 308d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 309f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonstatic void StoreRegToStackSlot(const TargetInstrInfo &TII, 310f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIdx, 311f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 312f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) { 313f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 314f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR) { 315f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 316f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 317f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 318f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 319f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 320f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 321f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11)); 322f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 323f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R11, false, false, isKill), FrameIdx)); 324f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 325f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 326f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR8) { 327f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 328f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 329f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 330f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 331f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 332f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 333f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11)); 334f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 335f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::X11, false, false, isKill), FrameIdx)); 336f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 337f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 338f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD)) 339f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 340f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 341f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) 342f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill), FrameIdx)); 343f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 344f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 345f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We need to store the CR in the low 4-bits of the saved value. First, 346f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // issue a MFCR to save all of the CRBits. 347f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); 348f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 349f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // If the saved register wasn't CR0, shift the bits left so that they are in 350f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // CR0's slot. 351f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::CR0) { 352f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 353f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // rlwinm r0, r0, ShiftBits, 0, 31. 354f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 355f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); 356f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 357f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 358f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 359f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0, false, false, isKill), FrameIdx)); 360f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 361f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 362f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 363f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // STVX VAL, 0, R0 364f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 365f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 366f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 367f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 368f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::STVX)) 369f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); 370f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 371f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 372f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 373f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 374f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 375f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 376f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 377f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 378f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 379f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIdx, 380f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 381f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 382f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs); 383f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 384f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 385f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 386f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 387f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 388f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson bool isKill, 389f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 390f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 391f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 392f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (Addr[0].isFrameIndex()) { 393f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs); 394f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 395f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 396f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 397f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 398f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 399f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STW; 400f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 401f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STD; 402f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 403f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STFD; 404f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 405f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STFS; 406f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 407f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::STVX; 408f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 409f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 410f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 411f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 412f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineInstrBuilder MIB = BuildMI(get(Opc)) 413f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 414f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 415f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 416f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (MO.isRegister()) 417f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 418f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (MO.isImmediate()) 419f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 420f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 421f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 422f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 423f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 424f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 425f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 426f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 427f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonstatic void LoadRegFromStackSlot(const TargetInstrInfo &TII, 428f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIdx, 429f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 430f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) { 431f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 432f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR) { 433f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg), 434f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 435f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 436f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11), 437f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 438f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11)); 439f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 440f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 441f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR8) { 442f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg), 443f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 444f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 445f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11), 446f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 447f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11)); 448f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 449f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 450f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg), 451f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 452f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 453f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg), 454f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 455f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::CRRCRegisterClass) { 456f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 457f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0), 458f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 459f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 460f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // If the reloaded register isn't CR0, shift the bits right so that they are 461f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // in the right CR's slot. 462f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::CR0) { 463f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 464f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // rlwinm r11, r11, 32-ShiftBits, 0, 31. 465f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 466f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); 467f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 468f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 469f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0)); 470f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 471f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 472f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 473f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // Dest = LVX 0, R0 474f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // 475f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 476f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 477f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 478f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0) 479f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0)); 480f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 481f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 482f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 483f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 484f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 485f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 486f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 487f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 488f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 489f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIdx, 490f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 491f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 492f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs); 493f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 494f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 495f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 496f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 497f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 498f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 499f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 500f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const{ 501f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (Addr[0].isFrameIndex()) { 502f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs); 503f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 504f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 505f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 506f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 507f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == PPC::GPRCRegisterClass) { 508f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(DestReg != PPC::LR && "Can't handle this yet!"); 509f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LWZ; 510f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::G8RCRegisterClass) { 511f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(DestReg != PPC::LR8 && "Can't handle this yet!"); 512f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LD; 513f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F8RCRegisterClass) { 514f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LFD; 515f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::F4RCRegisterClass) { 516f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LFS; 517f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else if (RC == PPC::VRRCRegisterClass) { 518f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = PPC::LVX; 519f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 520f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Unknown regclass!"); 521f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson abort(); 522f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 523f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); 524f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 525f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 526f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (MO.isRegister()) 527f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 528f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (MO.isImmediate()) 529f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 530f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 531f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 532f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 533f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 534f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 535f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 536f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 53743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 53843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson/// copy instructions, turning them into load/store instructions. 53943dbe05279b753aabda571d9c83eaeb36987001aOwen AndersonMachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI, 54043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<unsigned> &Ops, 54143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson int FrameIndex) const { 54243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 54343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 54443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 54543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 54643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 54743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 54843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 54943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 55043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 55143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 55243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 55343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 55443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg), 55543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 55643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 55743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 55843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg), 55943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 56043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 56143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if ((Opc == PPC::OR8 && 56243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 56343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 56443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 56543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg), 56643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 56743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 56843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 56943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex); 57043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 57143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if (Opc == PPC::FMRD) { 57243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 57343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 57443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg), 57543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 57643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 57743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 57843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex); 57943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 58043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else if (Opc == PPC::FMRS) { 58143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) { // move -> store 58243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned InReg = MI->getOperand(1).getReg(); 58343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg), 58443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson FrameIndex); 58543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } else { // move -> load 58643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OutReg = MI->getOperand(0).getReg(); 58743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex); 58843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 58943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 59043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 59143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (NewMI) 59243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson NewMI->copyKillDeadInfo(MI); 59343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 59443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 59543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 59643dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonbool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI, 59743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<unsigned> &Ops) const { 59843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return false; 59943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 60043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 60143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // it takes more than one instruction to store it. 60243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Opc = MI->getOpcode(); 60343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 60443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if ((Opc == PPC::OR && 60543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 60643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 60743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else if ((Opc == PPC::OR8 && 60843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) 60943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 61043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else if (Opc == PPC::FMRD || Opc == PPC::FMRS) 61143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return true; 61243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 61343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 61443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson} 61543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 616f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 617ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattnerbool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 618ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner if (MBB.empty()) return false; 619ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner 620ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner switch (MBB.back().getOpcode()) { 621126f17a17625876adb63f06d043fc1b1e4f0361cEvan Cheng case PPC::BLR: // Return. 622ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner case PPC::B: // Uncond branch. 623ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner case PPC::BCTR: // Indirect branch. 624ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner return true; 625ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner default: return false; 626ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner } 627ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner} 628ef13982aa7f3e57e82cd48370e79033dff0da295Chris Lattner 629c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo:: 630c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris LattnerReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 6317c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 6327c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner // Leave the CR# the same, but invert the condition. 63318258c640466274c26e89016e361ec411ff78520Chris Lattner Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 6347c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 635c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 636