PPCInstrInfo.cpp revision d1c321a89ab999b9bb602b0f398ecd4c2022262c 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
34                               unsigned& sourceReg,
35                               unsigned& destReg,
36                               unsigned& sourceSubIdx,
37                               unsigned& destSubIdx) const {
38  sourceSubIdx = destSubIdx = 0; // No sub-registers.
39
40  unsigned oc = MI.getOpcode();
41  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
43    assert(MI.getNumOperands() >= 3 &&
44           MI.getOperand(0).isReg() &&
45           MI.getOperand(1).isReg() &&
46           MI.getOperand(2).isReg() &&
47           "invalid PPC OR instruction!");
48    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49      sourceReg = MI.getOperand(1).getReg();
50      destReg = MI.getOperand(0).getReg();
51      return true;
52    }
53  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
54    assert(MI.getNumOperands() >= 3 &&
55           MI.getOperand(0).isReg() &&
56           MI.getOperand(2).isImm() &&
57           "invalid PPC ADDI instruction!");
58    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59      sourceReg = MI.getOperand(1).getReg();
60      destReg = MI.getOperand(0).getReg();
61      return true;
62    }
63  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
64    assert(MI.getNumOperands() >= 3 &&
65           MI.getOperand(0).isReg() &&
66           MI.getOperand(1).isReg() &&
67           MI.getOperand(2).isImm() &&
68           "invalid PPC ORI instruction!");
69    if (MI.getOperand(2).getImm() == 0) {
70      sourceReg = MI.getOperand(1).getReg();
71      destReg = MI.getOperand(0).getReg();
72      return true;
73    }
74  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75             oc == PPC::FMRSD) {      // fmr r1, r2
76    assert(MI.getNumOperands() >= 2 &&
77           MI.getOperand(0).isReg() &&
78           MI.getOperand(1).isReg() &&
79           "invalid PPC FMR instruction");
80    sourceReg = MI.getOperand(1).getReg();
81    destReg = MI.getOperand(0).getReg();
82    return true;
83  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC MCRF instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  }
92  return false;
93}
94
95unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                           int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::LD:
100  case PPC::LWZ:
101  case PPC::LFS:
102  case PPC::LFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                          int &FrameIndex) const {
115  switch (MI->getOpcode()) {
116  default: break;
117  case PPC::STD:
118  case PPC::STW:
119  case PPC::STFS:
120  case PPC::STFD:
121    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122        MI->getOperand(2).isFI()) {
123      FrameIndex = MI->getOperand(2).getIndex();
124      return MI->getOperand(0).getReg();
125    }
126    break;
127  }
128  return 0;
129}
130
131// commuteInstruction - We can commute rlwimi instructions, but only if the
132// rotate amt is zero.  We also have to munge the immediates a bit.
133MachineInstr *
134PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135  MachineFunction &MF = *MI->getParent()->getParent();
136
137  // Normal instructions can be commuted the obvious way.
138  if (MI->getOpcode() != PPC::RLWIMI)
139    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
140
141  // Cannot commute if it has a non-zero rotate count.
142  if (MI->getOperand(3).getImm() != 0)
143    return 0;
144
145  // If we have a zero rotate count, we have:
146  //   M = mask(MB,ME)
147  //   Op0 = (Op1 & ~M) | (Op2 & M)
148  // Change this to:
149  //   M = mask((ME+1)&31, (MB-1)&31)
150  //   Op0 = (Op2 & ~M) | (Op1 & M)
151
152  // Swap op1/op2
153  unsigned Reg0 = MI->getOperand(0).getReg();
154  unsigned Reg1 = MI->getOperand(1).getReg();
155  unsigned Reg2 = MI->getOperand(2).getReg();
156  bool Reg1IsKill = MI->getOperand(1).isKill();
157  bool Reg2IsKill = MI->getOperand(2).isKill();
158  bool ChangeReg0 = false;
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    Reg2IsKill = false;
166    ChangeReg0 = true;
167  }
168
169  // Masks.
170  unsigned MB = MI->getOperand(4).getImm();
171  unsigned ME = MI->getOperand(5).getImm();
172
173  if (NewMI) {
174    // Create a new instruction.
175    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176    bool Reg0IsDead = MI->getOperand(0).isDead();
177    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178      .addReg(Reg0, true, false, false, Reg0IsDead)
179      .addReg(Reg2, false, false, Reg2IsKill)
180      .addReg(Reg1, false, false, Reg1IsKill)
181      .addImm((ME+1) & 31)
182      .addImm((MB-1) & 31);
183  }
184
185  if (ChangeReg0)
186    MI->getOperand(0).setReg(Reg2);
187  MI->getOperand(2).setReg(Reg1);
188  MI->getOperand(1).setReg(Reg2);
189  MI->getOperand(2).setIsKill(Reg1IsKill);
190  MI->getOperand(1).setIsKill(Reg2IsKill);
191
192  // Swap the mask around.
193  MI->getOperand(4).setImm((ME+1) & 31);
194  MI->getOperand(5).setImm((MB-1) & 31);
195  return MI;
196}
197
198void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                              MachineBasicBlock::iterator MI) const {
200  DebugLoc DL = DebugLoc::getUnknownLoc();
201  if (MI != MBB.end()) DL = MI->getDebugLoc();
202
203  BuildMI(MBB, MI, DL, get(PPC::NOP));
204}
205
206
207// Branch analysis.
208bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                 MachineBasicBlock *&FBB,
210                                 SmallVectorImpl<MachineOperand> &Cond,
211                                 bool AllowModify) const {
212  // If the block has no terminators, it just falls into the block after it.
213  MachineBasicBlock::iterator I = MBB.end();
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
215    return false;
216
217  // Get the last instruction in the block.
218  MachineInstr *LastInst = I;
219
220  // If there is only one terminator instruction, process it.
221  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
222    if (LastInst->getOpcode() == PPC::B) {
223      TBB = LastInst->getOperand(0).getMBB();
224      return false;
225    } else if (LastInst->getOpcode() == PPC::BCC) {
226      // Block ends with fall-through condbranch.
227      TBB = LastInst->getOperand(2).getMBB();
228      Cond.push_back(LastInst->getOperand(0));
229      Cond.push_back(LastInst->getOperand(1));
230      return false;
231    }
232    // Otherwise, don't know what this is.
233    return true;
234  }
235
236  // Get the instruction before it if it's a terminator.
237  MachineInstr *SecondLastInst = I;
238
239  // If there are three terminators, we don't know what sort of block this is.
240  if (SecondLastInst && I != MBB.begin() &&
241      isUnpredicatedTerminator(--I))
242    return true;
243
244  // If the block ends with PPC::B and PPC:BCC, handle it.
245  if (SecondLastInst->getOpcode() == PPC::BCC &&
246      LastInst->getOpcode() == PPC::B) {
247    TBB =  SecondLastInst->getOperand(2).getMBB();
248    Cond.push_back(SecondLastInst->getOperand(0));
249    Cond.push_back(SecondLastInst->getOperand(1));
250    FBB = LastInst->getOperand(0).getMBB();
251    return false;
252  }
253
254  // If the block ends with two PPC:Bs, handle it.  The second one is not
255  // executed, so remove it.
256  if (SecondLastInst->getOpcode() == PPC::B &&
257      LastInst->getOpcode() == PPC::B) {
258    TBB = SecondLastInst->getOperand(0).getMBB();
259    I = LastInst;
260    if (AllowModify)
261      I->eraseFromParent();
262    return false;
263  }
264
265  // Otherwise, can't handle this.
266  return true;
267}
268
269unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
270  MachineBasicBlock::iterator I = MBB.end();
271  if (I == MBB.begin()) return 0;
272  --I;
273  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
274    return 0;
275
276  // Remove the branch.
277  I->eraseFromParent();
278
279  I = MBB.end();
280
281  if (I == MBB.begin()) return 1;
282  --I;
283  if (I->getOpcode() != PPC::BCC)
284    return 1;
285
286  // Remove the branch.
287  I->eraseFromParent();
288  return 2;
289}
290
291unsigned
292PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
293                           MachineBasicBlock *FBB,
294                           const SmallVectorImpl<MachineOperand> &Cond) const {
295  // Shouldn't be a fall through.
296  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
297  assert((Cond.size() == 2 || Cond.size() == 0) &&
298         "PPC branch conditions have two components!");
299
300  // One-way branch.
301  if (FBB == 0) {
302    if (Cond.empty())   // Unconditional branch
303      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
304    else                // Conditional branch
305      BuildMI(&MBB, get(PPC::BCC))
306        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
307    return 1;
308  }
309
310  // Two-way Conditional Branch.
311  BuildMI(&MBB, get(PPC::BCC))
312    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
313  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
314  return 2;
315}
316
317bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
318                                   MachineBasicBlock::iterator MI,
319                                   unsigned DestReg, unsigned SrcReg,
320                                   const TargetRegisterClass *DestRC,
321                                   const TargetRegisterClass *SrcRC) const {
322  if (DestRC != SrcRC) {
323    // Not yet supported!
324    return false;
325  }
326
327  DebugLoc DL = DebugLoc::getUnknownLoc();
328  if (MI != MBB.end()) DL = MI->getDebugLoc();
329
330  if (DestRC == PPC::GPRCRegisterClass) {
331    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
332  } else if (DestRC == PPC::G8RCRegisterClass) {
333    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
334  } else if (DestRC == PPC::F4RCRegisterClass) {
335    BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
336  } else if (DestRC == PPC::F8RCRegisterClass) {
337    BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
338  } else if (DestRC == PPC::CRRCRegisterClass) {
339    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
340  } else if (DestRC == PPC::VRRCRegisterClass) {
341    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
342  } else if (DestRC == PPC::CRBITRCRegisterClass) {
343    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
344  } else {
345    // Attempt to copy register that is not GPR or FPR
346    return false;
347  }
348
349  return true;
350}
351
352bool
353PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
354                                  unsigned SrcReg, bool isKill,
355                                  int FrameIdx,
356                                  const TargetRegisterClass *RC,
357                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
358  if (RC == PPC::GPRCRegisterClass) {
359    if (SrcReg != PPC::LR) {
360      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
361                                         .addReg(SrcReg, false, false, isKill),
362                                         FrameIdx));
363    } else {
364      // FIXME: this spills LR immediately to memory in one step.  To do this,
365      // we use R11, which we know cannot be used in the prolog/epilog.  This is
366      // a hack.
367      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
368      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
369                                         .addReg(PPC::R11, false, false, isKill),
370                                         FrameIdx));
371    }
372  } else if (RC == PPC::G8RCRegisterClass) {
373    if (SrcReg != PPC::LR8) {
374      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
375                              .addReg(SrcReg, false, false, isKill), FrameIdx));
376    } else {
377      // FIXME: this spills LR immediately to memory in one step.  To do this,
378      // we use R11, which we know cannot be used in the prolog/epilog.  This is
379      // a hack.
380      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
381      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
382                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
383    }
384  } else if (RC == PPC::F8RCRegisterClass) {
385    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
386                              .addReg(SrcReg, false, false, isKill), FrameIdx));
387  } else if (RC == PPC::F4RCRegisterClass) {
388    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
389                              .addReg(SrcReg, false, false, isKill), FrameIdx));
390  } else if (RC == PPC::CRRCRegisterClass) {
391    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
392        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
393      // FIXME (64-bit): Enable
394      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
395                                         .addReg(SrcReg, false, false, isKill),
396                                         FrameIdx));
397      return true;
398    } else {
399      // FIXME: We use R0 here, because it isn't available for RA.  We need to
400      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
401      // to save all of the CRBits.
402      NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
403
404      // If the saved register wasn't CR0, shift the bits left so that they are
405      // in CR0's slot.
406      if (SrcReg != PPC::CR0) {
407        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
408        // rlwinm r0, r0, ShiftBits, 0, 31.
409        NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
410                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
411      }
412
413      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
414                                         .addReg(PPC::R0, false, false, isKill),
415                                         FrameIdx));
416    }
417  } else if (RC == PPC::CRBITRCRegisterClass) {
418    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
419    // backend currently only uses CR1EQ as an individual bit, this should
420    // not cause any bug. If we need other uses of CR bits, the following
421    // code may be invalid.
422    unsigned Reg = 0;
423    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
424      Reg = PPC::CR0;
425    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
426      Reg = PPC::CR1;
427    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
428      Reg = PPC::CR2;
429    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
430      Reg = PPC::CR3;
431    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
432      Reg = PPC::CR4;
433    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
434      Reg = PPC::CR5;
435    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
436      Reg = PPC::CR6;
437    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
438      Reg = PPC::CR7;
439
440    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
441                               PPC::CRRCRegisterClass, NewMIs);
442
443  } else if (RC == PPC::VRRCRegisterClass) {
444    // We don't have indexed addressing for vector loads.  Emit:
445    // R0 = ADDI FI#
446    // STVX VAL, 0, R0
447    //
448    // FIXME: We use R0 here, because it isn't available for RA.
449    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
450                                       FrameIdx, 0, 0));
451    NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
452         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
453  } else {
454    assert(0 && "Unknown regclass!");
455    abort();
456  }
457
458  return false;
459}
460
461void
462PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
463                                  MachineBasicBlock::iterator MI,
464                                  unsigned SrcReg, bool isKill, int FrameIdx,
465                                  const TargetRegisterClass *RC) const {
466  MachineFunction &MF = *MBB.getParent();
467  SmallVector<MachineInstr*, 4> NewMIs;
468
469  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
470    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
471    FuncInfo->setSpillsCR();
472  }
473
474  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
475    MBB.insert(MI, NewMIs[i]);
476}
477
478void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
479                                  bool isKill,
480                                  SmallVectorImpl<MachineOperand> &Addr,
481                                  const TargetRegisterClass *RC,
482                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
483  if (Addr[0].isFI()) {
484    if (StoreRegToStackSlot(MF, SrcReg, isKill,
485                            Addr[0].getIndex(), RC, NewMIs)) {
486      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
487      FuncInfo->setSpillsCR();
488    }
489
490    return;
491  }
492
493  unsigned Opc = 0;
494  if (RC == PPC::GPRCRegisterClass) {
495    Opc = PPC::STW;
496  } else if (RC == PPC::G8RCRegisterClass) {
497    Opc = PPC::STD;
498  } else if (RC == PPC::F8RCRegisterClass) {
499    Opc = PPC::STFD;
500  } else if (RC == PPC::F4RCRegisterClass) {
501    Opc = PPC::STFS;
502  } else if (RC == PPC::VRRCRegisterClass) {
503    Opc = PPC::STVX;
504  } else {
505    assert(0 && "Unknown regclass!");
506    abort();
507  }
508  MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
509    .addReg(SrcReg, false, false, isKill);
510  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
511    MachineOperand &MO = Addr[i];
512    if (MO.isReg())
513      MIB.addReg(MO.getReg());
514    else if (MO.isImm())
515      MIB.addImm(MO.getImm());
516    else
517      MIB.addFrameIndex(MO.getIndex());
518  }
519  NewMIs.push_back(MIB);
520  return;
521}
522
523void
524PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
525                                   unsigned DestReg, int FrameIdx,
526                                   const TargetRegisterClass *RC,
527                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
528  if (RC == PPC::GPRCRegisterClass) {
529    if (DestReg != PPC::LR) {
530      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
531                                                 DestReg), FrameIdx));
532    } else {
533      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
534                                                 PPC::R11), FrameIdx));
535      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
536    }
537  } else if (RC == PPC::G8RCRegisterClass) {
538    if (DestReg != PPC::LR8) {
539      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
540                                         FrameIdx));
541    } else {
542      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
543                                                 PPC::R11), FrameIdx));
544      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
545    }
546  } else if (RC == PPC::F8RCRegisterClass) {
547    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
548                                       FrameIdx));
549  } else if (RC == PPC::F4RCRegisterClass) {
550    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
551                                       FrameIdx));
552  } else if (RC == PPC::CRRCRegisterClass) {
553    // FIXME: We use R0 here, because it isn't available for RA.
554    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
555                                       FrameIdx));
556
557    // If the reloaded register isn't CR0, shift the bits right so that they are
558    // in the right CR's slot.
559    if (DestReg != PPC::CR0) {
560      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
561      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
562      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
563                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
564    }
565
566    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
567  } else if (RC == PPC::CRBITRCRegisterClass) {
568
569    unsigned Reg = 0;
570    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
571      Reg = PPC::CR0;
572    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
573      Reg = PPC::CR1;
574    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
575      Reg = PPC::CR2;
576    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
577      Reg = PPC::CR3;
578    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
579      Reg = PPC::CR4;
580    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
581      Reg = PPC::CR5;
582    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
583      Reg = PPC::CR6;
584    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
585      Reg = PPC::CR7;
586
587    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
588                                PPC::CRRCRegisterClass, NewMIs);
589
590  } else if (RC == PPC::VRRCRegisterClass) {
591    // We don't have indexed addressing for vector loads.  Emit:
592    // R0 = ADDI FI#
593    // Dest = LVX 0, R0
594    //
595    // FIXME: We use R0 here, because it isn't available for RA.
596    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
597                                       FrameIdx, 0, 0));
598    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
599                     .addReg(PPC::R0));
600  } else {
601    assert(0 && "Unknown regclass!");
602    abort();
603  }
604}
605
606void
607PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
608                                   MachineBasicBlock::iterator MI,
609                                   unsigned DestReg, int FrameIdx,
610                                   const TargetRegisterClass *RC) const {
611  MachineFunction &MF = *MBB.getParent();
612  SmallVector<MachineInstr*, 4> NewMIs;
613  DebugLoc DL = DebugLoc::getUnknownLoc();
614  if (MI != MBB.end()) DL = MI->getDebugLoc();
615  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
616  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
617    MBB.insert(MI, NewMIs[i]);
618}
619
620void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
621                                   SmallVectorImpl<MachineOperand> &Addr,
622                                   const TargetRegisterClass *RC,
623                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
624  if (Addr[0].isFI()) {
625    LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
626                         DestReg, Addr[0].getIndex(), RC, NewMIs);
627    return;
628  }
629
630  unsigned Opc = 0;
631  if (RC == PPC::GPRCRegisterClass) {
632    assert(DestReg != PPC::LR && "Can't handle this yet!");
633    Opc = PPC::LWZ;
634  } else if (RC == PPC::G8RCRegisterClass) {
635    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
636    Opc = PPC::LD;
637  } else if (RC == PPC::F8RCRegisterClass) {
638    Opc = PPC::LFD;
639  } else if (RC == PPC::F4RCRegisterClass) {
640    Opc = PPC::LFS;
641  } else if (RC == PPC::VRRCRegisterClass) {
642    Opc = PPC::LVX;
643  } else {
644    assert(0 && "Unknown regclass!");
645    abort();
646  }
647  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
648  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
649    MachineOperand &MO = Addr[i];
650    if (MO.isReg())
651      MIB.addReg(MO.getReg());
652    else if (MO.isImm())
653      MIB.addImm(MO.getImm());
654    else
655      MIB.addFrameIndex(MO.getIndex());
656  }
657  NewMIs.push_back(MIB);
658  return;
659}
660
661/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
662/// copy instructions, turning them into load/store instructions.
663MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
664                                                  MachineInstr *MI,
665                                           const SmallVectorImpl<unsigned> &Ops,
666                                                  int FrameIndex) const {
667  if (Ops.size() != 1) return NULL;
668
669  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
670  // it takes more than one instruction to store it.
671  unsigned Opc = MI->getOpcode();
672  unsigned OpNum = Ops[0];
673
674  MachineInstr *NewMI = NULL;
675  if ((Opc == PPC::OR &&
676       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
677    if (OpNum == 0) {  // move -> store
678      unsigned InReg = MI->getOperand(1).getReg();
679      bool isKill = MI->getOperand(1).isKill();
680      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
681                                .addReg(InReg, false, false, isKill),
682                                FrameIndex);
683    } else {           // move -> load
684      unsigned OutReg = MI->getOperand(0).getReg();
685      bool isDead = MI->getOperand(0).isDead();
686      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
687                                .addReg(OutReg, true, false, false, isDead),
688                                FrameIndex);
689    }
690  } else if ((Opc == PPC::OR8 &&
691              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
692    if (OpNum == 0) {  // move -> store
693      unsigned InReg = MI->getOperand(1).getReg();
694      bool isKill = MI->getOperand(1).isKill();
695      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
696                                .addReg(InReg, false, false, isKill),
697                                FrameIndex);
698    } else {           // move -> load
699      unsigned OutReg = MI->getOperand(0).getReg();
700      bool isDead = MI->getOperand(0).isDead();
701      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
702                                .addReg(OutReg, true, false, false, isDead),
703                                FrameIndex);
704    }
705  } else if (Opc == PPC::FMRD) {
706    if (OpNum == 0) {  // move -> store
707      unsigned InReg = MI->getOperand(1).getReg();
708      bool isKill = MI->getOperand(1).isKill();
709      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
710                                .addReg(InReg, false, false, isKill),
711                                FrameIndex);
712    } else {           // move -> load
713      unsigned OutReg = MI->getOperand(0).getReg();
714      bool isDead = MI->getOperand(0).isDead();
715      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
716                                .addReg(OutReg, true, false, false, isDead),
717                                FrameIndex);
718    }
719  } else if (Opc == PPC::FMRS) {
720    if (OpNum == 0) {  // move -> store
721      unsigned InReg = MI->getOperand(1).getReg();
722      bool isKill = MI->getOperand(1).isKill();
723      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
724                                .addReg(InReg, false, false, isKill),
725                                FrameIndex);
726    } else {           // move -> load
727      unsigned OutReg = MI->getOperand(0).getReg();
728      bool isDead = MI->getOperand(0).isDead();
729      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
730                                .addReg(OutReg, true, false, false, isDead),
731                                FrameIndex);
732    }
733  }
734
735  return NewMI;
736}
737
738bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
739                                  const SmallVectorImpl<unsigned> &Ops) const {
740  if (Ops.size() != 1) return false;
741
742  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
743  // it takes more than one instruction to store it.
744  unsigned Opc = MI->getOpcode();
745
746  if ((Opc == PPC::OR &&
747       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
748    return true;
749  else if ((Opc == PPC::OR8 &&
750              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
751    return true;
752  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
753    return true;
754
755  return false;
756}
757
758
759bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
760  if (MBB.empty()) return false;
761
762  switch (MBB.back().getOpcode()) {
763  case PPC::BLR:   // Return.
764  case PPC::B:     // Uncond branch.
765  case PPC::BCTR:  // Indirect branch.
766    return true;
767  default: return false;
768  }
769}
770
771bool PPCInstrInfo::
772ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
773  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
774  // Leave the CR# the same, but invert the condition.
775  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
776  return false;
777}
778
779/// GetInstSize - Return the number of bytes of code the specified
780/// instruction may be.  This returns the maximum number of bytes.
781///
782unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
783  switch (MI->getOpcode()) {
784  case PPC::INLINEASM: {       // Inline Asm: Variable size.
785    const MachineFunction *MF = MI->getParent()->getParent();
786    const char *AsmStr = MI->getOperand(0).getSymbolName();
787    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
788  }
789  case PPC::DBG_LABEL:
790  case PPC::EH_LABEL:
791  case PPC::GC_LABEL:
792    return 0;
793  default:
794    return 4; // PowerPC instructions are all 4 bytes
795  }
796}
797