1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetRegisterInfo 11// class. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "reginfo" 16#include "PPCRegisterInfo.h" 17#include "PPC.h" 18#include "PPCInstrBuilder.h" 19#include "PPCMachineFunctionInfo.h" 20#include "PPCFrameLowering.h" 21#include "PPCSubtarget.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/Function.h" 25#include "llvm/Type.h" 26#include "llvm/CodeGen/ValueTypes.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/RegisterScavenging.h" 33#include "llvm/Target/TargetFrameLowering.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/Support/CommandLine.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/ErrorHandling.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/STLExtras.h" 44#include <cstdlib> 45 46#define GET_REGINFO_TARGET_DESC 47#include "PPCGenRegisterInfo.inc" 48 49namespace llvm { 50cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", 51 cl::init(false), 52 cl::desc("Disable PPC32 register scavenger"), 53 cl::Hidden); 54cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", 55 cl::init(false), 56 cl::desc("Disable PPC64 register scavenger"), 57 cl::Hidden); 58} 59 60using namespace llvm; 61 62// FIXME (64-bit): Should be inlined. 63bool 64PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 65 return ((!DisablePPC32RS && !Subtarget.isPPC64()) || 66 (!DisablePPC64RS && Subtarget.isPPC64())); 67} 68 69PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 70 const TargetInstrInfo &tii) 71 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 72 ST.isPPC64() ? 0 : 1, 73 ST.isPPC64() ? 0 : 1), 74 Subtarget(ST), TII(tii) { 75 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 76 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 77 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 78 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 79 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 80 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 81 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 82 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 83 84 // 64-bit 85 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 86 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 87 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 88 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 89 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 90} 91 92bool 93PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 94 return requiresRegisterScavenging(MF); 95} 96 97 98/// getPointerRegClass - Return the register class to use to hold pointers. 99/// This is used for addressing modes. 100const TargetRegisterClass * 101PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 102 const { 103 if (Subtarget.isPPC64()) 104 return &PPC::G8RCRegClass; 105 return &PPC::GPRCRegClass; 106} 107 108const uint16_t* 109PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 112 CSR_Darwin32_SaveList; 113 114 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 115} 116 117const unsigned* 118PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 119 if (Subtarget.isDarwinABI()) 120 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 121 CSR_Darwin32_RegMask; 122 123 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 124} 125 126BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 127 BitVector Reserved(getNumRegs()); 128 const PPCFrameLowering *PPCFI = 129 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 130 131 Reserved.set(PPC::R0); 132 Reserved.set(PPC::R1); 133 Reserved.set(PPC::LR); 134 Reserved.set(PPC::LR8); 135 Reserved.set(PPC::RM); 136 137 // The SVR4 ABI reserves r2 and r13 138 if (Subtarget.isSVR4ABI()) { 139 Reserved.set(PPC::R2); // System-reserved register 140 Reserved.set(PPC::R13); // Small Data Area pointer register 141 } 142 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 143 // when the stack frame is too big to address directly; we need two regs. 144 // This is a hack. 145 if (Subtarget.isDarwinABI()) { 146 Reserved.set(PPC::R2); 147 } 148 149 // On PPC64, r13 is the thread pointer. Never allocate this register. 150 // Note that this is over conservative, as it also prevents allocation of R31 151 // when the FP is not needed. 152 if (Subtarget.isPPC64()) { 153 Reserved.set(PPC::R13); 154 Reserved.set(PPC::R31); 155 156 Reserved.set(PPC::X0); 157 Reserved.set(PPC::X1); 158 Reserved.set(PPC::X13); 159 Reserved.set(PPC::X31); 160 161 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 162 if (Subtarget.isSVR4ABI()) { 163 Reserved.set(PPC::X2); 164 } 165 // Reserve X2 on Darwin to hack around the problem of save/restore of CR 166 // when the stack frame is too big to address directly; we need two regs. 167 // This is a hack. 168 if (Subtarget.isDarwinABI()) { 169 Reserved.set(PPC::X2); 170 } 171 } 172 173 if (PPCFI->needsFP(MF)) 174 Reserved.set(PPC::R31); 175 176 return Reserved; 177} 178 179unsigned 180PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 181 MachineFunction &MF) const { 182 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183 const unsigned DefaultSafety = 1; 184 185 switch (RC->getID()) { 186 default: 187 return 0; 188 case PPC::G8RCRegClassID: 189 case PPC::GPRCRegClassID: { 190 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 191 return 32 - FP - DefaultSafety; 192 } 193 case PPC::F8RCRegClassID: 194 case PPC::F4RCRegClassID: 195 case PPC::VRRCRegClassID: 196 return 32 - DefaultSafety; 197 case PPC::CRRCRegClassID: 198 return 8 - DefaultSafety; 199 } 200} 201 202bool 203PPCRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 204 switch (RC->getID()) { 205 case PPC::G8RCRegClassID: 206 case PPC::GPRCRegClassID: 207 case PPC::F8RCRegClassID: 208 case PPC::F4RCRegClassID: 209 case PPC::VRRCRegClassID: 210 return true; 211 default: 212 return false; 213 } 214} 215 216//===----------------------------------------------------------------------===// 217// Stack Frame Processing methods 218//===----------------------------------------------------------------------===// 219 220void PPCRegisterInfo:: 221eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 222 MachineBasicBlock::iterator I) const { 223 if (MF.getTarget().Options.GuaranteedTailCallOpt && 224 I->getOpcode() == PPC::ADJCALLSTACKUP) { 225 // Add (actually subtract) back the amount the callee popped on return. 226 if (int CalleeAmt = I->getOperand(1).getImm()) { 227 bool is64Bit = Subtarget.isPPC64(); 228 CalleeAmt *= -1; 229 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 230 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 231 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 232 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 233 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 234 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 235 MachineInstr *MI = I; 236 DebugLoc dl = MI->getDebugLoc(); 237 238 if (isInt<16>(CalleeAmt)) { 239 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 240 .addReg(StackReg, RegState::Kill) 241 .addImm(CalleeAmt); 242 } else { 243 MachineBasicBlock::iterator MBBI = I; 244 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 245 .addImm(CalleeAmt >> 16); 246 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 247 .addReg(TmpReg, RegState::Kill) 248 .addImm(CalleeAmt & 0xFFFF); 249 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 250 .addReg(StackReg, RegState::Kill) 251 .addReg(TmpReg); 252 } 253 } 254 } 255 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 256 MBB.erase(I); 257} 258 259/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 260/// register first and then a spilled callee-saved register if that fails. 261static 262unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 263 const TargetRegisterClass *RC, int SPAdj) { 264 assert(RS && "Register scavenging must be on"); 265 unsigned Reg = RS->FindUnusedReg(RC); 266 // FIXME: move ARM callee-saved reg scan to target independent code, then 267 // search for already spilled CS register here. 268 if (Reg == 0) 269 Reg = RS->scavengeRegister(RC, II, SPAdj); 270 return Reg; 271} 272 273/// lowerDynamicAlloc - Generate the code for allocating an object in the 274/// current frame. The sequence of code with be in the general form 275/// 276/// addi R0, SP, \#frameSize ; get the address of the previous frame 277/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 278/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 279/// 280void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 281 int SPAdj, RegScavenger *RS) const { 282 // Get the instruction. 283 MachineInstr &MI = *II; 284 // Get the instruction's basic block. 285 MachineBasicBlock &MBB = *MI.getParent(); 286 // Get the basic block's function. 287 MachineFunction &MF = *MBB.getParent(); 288 // Get the frame info. 289 MachineFrameInfo *MFI = MF.getFrameInfo(); 290 // Determine whether 64-bit pointers are used. 291 bool LP64 = Subtarget.isPPC64(); 292 DebugLoc dl = MI.getDebugLoc(); 293 294 // Get the maximum call stack size. 295 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 296 // Get the total frame size. 297 unsigned FrameSize = MFI->getStackSize(); 298 299 // Get stack alignments. 300 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 301 unsigned MaxAlign = MFI->getMaxAlignment(); 302 if (MaxAlign > TargetAlign) 303 report_fatal_error("Dynamic alloca with large aligns not supported"); 304 305 // Determine the previous frame's address. If FrameSize can't be 306 // represented as 16 bits or we need special alignment, then we load the 307 // previous frame's address from 0(SP). Why not do an addis of the hi? 308 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 309 // Constructing the constant and adding would take 3 instructions. 310 // Fortunately, a frame greater than 32K is rare. 311 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 312 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 313 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 314 315 // FIXME (64-bit): Use "findScratchRegister" 316 unsigned Reg; 317 if (requiresRegisterScavenging(MF)) 318 Reg = findScratchRegister(II, RS, RC, SPAdj); 319 else 320 Reg = PPC::R0; 321 322 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 323 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 324 .addReg(PPC::R31) 325 .addImm(FrameSize); 326 } else if (LP64) { 327 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 328 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 329 .addImm(0) 330 .addReg(PPC::X1); 331 else 332 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 333 .addImm(0) 334 .addReg(PPC::X1); 335 } else { 336 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 337 .addImm(0) 338 .addReg(PPC::R1); 339 } 340 341 // Grow the stack and update the stack pointer link, then determine the 342 // address of new allocated space. 343 if (LP64) { 344 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 345 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 346 .addReg(Reg, RegState::Kill) 347 .addReg(PPC::X1) 348 .addReg(MI.getOperand(1).getReg()); 349 else 350 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 351 .addReg(PPC::X0, RegState::Kill) 352 .addReg(PPC::X1) 353 .addReg(MI.getOperand(1).getReg()); 354 355 if (!MI.getOperand(1).isKill()) 356 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 357 .addReg(PPC::X1) 358 .addImm(maxCallFrameSize); 359 else 360 // Implicitly kill the register. 361 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 362 .addReg(PPC::X1) 363 .addImm(maxCallFrameSize) 364 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 365 } else { 366 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 367 .addReg(Reg, RegState::Kill) 368 .addReg(PPC::R1) 369 .addReg(MI.getOperand(1).getReg()); 370 371 if (!MI.getOperand(1).isKill()) 372 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 373 .addReg(PPC::R1) 374 .addImm(maxCallFrameSize); 375 else 376 // Implicitly kill the register. 377 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 378 .addReg(PPC::R1) 379 .addImm(maxCallFrameSize) 380 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 381 } 382 383 // Discard the DYNALLOC instruction. 384 MBB.erase(II); 385} 386 387/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 388/// reserving a whole register (R0), we scrounge for one here. This generates 389/// code like this: 390/// 391/// mfcr rA ; Move the conditional register into GPR rA. 392/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 393/// stw rA, FI ; Store rA to the frame. 394/// 395void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 396 unsigned FrameIndex, int SPAdj, 397 RegScavenger *RS) const { 398 // Get the instruction. 399 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 400 // Get the instruction's basic block. 401 MachineBasicBlock &MBB = *MI.getParent(); 402 DebugLoc dl = MI.getDebugLoc(); 403 404 // FIXME: Once LLVM supports creating virtual registers here, or the register 405 // scavenger can return multiple registers, stop using reserved registers 406 // here. 407 (void) SPAdj; 408 (void) RS; 409 410 bool LP64 = Subtarget.isPPC64(); 411 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 412 (LP64 ? PPC::X0 : PPC::R0); 413 unsigned SrcReg = MI.getOperand(0).getReg(); 414 415 // We need to store the CR in the low 4-bits of the saved value. First, issue 416 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 417 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 418 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 419 420 // If the saved register wasn't CR0, shift the bits left so that they are in 421 // CR0's slot. 422 if (SrcReg != PPC::CR0) 423 // rlwinm rA, rA, ShiftBits, 0, 31. 424 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 425 .addReg(Reg, RegState::Kill) 426 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 427 .addImm(0) 428 .addImm(31); 429 430 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 431 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 432 FrameIndex); 433 434 // Discard the pseudo instruction. 435 MBB.erase(II); 436} 437 438void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 439 unsigned FrameIndex, int SPAdj, 440 RegScavenger *RS) const { 441 // Get the instruction. 442 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 443 // Get the instruction's basic block. 444 MachineBasicBlock &MBB = *MI.getParent(); 445 DebugLoc dl = MI.getDebugLoc(); 446 447 // FIXME: Once LLVM supports creating virtual registers here, or the register 448 // scavenger can return multiple registers, stop using reserved registers 449 // here. 450 (void) SPAdj; 451 (void) RS; 452 453 bool LP64 = Subtarget.isPPC64(); 454 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 455 (LP64 ? PPC::X0 : PPC::R0); 456 unsigned DestReg = MI.getOperand(0).getReg(); 457 assert(MI.definesRegister(DestReg) && 458 "RESTORE_CR does not define its destination"); 459 460 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 461 Reg), FrameIndex); 462 463 // If the reloaded register isn't CR0, shift the bits right so that they are 464 // in the right CR's slot. 465 if (DestReg != PPC::CR0) { 466 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 467 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 468 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 469 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 470 .addImm(31); 471 } 472 473 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 474 .addReg(Reg); 475 476 // Discard the pseudo instruction. 477 MBB.erase(II); 478} 479 480void 481PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 482 int SPAdj, RegScavenger *RS) const { 483 assert(SPAdj == 0 && "Unexpected"); 484 485 // Get the instruction. 486 MachineInstr &MI = *II; 487 // Get the instruction's basic block. 488 MachineBasicBlock &MBB = *MI.getParent(); 489 // Get the basic block's function. 490 MachineFunction &MF = *MBB.getParent(); 491 // Get the frame info. 492 MachineFrameInfo *MFI = MF.getFrameInfo(); 493 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 494 DebugLoc dl = MI.getDebugLoc(); 495 496 // Find out which operand is the frame index. 497 unsigned FIOperandNo = 0; 498 while (!MI.getOperand(FIOperandNo).isFI()) { 499 ++FIOperandNo; 500 assert(FIOperandNo != MI.getNumOperands() && 501 "Instr doesn't have FrameIndex operand!"); 502 } 503 // Take into account whether it's an add or mem instruction 504 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 505 if (MI.isInlineAsm()) 506 OffsetOperandNo = FIOperandNo-1; 507 508 // Get the frame index. 509 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 510 511 // Get the frame pointer save index. Users of this index are primarily 512 // DYNALLOC instructions. 513 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 514 int FPSI = FI->getFramePointerSaveIndex(); 515 // Get the instruction opcode. 516 unsigned OpC = MI.getOpcode(); 517 518 // Special case for dynamic alloca. 519 if (FPSI && FrameIndex == FPSI && 520 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 521 lowerDynamicAlloc(II, SPAdj, RS); 522 return; 523 } 524 525 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 526 if (requiresRegisterScavenging(MF)) { 527 if (OpC == PPC::SPILL_CR) { 528 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 529 return; 530 } else if (OpC == PPC::RESTORE_CR) { 531 lowerCRRestore(II, FrameIndex, SPAdj, RS); 532 return; 533 } 534 } 535 536 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 537 538 bool is64Bit = Subtarget.isPPC64(); 539 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 540 (is64Bit ? PPC::X31 : PPC::R31) : 541 (is64Bit ? PPC::X1 : PPC::R1), 542 false); 543 544 // Figure out if the offset in the instruction is shifted right two bits. This 545 // is true for instructions like "STD", which the machine implicitly adds two 546 // low zeros to. 547 bool isIXAddr = false; 548 switch (OpC) { 549 case PPC::LWA: 550 case PPC::LD: 551 case PPC::STD: 552 case PPC::STD_32: 553 isIXAddr = true; 554 break; 555 } 556 557 // Now add the frame object offset to the offset from r1. 558 int Offset = MFI->getObjectOffset(FrameIndex); 559 if (!isIXAddr) 560 Offset += MI.getOperand(OffsetOperandNo).getImm(); 561 else 562 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 563 564 // If we're not using a Frame Pointer that has been set to the value of the 565 // SP before having the stack size subtracted from it, then add the stack size 566 // to Offset to get the correct offset. 567 // Naked functions have stack size 0, although getStackSize may not reflect that 568 // because we didn't call all the pieces that compute it for naked functions. 569 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 570 Offset += MFI->getStackSize(); 571 572 // If we can, encode the offset directly into the instruction. If this is a 573 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 574 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 575 // clear can be encoded. This is extremely uncommon, because normally you 576 // only "std" to a stack slot that is at least 4-byte aligned, but it can 577 // happen in invalid code. 578 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 579 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 580 if (isIXAddr) 581 Offset >>= 2; // The actual encoded value has the low two bits zero. 582 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 583 return; 584 } 585 586 // The offset doesn't fit into a single register, scavenge one to build the 587 // offset in. 588 589 unsigned SReg; 590 if (requiresRegisterScavenging(MF)) { 591 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 592 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 593 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 594 } else 595 SReg = is64Bit ? PPC::X0 : PPC::R0; 596 597 // Insert a set of rA with the full offset value before the ld, st, or add 598 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 599 .addImm(Offset >> 16); 600 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 601 .addReg(SReg, RegState::Kill) 602 .addImm(Offset); 603 604 // Convert into indexed form of the instruction: 605 // 606 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 607 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 608 unsigned OperandBase; 609 610 if (OpC != TargetOpcode::INLINEASM) { 611 assert(ImmToIdxMap.count(OpC) && 612 "No indexed form of load or store available!"); 613 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 614 MI.setDesc(TII.get(NewOpcode)); 615 OperandBase = 1; 616 } else { 617 OperandBase = OffsetOperandNo; 618 } 619 620 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 621 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 622 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 623} 624 625unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 626 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 627 628 if (!Subtarget.isPPC64()) 629 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 630 else 631 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 632} 633 634unsigned PPCRegisterInfo::getEHExceptionRegister() const { 635 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 636} 637 638unsigned PPCRegisterInfo::getEHHandlerRegister() const { 639 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 640} 641