131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file contains the PowerPC implementation of the TargetRegisterInfo 116f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// class. 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 14f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 15f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#define DEBUG_TYPE "reginfo" 1679aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "PPCRegisterInfo.h" 172668959b8879097db368aec7d76c455260abc75bChris Lattner#include "PPC.h" 1826bd0d48a164c419462133270e3ec1c2401a34d7Chris Lattner#include "PPCInstrBuilder.h" 192f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey#include "PPCMachineFunctionInfo.h" 2016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "PPCFrameLowering.h" 21804e06704261f233111913a047ef7f7dec1b8725Chris Lattner#include "PPCSubtarget.h" 2230e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer#include "llvm/CallingConv.h" 23f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/Constants.h" 241532f3ddd77c362dd5f613af06b4de636e3c5b0eDale Johannesen#include "llvm/Function.h" 25f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/Type.h" 26f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/ValueTypes.h" 27f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 2844c3b9fdd416c79f4b67cde1aecfced5921efd81Jim Laskey#include "llvm/CodeGen/MachineModuleInfo.h" 29f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineFunction.h" 30f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineFrameInfo.h" 3184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 327194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "llvm/CodeGen/RegisterScavenging.h" 3316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 34f9568d8700d5389799796262cde313bb5c7d588aChris Lattner#include "llvm/Target/TargetInstrInfo.h" 35f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/Target/TargetMachine.h" 36f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/Target/TargetOptions.h" 37551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/CommandLine.h" 38551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/Debug.h" 39dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 40ae232e7a1055033436370c0b3aecf054fa44d5e7Nate Begeman#include "llvm/Support/MathExtras.h" 41dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 42b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng#include "llvm/ADT/BitVector.h" 43551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/ADT/STLExtras.h" 44f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include <cstdlib> 4573f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4673f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 47a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "PPCGenRegisterInfo.inc" 48f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 4982bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmannamespace llvm { 503fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkelcl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", 51b35798347ea87b8b6d36155b211016a7769f01abDan Gohman cl::init(false), 523fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel cl::desc("Disable PPC32 register scavenger"), 53b35798347ea87b8b6d36155b211016a7769f01abDan Gohman cl::Hidden); 543fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkelcl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", 55b35798347ea87b8b6d36155b211016a7769f01abDan Gohman cl::init(false), 563fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel cl::desc("Disable PPC64 register scavenger"), 57b35798347ea87b8b6d36155b211016a7769f01abDan Gohman cl::Hidden); 5882bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman} 5982bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman 6082bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmanusing namespace llvm; 6182bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman 627194aaf738a1b89441635340403f1c5b06ae18efBill Wendling// FIXME (64-bit): Should be inlined. 637194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingbool 647194aaf738a1b89441635340403f1c5b06ae18efBill WendlingPPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 653fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel return ((!DisablePPC32RS && !Subtarget.isPPC64()) || 663fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel (!DisablePPC64RS && Subtarget.isPPC64())); 677194aaf738a1b89441635340403f1c5b06ae18efBill Wendling} 687194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 697ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan ChengPPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 707ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng const TargetInstrInfo &tii) 710e6a052331f674dd70e28af41f654a7874405eabEvan Cheng : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 720e6a052331f674dd70e28af41f654a7874405eabEvan Cheng ST.isPPC64() ? 0 : 1, 730e6a052331f674dd70e28af41f654a7874405eabEvan Cheng ST.isPPC64() ? 0 : 1), 740e6a052331f674dd70e28af41f654a7874405eabEvan Cheng Subtarget(ST), TII(tii) { 75b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 76f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 77f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 78f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 79f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 80f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 81f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 821d9d7427c4a4e3c7bdcfd1f725447f355e509c20Nate Begeman ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 8382d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling 8482d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling // 64-bit 8582d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 8682d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 8782d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 8882d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 8982d25148a7aab0b7e048ab9b774207b3766d1bbfBill Wendling ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 90f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 91f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 926a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurdbool 936a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston GurdPPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 946a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return requiresRegisterScavenging(MF); 956a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd} 966a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 976a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 98770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// getPointerRegClass - Return the register class to use to hold pointers. 99770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng/// This is used for addressing modes. 1002cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 101397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenPPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 102397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 103770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng if (Subtarget.isPPC64()) 104770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng return &PPC::G8RCRegClass; 1052cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner return &PPC::GPRCRegClass; 106770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng} 107770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng 108015f228861ef9b337366f92f637d4e8d624bb006Craig Topperconst uint16_t* 10964d80e3387f328d21cd9cc06464b5de7861e3f27Evan ChengPPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 110e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky if (Subtarget.isDarwinABI()) 111e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 112e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky CSR_Darwin32_SaveList; 1136b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 114e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 115e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky} 1166b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 117e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divackyconst unsigned* 118e46137f498fa81a088f13d24c79242eed3ff45a7Roman DivackyPPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 1192a9ddfb903ae3baede7282348afae1f750905248Tilmann Scheller if (Subtarget.isDarwinABI()) 120e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 121e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky CSR_Darwin32_RegMask; 1226b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 123e46137f498fa81a088f13d24c79242eed3ff45a7Roman Divacky return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 1240f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng} 1250f3ac8d8d4ce23eb2ae6f9d850f389250874eea5Evan Cheng 126b371f457b0ea4a652a9f526ba4375c80ae542252Evan ChengBitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 127b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng BitVector Reserved(getNumRegs()); 12816c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const PPCFrameLowering *PPCFI = 12916c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 130d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 131b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R0); 132b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R1); 133b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::LR); 1347194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::LR8); 135b384ab9ea113ad22a9c7034b98060c7470f0dcc5Dale Johannesen Reserved.set(PPC::RM); 1367194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 137ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller // The SVR4 ABI reserves r2 and r13 1382a9ddfb903ae3baede7282348afae1f750905248Tilmann Scheller if (Subtarget.isSVR4ABI()) { 139ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller Reserved.set(PPC::R2); // System-reserved register 140ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller Reserved.set(PPC::R13); // Small Data Area pointer register 141ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller } 142ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen // Reserve R2 on Darwin to hack around the problem of save/restore of CR 143ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen // when the stack frame is too big to address directly; we need two regs. 144ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen // This is a hack. 145ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen if (Subtarget.isDarwinABI()) { 146ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen Reserved.set(PPC::R2); 147ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen } 148ffd0200abfd63177257f949a3674b91dcf87bf23Tilmann Scheller 1496b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // On PPC64, r13 is the thread pointer. Never allocate this register. 1506b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // Note that this is over conservative, as it also prevents allocation of R31 1516b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // when the FP is not needed. 152b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng if (Subtarget.isPPC64()) { 153b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R13); 154b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R31); 1557194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 1567194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X0); 1577194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X1); 1587194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X13); 1597194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reserved.set(PPC::X31); 1606b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller 1616b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 1626b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller if (Subtarget.isSVR4ABI()) { 1636b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller Reserved.set(PPC::X2); 1646b16eff207f99bbde3c0f7340452a5287218772cTilmann Scheller } 1656d0e014b1fecb35a06e551165614c08edc30194aHal Finkel // Reserve X2 on Darwin to hack around the problem of save/restore of CR 166ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen // when the stack frame is too big to address directly; we need two regs. 167ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen // This is a hack. 168ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen if (Subtarget.isDarwinABI()) { 169ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen Reserved.set(PPC::X2); 170ee25bc294204ef326994d4142dd6bea9605e6a63Dale Johannesen } 171b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng } 1727194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 173c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov if (PPCFI->needsFP(MF)) 174b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng Reserved.set(PPC::R31); 1757194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 176b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng return Reserved; 177b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng} 178b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 179768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkelunsigned 180768c65f677af3f05c2e94982043f90a1bfaceda5Hal FinkelPPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 181768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel MachineFunction &MF) const { 182768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const unsigned DefaultSafety = 1; 184768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel 185768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel switch (RC->getID()) { 186768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel default: 187768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 0; 188768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::G8RCRegClassID: 189768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::GPRCRegClassID: { 190768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel unsigned FP = TFI->hasFP(MF) ? 1 : 0; 191768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 32 - FP - DefaultSafety; 192768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel } 193768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::F8RCRegClassID: 194768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::F4RCRegClassID: 195768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel case PPC::VRRCRegClassID: 196768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel return 32 - DefaultSafety; 1972e313caa3631e2c94bb6d81429b77a30b116b520Hal Finkel case PPC::CRRCRegClassID: 1982e313caa3631e2c94bb6d81429b77a30b116b520Hal Finkel return 8 - DefaultSafety; 199768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel } 200768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel} 201768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel 202fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkelbool 203fe5b65827f20a61bef817c6421f32b7e05d65cafHal FinkelPPCRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 204fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel switch (RC->getID()) { 205fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel case PPC::G8RCRegClassID: 206fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel case PPC::GPRCRegClassID: 207fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel case PPC::F8RCRegClassID: 208fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel case PPC::F4RCRegClassID: 209fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel case PPC::VRRCRegClassID: 210fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel return true; 211fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel default: 212fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel return false; 213fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel } 214fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel} 215fe5b65827f20a61bef817c6421f32b7e05d65cafHal Finkel 216f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 217f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// Stack Frame Processing methods 218f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 219f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 22021e463b2bf864671a87ebe386cb100ef9349a540Nate Begemanvoid PPCRegisterInfo:: 221f2ccb77ee9d8ab35866dae111fa36929689c7511Misha BrukmaneliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 222f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineBasicBlock::iterator I) const { 2238a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.GuaranteedTailCallOpt && 2248a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky I->getOpcode() == PPC::ADJCALLSTACKUP) { 225c12e5812be4dacc30781db84b045775c46580240Dale Johannesen // Add (actually subtract) back the amount the callee popped on return. 22630e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer if (int CalleeAmt = I->getOperand(1).getImm()) { 22730e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer bool is64Bit = Subtarget.isPPC64(); 22830e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer CalleeAmt *= -1; 22930e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 23030e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 23130e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 23230e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 23330e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 23430e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 235536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen MachineInstr *MI = I; 236536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI->getDebugLoc(); 23730e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer 23834247a0f356edf45ae3ad9ce04e1f90a77c6dba7Benjamin Kramer if (isInt<16>(CalleeAmt)) { 2392e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 2402e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel .addReg(StackReg, RegState::Kill) 2412e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel .addImm(CalleeAmt); 24230e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer } else { 24330e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer MachineBasicBlock::iterator MBBI = I; 244536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 24530e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer .addImm(CalleeAmt >> 16); 246536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 247587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(TmpReg, RegState::Kill) 24830e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer .addImm(CalleeAmt & 0xFFFF); 2492e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 2502e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel .addReg(StackReg, RegState::Kill) 25130e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer .addReg(TmpReg); 25230e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer } 25330e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer } 25430e62c098b5841259f8026df1c5c45c7c1182a38Arnold Schwaighofer } 2552f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 256f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MBB.erase(I); 257f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 258f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 2597194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 2607194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// register first and then a spilled callee-saved register if that fails. 2617194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingstatic 2627194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingunsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 2637194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC, int SPAdj) { 2647194aaf738a1b89441635340403f1c5b06ae18efBill Wendling assert(RS && "Register scavenging must be on"); 265c0823fe7c679ca8f7d1667a310c2fca97b9402d5Jakob Stoklund Olesen unsigned Reg = RS->FindUnusedReg(RC); 2667194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // FIXME: move ARM callee-saved reg scan to target independent code, then 2677194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // search for already spilled CS register here. 2687194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (Reg == 0) 2697194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reg = RS->scavengeRegister(RC, II, SPAdj); 2707194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return Reg; 2717194aaf738a1b89441635340403f1c5b06ae18efBill Wendling} 2727194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 2737194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// lowerDynamicAlloc - Generate the code for allocating an object in the 2742f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// current frame. The sequence of code with be in the general form 2752f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// 2760f8b53f19d29013ab18f3d444cea1e6305405611Dan Gohman/// addi R0, SP, \#frameSize ; get the address of the previous frame 2772f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 2780f8b53f19d29013ab18f3d444cea1e6305405611Dan Gohman/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 2792f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey/// 2807194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingvoid PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 2817194aaf738a1b89441635340403f1c5b06ae18efBill Wendling int SPAdj, RegScavenger *RS) const { 2822f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction. 2832f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineInstr &MI = *II; 2842f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction's basic block. 2852f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineBasicBlock &MBB = *MI.getParent(); 2862f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the basic block's function. 2872f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFunction &MF = *MBB.getParent(); 2882f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame info. 2892f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFrameInfo *MFI = MF.getFrameInfo(); 2902f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Determine whether 64-bit pointers are used. 2912f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey bool LP64 = Subtarget.isPPC64(); 292536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 2932f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 294fab0439c62984b3dc851eb99c31c4f6edda092a1Evan Cheng // Get the maximum call stack size. 2952f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 2962f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the total frame size. 2972f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned FrameSize = MFI->getStackSize(); 2982f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 2992f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get stack alignments. 30016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 3012f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned MaxAlign = MFI->getMaxAlignment(); 30238cb1381b5ec8c75242650491c2b8e7e8a302665Dale Johannesen if (MaxAlign > TargetAlign) 30338cb1381b5ec8c75242650491c2b8e7e8a302665Dale Johannesen report_fatal_error("Dynamic alloca with large aligns not supported"); 3042f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 3052f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Determine the previous frame's address. If FrameSize can't be 3062f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // represented as 16 bits or we need special alignment, then we load the 3072f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // previous frame's address from 0(SP). Why not do an addis of the hi? 3082f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 3092f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Constructing the constant and adding would take 3 instructions. 3102f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Fortunately, a frame greater than 32K is rare. 3117194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 3127194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 3137194aaf738a1b89441635340403f1c5b06ae18efBill Wendling const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 3147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3157194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // FIXME (64-bit): Use "findScratchRegister" 3167194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned Reg; 31794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (requiresRegisterScavenging(MF)) 3187194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reg = findScratchRegister(II, RS, RC, SPAdj); 3197194aaf738a1b89441635340403f1c5b06ae18efBill Wendling else 3207194aaf738a1b89441635340403f1c5b06ae18efBill Wendling Reg = PPC::R0; 3217194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 32234247a0f356edf45ae3ad9ce04e1f90a77c6dba7Benjamin Kramer if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 323536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 3242f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(PPC::R31) 3252f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addImm(FrameSize); 3262f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else if (LP64) { 32794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 328536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 32971a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(0) 33071a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1); 331880d0f6018b6928bdcad291be60c801238619955Bill Wendling else 332536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 33371a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(0) 33471a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1); 3352f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else { 336536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 3372f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addImm(0) 3382f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(PPC::R1); 3392f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } 3402f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 3417194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Grow the stack and update the stack pointer link, then determine the 3427194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // address of new allocated space. 3432f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey if (LP64) { 34494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 345ac81cc3282750d724f824547bc519caec0a01bceHal Finkel BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 346587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, RegState::Kill) 347ac81cc3282750d724f824547bc519caec0a01bceHal Finkel .addReg(PPC::X1) 34871a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(MI.getOperand(1).getReg()); 349880d0f6018b6928bdcad291be60c801238619955Bill Wendling else 350ac81cc3282750d724f824547bc519caec0a01bceHal Finkel BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 351587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::X0, RegState::Kill) 352ac81cc3282750d724f824547bc519caec0a01bceHal Finkel .addReg(PPC::X1) 35371a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(MI.getOperand(1).getReg()); 3547194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3557194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (!MI.getOperand(1).isKill()) 356536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 35771a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1) 35871a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize); 3597194aaf738a1b89441635340403f1c5b06ae18efBill Wendling else 3607194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Implicitly kill the register. 361536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 36271a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::X1) 36371a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize) 364587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 3652f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } else { 366ac81cc3282750d724f824547bc519caec0a01bceHal Finkel BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 367587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, RegState::Kill) 368ac81cc3282750d724f824547bc519caec0a01bceHal Finkel .addReg(PPC::R1) 3692f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey .addReg(MI.getOperand(1).getReg()); 3707194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 3717194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (!MI.getOperand(1).isKill()) 372536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 37371a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::R1) 37471a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize); 3757194aaf738a1b89441635340403f1c5b06ae18efBill Wendling else 3767194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Implicitly kill the register. 377536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 37871a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addReg(PPC::R1) 37971a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner .addImm(maxCallFrameSize) 380587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 3812f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey } 3822f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 3832f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Discard the DYNALLOC instruction. 3842f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MBB.erase(II); 3852f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey} 3862f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 3877194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 3887194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// reserving a whole register (R0), we scrounge for one here. This generates 3897194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// code like this: 3907194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// 3917194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// mfcr rA ; Move the conditional register into GPR rA. 3927194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 3937194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// stw rA, FI ; Store rA to the frame. 3947194aaf738a1b89441635340403f1c5b06ae18efBill Wendling/// 3957194aaf738a1b89441635340403f1c5b06ae18efBill Wendlingvoid PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 3967194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned FrameIndex, int SPAdj, 3977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling RegScavenger *RS) const { 3987194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Get the instruction. 399d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 4007194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Get the instruction's basic block. 4017194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock &MBB = *MI.getParent(); 402536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 4037194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 404fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // FIXME: Once LLVM supports creating virtual registers here, or the register 405fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // scavenger can return multiple registers, stop using reserved registers 406fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // here. 407fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) SPAdj; 408fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) RS; 409fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel 410951cd021c10966f3ae146588b2466deaef730cb6Roman Divacky bool LP64 = Subtarget.isPPC64(); 411fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 412fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (LP64 ? PPC::X0 : PPC::R0); 413fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel unsigned SrcReg = MI.getOperand(0).getReg(); 4147194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4152b5fab67c1a2d3ec1184c065e0a6bdaaaec9253aBill Wendling // We need to store the CR in the low 4-bits of the saved value. First, issue 4165f07d5224ddc32f405d7e19de8e58e91ab2816bcDale Johannesen // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 417234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 4185f07d5224ddc32f405d7e19de8e58e91ab2816bcDale Johannesen .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 4192b5fab67c1a2d3ec1184c065e0a6bdaaaec9253aBill Wendling 4207194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // If the saved register wasn't CR0, shift the bits left so that they are in 4217194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // CR0's slot. 4227194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (SrcReg != PPC::CR0) 4237194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // rlwinm rA, rA, ShiftBits, 0, 31. 424234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 425587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, RegState::Kill) 426966aeb5788c242cfaca35c56c0ddc0ff778d4376Evan Cheng .addImm(getPPCRegisterNumbering(SrcReg) * 4) 4277194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(0) 4287194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(31); 4297194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 430951cd021c10966f3ae146588b2466deaef730cb6Roman Divacky addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 431587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 4327194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIndex); 4337194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4347194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Discard the pseudo instruction. 4357194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MBB.erase(II); 4367194aaf738a1b89441635340403f1c5b06ae18efBill Wendling} 4377194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 438d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkelvoid PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 439d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned FrameIndex, int SPAdj, 440d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel RegScavenger *RS) const { 441d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Get the instruction. 442d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 443d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Get the instruction's basic block. 444d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MachineBasicBlock &MBB = *MI.getParent(); 445d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel DebugLoc dl = MI.getDebugLoc(); 446d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 447fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // FIXME: Once LLVM supports creating virtual registers here, or the register 448fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // scavenger can return multiple registers, stop using reserved registers 449fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel // here. 450fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) SPAdj; 451fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (void) RS; 452fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel 453fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel bool LP64 = Subtarget.isPPC64(); 454fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 455fed4d19eddcedf2a210a0ff3a290f4bf70927452Hal Finkel (LP64 ? PPC::X0 : PPC::R0); 456d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned DestReg = MI.getOperand(0).getReg(); 457d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel assert(MI.definesRegister(DestReg) && 458d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel "RESTORE_CR does not define its destination"); 459d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 460d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 461d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel Reg), FrameIndex); 462d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 463d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // If the reloaded register isn't CR0, shift the bits right so that they are 464d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // in the right CR's slot. 465d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if (DestReg != PPC::CR0) { 466d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 467d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // rlwinm r11, r11, 32-ShiftBits, 0, 31. 46817d2dbd5f9dd6c0de86398178f302ef46ba6ec79Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 469d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(Reg).addImm(32-ShiftBits).addImm(0) 470d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addImm(31); 471d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 472d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 473234bb38d6c421ea22229087a9835afe99e531276Hal Finkel BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 474d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(Reg); 475d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 476d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Discard the pseudo instruction. 477d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel MBB.erase(II); 478d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel} 479d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 480fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 481b58f498f7502e7e1833decbbbb4df771367c7341Jim GrosbachPPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 482fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS) const { 48397de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng assert(SPAdj == 0 && "Unexpected"); 48497de9138217d6f76f25100df272ec1a3c4d31aadEvan Cheng 4852f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction. 486f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineInstr &MI = *II; 4872f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction's basic block. 488f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineBasicBlock &MBB = *MI.getParent(); 4892f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the basic block's function. 490f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman MachineFunction &MF = *MBB.getParent(); 4912f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame info. 4922f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey MachineFrameInfo *MFI = MF.getFrameInfo(); 49316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 494536a2f1f8467a17f6d145bd83f25faae1f689839Dale Johannesen DebugLoc dl = MI.getDebugLoc(); 495b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman 4962f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Find out which operand is the frame index. 497f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner unsigned FIOperandNo = 0; 498d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman while (!MI.getOperand(FIOperandNo).isFI()) { 499f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner ++FIOperandNo; 500f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner assert(FIOperandNo != MI.getNumOperands() && 501f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner "Instr doesn't have FrameIndex operand!"); 502f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 5032f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Take into account whether it's an add or mem instruction 504f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 505518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (MI.isInlineAsm()) 506f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner OffsetOperandNo = FIOperandNo-1; 5077194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5082f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame index. 5098aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 5107194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5112f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the frame pointer save index. Users of this index are primarily 5122f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // DYNALLOC instructions. 5132f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 5142f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey int FPSI = FI->getFramePointerSaveIndex(); 5152f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Get the instruction opcode. 5162f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey unsigned OpC = MI.getOpcode(); 5172f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey 5182f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey // Special case for dynamic alloca. 5192f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey if (FPSI && FrameIndex == FPSI && 5202f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 5217194aaf738a1b89441635340403f1c5b06ae18efBill Wendling lowerDynamicAlloc(II, SPAdj, RS); 522fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 5237194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 5247194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 525d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 526d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if (requiresRegisterScavenging(MF)) { 527880d0f6018b6928bdcad291be60c801238619955Bill Wendling if (OpC == PPC::SPILL_CR) { 528880d0f6018b6928bdcad291be60c801238619955Bill Wendling lowerCRSpilling(II, FrameIndex, SPAdj, RS); 529fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 530d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } else if (OpC == PPC::RESTORE_CR) { 531d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel lowerCRRestore(II, FrameIndex, SPAdj, RS); 532d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel return; 533880d0f6018b6928bdcad291be60c801238619955Bill Wendling } 534d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 535f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 536f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 5376d0e014b1fecb35a06e551165614c08edc30194aHal Finkel 5386d0e014b1fecb35a06e551165614c08edc30194aHal Finkel bool is64Bit = Subtarget.isPPC64(); 539d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 5406d0e014b1fecb35a06e551165614c08edc30194aHal Finkel (is64Bit ? PPC::X31 : PPC::R31) : 5416d0e014b1fecb35a06e551165614c08edc30194aHal Finkel (is64Bit ? PPC::X1 : PPC::R1), 542f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner false); 543f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 5447ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // Figure out if the offset in the instruction is shifted right two bits. This 5457ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // is true for instructions like "STD", which the machine implicitly adds two 5467ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner // low zeros to. 5477ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner bool isIXAddr = false; 5482f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey switch (OpC) { 5497ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::LWA: 5507ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::LD: 5517ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::STD: 5527ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner case PPC::STD_32: 5537ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner isIXAddr = true; 5547ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner break; 5557ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner } 5567ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner 557f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // Now add the frame object offset to the offset from r1. 5582f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173Jim Laskey int Offset = MFI->getObjectOffset(FrameIndex); 5597ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner if (!isIXAddr) 5609a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner Offset += MI.getOperand(OffsetOperandNo).getImm(); 5617ffa9abdadd7e51726240b6a8352abda8edde869Chris Lattner else 5629a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 563f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 564f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // If we're not using a Frame Pointer that has been set to the value of the 565f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // SP before having the stack size subtracted from it, then add the stack size 566f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman // to Offset to get the correct offset. 5678c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen // Naked functions have stack size 0, although getStackSize may not reflect that 5688c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen // because we didn't call all the pieces that compute it for naked functions. 5698c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 5708c5358c93675b009ba2d57c3a5980f6bc58ba536Dale Johannesen Offset += MFI->getStackSize(); 571b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman 572789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // If we can, encode the offset directly into the instruction. If this is a 573789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 574789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 575789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // clear can be encoded. This is extremely uncommon, because normally you 576789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // only "std" to a stack slot that is at least 4-byte aligned, but it can 577789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner // happen in invalid code. 578f2f6182f6a88cf4b8d8cb95686d68aa14ddb6857Hal Finkel if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 579f2f6182f6a88cf4b8d8cb95686d68aa14ddb6857Hal Finkel (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 580789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner if (isIXAddr) 581f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner Offset >>= 2; // The actual encoded value has the low two bits zero. 582f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 583fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 584789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner } 5857194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5867194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // The offset doesn't fit into a single register, scavenge one to build the 5877194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // offset in. 5887194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5897194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned SReg; 5906d0e014b1fecb35a06e551165614c08edc30194aHal Finkel if (requiresRegisterScavenging(MF)) { 5916d0e014b1fecb35a06e551165614c08edc30194aHal Finkel const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 5926d0e014b1fecb35a06e551165614c08edc30194aHal Finkel const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 5936d0e014b1fecb35a06e551165614c08edc30194aHal Finkel SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 5946d0e014b1fecb35a06e551165614c08edc30194aHal Finkel } else 5956d0e014b1fecb35a06e551165614c08edc30194aHal Finkel SReg = is64Bit ? PPC::X0 : PPC::R0; 5967194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Insert a set of rA with the full offset value before the ld, st, or add 5986d0e014b1fecb35a06e551165614c08edc30194aHal Finkel BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 5997194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(Offset >> 16); 6006d0e014b1fecb35a06e551165614c08edc30194aHal Finkel BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 601587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SReg, RegState::Kill) 6027194aaf738a1b89441635340403f1c5b06ae18efBill Wendling .addImm(Offset); 6037194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 6047194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // Convert into indexed form of the instruction: 6057194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // 6067194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 6077194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 608789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner unsigned OperandBase; 6097194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 610518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (OpC != TargetOpcode::INLINEASM) { 611789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner assert(ImmToIdxMap.count(OpC) && 612789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner "No indexed form of load or store available!"); 613789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 6145080f4d9919d39b367891dc51e739c571a66036cChris Lattner MI.setDesc(TII.get(NewOpcode)); 615789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner OperandBase = 1; 616f602a2566845dc57444b9d40538c947b5ed23111Chris Lattner } else { 617789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner OperandBase = OffsetOperandNo; 618f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman } 619fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach 620789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 621789db09cde5f0cb2a0a5fc175c1141c760a3e807Chris Lattner MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 6222e95afa04cd1c89de7e4abaeead66cd8e51ec929Hal Finkel MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 623f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman} 624f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 6253f2bf85d14759cc4b28a86805f566ac805a54d00David Greeneunsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 62616c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 627d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 628a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6Chris Lattner if (!Subtarget.isPPC64()) 629d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 630a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6Chris Lattner else 631d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 6324188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey} 6334188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey 63462819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned PPCRegisterInfo::getEHExceptionRegister() const { 63562819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 63662819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 63762819f31440fe1b1415473a89b8683b5b690d5faJim Laskey 63862819f31440fe1b1415473a89b8683b5b690d5faJim Laskeyunsigned PPCRegisterInfo::getEHHandlerRegister() const { 63962819f31440fe1b1415473a89b8683b5b690d5faJim Laskey return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 64062819f31440fe1b1415473a89b8683b5b690d5faJim Laskey} 641