PPCRegisterInfo.cpp revision e46137f498fa81a088f13d24c79242eed3ff45a7 
1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "reginfo"
16#include "PPC.h"
17#include "PPCInstrBuilder.h"
18#include "PPCMachineFunctionInfo.h"
19#include "PPCRegisterInfo.h"
20#include "PPCFrameLowering.h"
21#include "PPCSubtarget.h"
22#include "llvm/CallingConv.h"
23#include "llvm/Constants.h"
24#include "llvm/Function.h"
25#include "llvm/Type.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RegisterScavenging.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/BitVector.h"
43#include "llvm/ADT/STLExtras.h"
44#include <cstdlib>
45
46#define GET_REGINFO_TARGET_DESC
47#include "PPCGenRegisterInfo.inc"
48
49namespace llvm {
50cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger",
51                                   cl::init(false),
52                                   cl::desc("Disable PPC32 register scavenger"),
53                                   cl::Hidden);
54cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger",
55                                   cl::init(false),
56                                   cl::desc("Disable PPC64 register scavenger"),
57                                   cl::Hidden);
58}
59
60using namespace llvm;
61
62// FIXME (64-bit): Should be inlined.
63bool
64PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
65  return ((!DisablePPC32RS && !Subtarget.isPPC64()) ||
66          (!DisablePPC64RS && Subtarget.isPPC64()));
67}
68
69PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
70                                 const TargetInstrInfo &tii)
71  : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
72                       ST.isPPC64() ? 0 : 1,
73                       ST.isPPC64() ? 0 : 1),
74    Subtarget(ST), TII(tii) {
75  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
76  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
77  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
78  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
79  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
80  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
81  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
82  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
83
84  // 64-bit
85  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
86  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
87  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
88  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
89  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
90}
91
92/// getPointerRegClass - Return the register class to use to hold pointers.
93/// This is used for addressing modes.
94const TargetRegisterClass *
95PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
96  if (Subtarget.isPPC64())
97    return &PPC::G8RCRegClass;
98  return &PPC::GPRCRegClass;
99}
100
101const uint16_t*
102PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
103  if (Subtarget.isDarwinABI())
104    return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
105                                 CSR_Darwin32_SaveList;
106
107  return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
108}
109
110const unsigned*
111PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
112  if (Subtarget.isDarwinABI())
113    return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
114                                 CSR_Darwin32_RegMask;
115
116  return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
117}
118
119BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
120  BitVector Reserved(getNumRegs());
121  const PPCFrameLowering *PPCFI =
122    static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
123
124  Reserved.set(PPC::R0);
125  Reserved.set(PPC::R1);
126  Reserved.set(PPC::LR);
127  Reserved.set(PPC::LR8);
128  Reserved.set(PPC::RM);
129
130  // The SVR4 ABI reserves r2 and r13
131  if (Subtarget.isSVR4ABI()) {
132    Reserved.set(PPC::R2);  // System-reserved register
133    Reserved.set(PPC::R13); // Small Data Area pointer register
134  }
135  // Reserve R2 on Darwin to hack around the problem of save/restore of CR
136  // when the stack frame is too big to address directly; we need two regs.
137  // This is a hack.
138  if (Subtarget.isDarwinABI()) {
139    Reserved.set(PPC::R2);
140  }
141
142  // On PPC64, r13 is the thread pointer. Never allocate this register.
143  // Note that this is over conservative, as it also prevents allocation of R31
144  // when the FP is not needed.
145  if (Subtarget.isPPC64()) {
146    Reserved.set(PPC::R13);
147    Reserved.set(PPC::R31);
148
149    Reserved.set(PPC::X0);
150    Reserved.set(PPC::X1);
151    Reserved.set(PPC::X13);
152    Reserved.set(PPC::X31);
153
154    // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
155    if (Subtarget.isSVR4ABI()) {
156      Reserved.set(PPC::X2);
157    }
158    // Reserve X2 on Darwin to hack around the problem of save/restore of CR
159    // when the stack frame is too big to address directly; we need two regs.
160    // This is a hack.
161    if (Subtarget.isDarwinABI()) {
162      Reserved.set(PPC::X2);
163    }
164  }
165
166  if (PPCFI->needsFP(MF))
167    Reserved.set(PPC::R31);
168
169  return Reserved;
170}
171
172unsigned
173PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
174                                         MachineFunction &MF) const {
175  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
176  const unsigned DefaultSafety = 1;
177
178  switch (RC->getID()) {
179  default:
180    return 0;
181  case PPC::G8RCRegClassID:
182  case PPC::GPRCRegClassID: {
183    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
184    return 32 - FP - DefaultSafety;
185  }
186  case PPC::F8RCRegClassID:
187  case PPC::F4RCRegClassID:
188  case PPC::VRRCRegClassID:
189    return 32 - DefaultSafety;
190  case PPC::CRRCRegClassID:
191    return 8 - DefaultSafety;
192  }
193}
194
195//===----------------------------------------------------------------------===//
196// Stack Frame Processing methods
197//===----------------------------------------------------------------------===//
198
199void PPCRegisterInfo::
200eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
201                              MachineBasicBlock::iterator I) const {
202  if (MF.getTarget().Options.GuaranteedTailCallOpt &&
203      I->getOpcode() == PPC::ADJCALLSTACKUP) {
204    // Add (actually subtract) back the amount the callee popped on return.
205    if (int CalleeAmt =  I->getOperand(1).getImm()) {
206      bool is64Bit = Subtarget.isPPC64();
207      CalleeAmt *= -1;
208      unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
209      unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
210      unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
211      unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
212      unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
213      unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
214      MachineInstr *MI = I;
215      DebugLoc dl = MI->getDebugLoc();
216
217      if (isInt<16>(CalleeAmt)) {
218        BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
219          .addReg(StackReg, RegState::Kill)
220          .addImm(CalleeAmt);
221      } else {
222        MachineBasicBlock::iterator MBBI = I;
223        BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
224          .addImm(CalleeAmt >> 16);
225        BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
226          .addReg(TmpReg, RegState::Kill)
227          .addImm(CalleeAmt & 0xFFFF);
228        BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
229          .addReg(StackReg, RegState::Kill)
230          .addReg(TmpReg);
231      }
232    }
233  }
234  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
235  MBB.erase(I);
236}
237
238/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
239/// register first and then a spilled callee-saved register if that fails.
240static
241unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
242                             const TargetRegisterClass *RC, int SPAdj) {
243  assert(RS && "Register scavenging must be on");
244  unsigned Reg = RS->FindUnusedReg(RC);
245  // FIXME: move ARM callee-saved reg scan to target independent code, then
246  // search for already spilled CS register here.
247  if (Reg == 0)
248    Reg = RS->scavengeRegister(RC, II, SPAdj);
249  return Reg;
250}
251
252/// lowerDynamicAlloc - Generate the code for allocating an object in the
253/// current frame.  The sequence of code with be in the general form
254///
255///   addi   R0, SP, \#frameSize ; get the address of the previous frame
256///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
257///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
258///
259void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
260                                        int SPAdj, RegScavenger *RS) const {
261  // Get the instruction.
262  MachineInstr &MI = *II;
263  // Get the instruction's basic block.
264  MachineBasicBlock &MBB = *MI.getParent();
265  // Get the basic block's function.
266  MachineFunction &MF = *MBB.getParent();
267  // Get the frame info.
268  MachineFrameInfo *MFI = MF.getFrameInfo();
269  // Determine whether 64-bit pointers are used.
270  bool LP64 = Subtarget.isPPC64();
271  DebugLoc dl = MI.getDebugLoc();
272
273  // Get the maximum call stack size.
274  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
275  // Get the total frame size.
276  unsigned FrameSize = MFI->getStackSize();
277
278  // Get stack alignments.
279  unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
280  unsigned MaxAlign = MFI->getMaxAlignment();
281  if (MaxAlign > TargetAlign)
282    report_fatal_error("Dynamic alloca with large aligns not supported");
283
284  // Determine the previous frame's address.  If FrameSize can't be
285  // represented as 16 bits or we need special alignment, then we load the
286  // previous frame's address from 0(SP).  Why not do an addis of the hi?
287  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
288  // Constructing the constant and adding would take 3 instructions.
289  // Fortunately, a frame greater than 32K is rare.
290  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
291  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
292  const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
293
294  // FIXME (64-bit): Use "findScratchRegister"
295  unsigned Reg;
296  if (requiresRegisterScavenging(MF))
297    Reg = findScratchRegister(II, RS, RC, SPAdj);
298  else
299    Reg = PPC::R0;
300
301  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
302    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
303      .addReg(PPC::R31)
304      .addImm(FrameSize);
305  } else if (LP64) {
306    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
307      BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
308        .addImm(0)
309        .addReg(PPC::X1);
310    else
311      BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
312        .addImm(0)
313        .addReg(PPC::X1);
314  } else {
315    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
316      .addImm(0)
317      .addReg(PPC::R1);
318  }
319
320  // Grow the stack and update the stack pointer link, then determine the
321  // address of new allocated space.
322  if (LP64) {
323    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
324      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
325        .addReg(Reg, RegState::Kill)
326        .addReg(PPC::X1, RegState::Define)
327        .addReg(MI.getOperand(1).getReg());
328    else
329      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
330        .addReg(PPC::X0, RegState::Kill)
331        .addReg(PPC::X1, RegState::Define)
332        .addReg(MI.getOperand(1).getReg());
333
334    if (!MI.getOperand(1).isKill())
335      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
336        .addReg(PPC::X1)
337        .addImm(maxCallFrameSize);
338    else
339      // Implicitly kill the register.
340      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
341        .addReg(PPC::X1)
342        .addImm(maxCallFrameSize)
343        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
344  } else {
345    BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
346      .addReg(Reg, RegState::Kill)
347      .addReg(PPC::R1, RegState::Define)
348      .addReg(MI.getOperand(1).getReg());
349
350    if (!MI.getOperand(1).isKill())
351      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
352        .addReg(PPC::R1)
353        .addImm(maxCallFrameSize);
354    else
355      // Implicitly kill the register.
356      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
357        .addReg(PPC::R1)
358        .addImm(maxCallFrameSize)
359        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
360  }
361
362  // Discard the DYNALLOC instruction.
363  MBB.erase(II);
364}
365
366/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
367/// reserving a whole register (R0), we scrounge for one here. This generates
368/// code like this:
369///
370///   mfcr rA                  ; Move the conditional register into GPR rA.
371///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
372///   stw rA, FI               ; Store rA to the frame.
373///
374void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
375                                      unsigned FrameIndex, int SPAdj,
376                                      RegScavenger *RS) const {
377  // Get the instruction.
378  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
379  // Get the instruction's basic block.
380  MachineBasicBlock &MBB = *MI.getParent();
381  DebugLoc dl = MI.getDebugLoc();
382
383  // FIXME: Once LLVM supports creating virtual registers here, or the register
384  // scavenger can return multiple registers, stop using reserved registers
385  // here.
386  (void) SPAdj;
387  (void) RS;
388
389  bool LP64 = Subtarget.isPPC64();
390  unsigned Reg = Subtarget.isDarwinABI() ?  (LP64 ? PPC::X2 : PPC::R2) :
391                                            (LP64 ? PPC::X0 : PPC::R0);
392  unsigned SrcReg = MI.getOperand(0).getReg();
393
394  // We need to store the CR in the low 4-bits of the saved value. First, issue
395  // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
396  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
397          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
398
399  // If the saved register wasn't CR0, shift the bits left so that they are in
400  // CR0's slot.
401  if (SrcReg != PPC::CR0)
402    // rlwinm rA, rA, ShiftBits, 0, 31.
403    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
404      .addReg(Reg, RegState::Kill)
405      .addImm(getPPCRegisterNumbering(SrcReg) * 4)
406      .addImm(0)
407      .addImm(31);
408
409  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
410                    .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
411                    FrameIndex);
412
413  // Discard the pseudo instruction.
414  MBB.erase(II);
415}
416
417void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
418                                      unsigned FrameIndex, int SPAdj,
419                                      RegScavenger *RS) const {
420  // Get the instruction.
421  MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
422  // Get the instruction's basic block.
423  MachineBasicBlock &MBB = *MI.getParent();
424  DebugLoc dl = MI.getDebugLoc();
425
426  // FIXME: Once LLVM supports creating virtual registers here, or the register
427  // scavenger can return multiple registers, stop using reserved registers
428  // here.
429  (void) SPAdj;
430  (void) RS;
431
432  bool LP64 = Subtarget.isPPC64();
433  unsigned Reg = Subtarget.isDarwinABI() ?  (LP64 ? PPC::X2 : PPC::R2) :
434                                            (LP64 ? PPC::X0 : PPC::R0);
435  unsigned DestReg = MI.getOperand(0).getReg();
436  assert(MI.definesRegister(DestReg) &&
437    "RESTORE_CR does not define its destination");
438
439  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
440                              Reg), FrameIndex);
441
442  // If the reloaded register isn't CR0, shift the bits right so that they are
443  // in the right CR's slot.
444  if (DestReg != PPC::CR0) {
445    unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
446    // rlwinm r11, r11, 32-ShiftBits, 0, 31.
447    BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
448             .addReg(Reg).addImm(32-ShiftBits).addImm(0)
449             .addImm(31);
450  }
451
452  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
453             .addReg(Reg);
454
455  // Discard the pseudo instruction.
456  MBB.erase(II);
457}
458
459void
460PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
461                                     int SPAdj, RegScavenger *RS) const {
462  assert(SPAdj == 0 && "Unexpected");
463
464  // Get the instruction.
465  MachineInstr &MI = *II;
466  // Get the instruction's basic block.
467  MachineBasicBlock &MBB = *MI.getParent();
468  // Get the basic block's function.
469  MachineFunction &MF = *MBB.getParent();
470  // Get the frame info.
471  MachineFrameInfo *MFI = MF.getFrameInfo();
472  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
473  DebugLoc dl = MI.getDebugLoc();
474
475  // Find out which operand is the frame index.
476  unsigned FIOperandNo = 0;
477  while (!MI.getOperand(FIOperandNo).isFI()) {
478    ++FIOperandNo;
479    assert(FIOperandNo != MI.getNumOperands() &&
480           "Instr doesn't have FrameIndex operand!");
481  }
482  // Take into account whether it's an add or mem instruction
483  unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
484  if (MI.isInlineAsm())
485    OffsetOperandNo = FIOperandNo-1;
486
487  // Get the frame index.
488  int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
489
490  // Get the frame pointer save index.  Users of this index are primarily
491  // DYNALLOC instructions.
492  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
493  int FPSI = FI->getFramePointerSaveIndex();
494  // Get the instruction opcode.
495  unsigned OpC = MI.getOpcode();
496
497  // Special case for dynamic alloca.
498  if (FPSI && FrameIndex == FPSI &&
499      (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
500    lowerDynamicAlloc(II, SPAdj, RS);
501    return;
502  }
503
504  // Special case for pseudo-ops SPILL_CR and RESTORE_CR.
505  if (requiresRegisterScavenging(MF)) {
506    if (OpC == PPC::SPILL_CR) {
507      lowerCRSpilling(II, FrameIndex, SPAdj, RS);
508      return;
509    } else if (OpC == PPC::RESTORE_CR) {
510      lowerCRRestore(II, FrameIndex, SPAdj, RS);
511      return;
512    }
513  }
514
515  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
516
517  bool is64Bit = Subtarget.isPPC64();
518  MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
519                                              (is64Bit ? PPC::X31 : PPC::R31) :
520                                                (is64Bit ? PPC::X1 : PPC::R1),
521                                              false);
522
523  // Figure out if the offset in the instruction is shifted right two bits. This
524  // is true for instructions like "STD", which the machine implicitly adds two
525  // low zeros to.
526  bool isIXAddr = false;
527  switch (OpC) {
528  case PPC::LWA:
529  case PPC::LD:
530  case PPC::STD:
531  case PPC::STD_32:
532    isIXAddr = true;
533    break;
534  }
535
536  // Now add the frame object offset to the offset from r1.
537  int Offset = MFI->getObjectOffset(FrameIndex);
538  if (!isIXAddr)
539    Offset += MI.getOperand(OffsetOperandNo).getImm();
540  else
541    Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
542
543  // If we're not using a Frame Pointer that has been set to the value of the
544  // SP before having the stack size subtracted from it, then add the stack size
545  // to Offset to get the correct offset.
546  // Naked functions have stack size 0, although getStackSize may not reflect that
547  // because we didn't call all the pieces that compute it for naked functions.
548  if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
549    Offset += MFI->getStackSize();
550
551  // If we can, encode the offset directly into the instruction.  If this is a
552  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
553  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
554  // clear can be encoded.  This is extremely uncommon, because normally you
555  // only "std" to a stack slot that is at least 4-byte aligned, but it can
556  // happen in invalid code.
557  if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
558    if (isIXAddr)
559      Offset >>= 2;    // The actual encoded value has the low two bits zero.
560    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
561    return;
562  }
563
564  // The offset doesn't fit into a single register, scavenge one to build the
565  // offset in.
566
567  unsigned SReg;
568  if (requiresRegisterScavenging(MF)) {
569    const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
570    const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
571    SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj);
572  } else
573    SReg = is64Bit ? PPC::X0 : PPC::R0;
574
575  // Insert a set of rA with the full offset value before the ld, st, or add
576  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
577    .addImm(Offset >> 16);
578  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
579    .addReg(SReg, RegState::Kill)
580    .addImm(Offset);
581
582  // Convert into indexed form of the instruction:
583  //
584  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
585  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
586  unsigned OperandBase;
587
588  if (OpC != TargetOpcode::INLINEASM) {
589    assert(ImmToIdxMap.count(OpC) &&
590           "No indexed form of load or store available!");
591    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
592    MI.setDesc(TII.get(NewOpcode));
593    OperandBase = 1;
594  } else {
595    OperandBase = OffsetOperandNo;
596  }
597
598  unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
599  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
600  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
601}
602
603unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
604  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
605
606  if (!Subtarget.isPPC64())
607    return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
608  else
609    return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
610}
611
612unsigned PPCRegisterInfo::getEHExceptionRegister() const {
613  return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
614}
615
616unsigned PPCRegisterInfo::getEHHandlerRegister() const {
617  return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
618}
619