PPCRegisterInfo.cpp revision f9568d8700d5389799796262cde313bb5c7d588a 
1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "reginfo"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCRegisterInfo.h"
18#include "llvm/Constants.h"
19#include "llvm/Type.h"
20#include "llvm/CodeGen/ValueTypes.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineDebugInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineLocation.h"
26#include "llvm/CodeGen/SelectionDAGNodes.h"
27#include "llvm/Target/TargetFrameInfo.h"
28#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/ADT/STLExtras.h"
35#include <cstdlib>
36#include <iostream>
37using namespace llvm;
38
39/// getRegisterNumbering - Given the enum value for some register, e.g.
40/// PPC::F14, return the number that it corresponds to (e.g. 14).
41unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
42  switch (RegEnum) {
43    case PPC::R0 :  case PPC::F0 :  case PPC::V0 : case PPC::CR0:  return  0;
44    case PPC::R1 :  case PPC::F1 :  case PPC::V1 : case PPC::CR1:  return  1;
45    case PPC::R2 :  case PPC::F2 :  case PPC::V2 : case PPC::CR2:  return  2;
46    case PPC::R3 :  case PPC::F3 :  case PPC::V3 : case PPC::CR3:  return  3;
47    case PPC::R4 :  case PPC::F4 :  case PPC::V4 : case PPC::CR4:  return  4;
48    case PPC::R5 :  case PPC::F5 :  case PPC::V5 : case PPC::CR5:  return  5;
49    case PPC::R6 :  case PPC::F6 :  case PPC::V6 : case PPC::CR6:  return  6;
50    case PPC::R7 :  case PPC::F7 :  case PPC::V7 : case PPC::CR7:  return  7;
51    case PPC::R8 :  case PPC::F8 :  case PPC::V8 : return  8;
52    case PPC::R9 :  case PPC::F9 :  case PPC::V9 : return  9;
53    case PPC::R10:  case PPC::F10:  case PPC::V10: return 10;
54    case PPC::R11:  case PPC::F11:  case PPC::V11: return 11;
55    case PPC::R12:  case PPC::F12:  case PPC::V12: return 12;
56    case PPC::R13:  case PPC::F13:  case PPC::V13: return 13;
57    case PPC::R14:  case PPC::F14:  case PPC::V14: return 14;
58    case PPC::R15:  case PPC::F15:  case PPC::V15: return 15;
59    case PPC::R16:  case PPC::F16:  case PPC::V16: return 16;
60    case PPC::R17:  case PPC::F17:  case PPC::V17: return 17;
61    case PPC::R18:  case PPC::F18:  case PPC::V18: return 18;
62    case PPC::R19:  case PPC::F19:  case PPC::V19: return 19;
63    case PPC::R20:  case PPC::F20:  case PPC::V20: return 20;
64    case PPC::R21:  case PPC::F21:  case PPC::V21: return 21;
65    case PPC::R22:  case PPC::F22:  case PPC::V22: return 22;
66    case PPC::R23:  case PPC::F23:  case PPC::V23: return 23;
67    case PPC::R24:  case PPC::F24:  case PPC::V24: return 24;
68    case PPC::R25:  case PPC::F25:  case PPC::V25: return 25;
69    case PPC::R26:  case PPC::F26:  case PPC::V26: return 26;
70    case PPC::R27:  case PPC::F27:  case PPC::V27: return 27;
71    case PPC::R28:  case PPC::F28:  case PPC::V28: return 28;
72    case PPC::R29:  case PPC::F29:  case PPC::V29: return 29;
73    case PPC::R30:  case PPC::F30:  case PPC::V30: return 30;
74    case PPC::R31:  case PPC::F31:  case PPC::V31: return 31;
75    default:
76      std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
77      abort();
78  }
79}
80
81PPCRegisterInfo::PPCRegisterInfo()
82  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
83  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
84  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
85  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
86  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
87  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
88  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
89  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
90  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
91}
92
93void
94PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
95                                     MachineBasicBlock::iterator MI,
96                                     unsigned SrcReg, int FrameIdx,
97                                     const TargetRegisterClass *RC) const {
98  if (SrcReg == PPC::LR) {
99    // FIXME: this spills LR immediately to memory in one step.  To do this, we
100    // use R11, which we know cannot be used in the prolog/epilog.  This is a
101    // hack.
102    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
103    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
104  } else if (RC == PPC::CRRCRegisterClass) {
105    BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
106    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
107  } else if (RC == PPC::GPRCRegisterClass) {
108    addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
109  } else if (RC == PPC::G8RCRegisterClass) {
110    addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
111  } else if (RC == PPC::F8RCRegisterClass) {
112    addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
113  } else if (RC == PPC::F4RCRegisterClass) {
114    addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
115  } else if (RC == PPC::VRRCRegisterClass) {
116    // We don't have indexed addressing for vector loads.  Emit:
117    // R11 = ADDI FI#
118    // Dest = LVX R0, R11
119    //
120    // FIXME: We use R0 here, because it isn't available for RA.
121    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
122    BuildMI(MBB, MI, PPC::STVX, 3)
123      .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
124  } else {
125    assert(0 && "Unknown regclass!");
126    abort();
127  }
128}
129
130void
131PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
132                                        MachineBasicBlock::iterator MI,
133                                        unsigned DestReg, int FrameIdx,
134                                        const TargetRegisterClass *RC) const {
135  if (DestReg == PPC::LR) {
136    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
137    BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
138  } else if (RC == PPC::CRRCRegisterClass) {
139    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
140    BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
141  } else if (RC == PPC::GPRCRegisterClass) {
142    addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
143  } else if (RC == PPC::G8RCRegisterClass) {
144    addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
145  } else if (RC == PPC::F8RCRegisterClass) {
146    addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
147  } else if (RC == PPC::F4RCRegisterClass) {
148    addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
149  } else if (RC == PPC::VRRCRegisterClass) {
150    // We don't have indexed addressing for vector loads.  Emit:
151    // R11 = ADDI FI#
152    // Dest = LVX R0, R11
153    //
154    // FIXME: We use R0 here, because it isn't available for RA.
155    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
156    BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
157  } else {
158    assert(0 && "Unknown regclass!");
159    abort();
160  }
161}
162
163void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
164                                   MachineBasicBlock::iterator MI,
165                                   unsigned DestReg, unsigned SrcReg,
166                                   const TargetRegisterClass *RC) const {
167  if (RC == PPC::GPRCRegisterClass) {
168    BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
169  } else if (RC == PPC::G8RCRegisterClass) {
170    BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
171  } else if (RC == PPC::F4RCRegisterClass) {
172    BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
173  } else if (RC == PPC::F8RCRegisterClass) {
174    BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
175  } else if (RC == PPC::CRRCRegisterClass) {
176    BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
177  } else if (RC == PPC::VRRCRegisterClass) {
178    BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
179  } else {
180    std::cerr << "Attempt to copy register that is not GPR or FPR";
181    abort();
182  }
183}
184
185/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
186/// copy instructions, turning them into load/store instructions.
187MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
188                                                 unsigned OpNum,
189                                                 int FrameIndex) const {
190  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
191  // it takes more than one instruction to store it.
192  unsigned Opc = MI->getOpcode();
193
194  if ((Opc == PPC::OR4 &&
195       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
196    if (OpNum == 0) {  // move -> store
197      unsigned InReg = MI->getOperand(1).getReg();
198      return addFrameReference(BuildMI(PPC::STW,
199                                       3).addReg(InReg), FrameIndex);
200    } else {           // move -> load
201      unsigned OutReg = MI->getOperand(0).getReg();
202      return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
203    }
204  } else if ((Opc == PPC::OR8 &&
205              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
206    if (OpNum == 0) {  // move -> store
207      unsigned InReg = MI->getOperand(1).getReg();
208      return addFrameReference(BuildMI(PPC::STD,
209                                       3).addReg(InReg), FrameIndex);
210    } else {           // move -> load
211      unsigned OutReg = MI->getOperand(0).getReg();
212      return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
213    }
214  } else if (Opc == PPC::FMRD) {
215    if (OpNum == 0) {  // move -> store
216      unsigned InReg = MI->getOperand(1).getReg();
217      return addFrameReference(BuildMI(PPC::STFD,
218                                       3).addReg(InReg), FrameIndex);
219    } else {           // move -> load
220      unsigned OutReg = MI->getOperand(0).getReg();
221      return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
222    }
223  } else if (Opc == PPC::FMRS) {
224    if (OpNum == 0) {  // move -> store
225      unsigned InReg = MI->getOperand(1).getReg();
226      return addFrameReference(BuildMI(PPC::STFS,
227                                       3).addReg(InReg), FrameIndex);
228    } else {           // move -> load
229      unsigned OutReg = MI->getOperand(0).getReg();
230      return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
231    }
232  }
233  return 0;
234}
235
236//===----------------------------------------------------------------------===//
237// Stack Frame Processing methods
238//===----------------------------------------------------------------------===//
239
240// hasFP - Return true if the specified function should have a dedicated frame
241// pointer register.  This is true if the function has variable sized allocas or
242// if frame pointer elimination is disabled.
243//
244static bool hasFP(const MachineFunction &MF) {
245  const MachineFrameInfo *MFI = MF.getFrameInfo();
246  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
247
248  // If frame pointers are forced, or if there are variable sized stack objects,
249  // use a frame pointer.
250  //
251  return NoFramePointerElim || MFI->hasVarSizedObjects();
252}
253
254void PPCRegisterInfo::
255eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
256                              MachineBasicBlock::iterator I) const {
257  if (hasFP(MF)) {
258    // If we have a frame pointer, convert as follows:
259    // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
260    // ADJCALLSTACKUP   -> addi, r1, r1, amount
261    MachineInstr *Old = I;
262    unsigned Amount = Old->getOperand(0).getImmedValue();
263    if (Amount != 0) {
264      // We need to keep the stack aligned properly.  To do this, we round the
265      // amount of space needed for the outgoing arguments up to the next
266      // alignment boundary.
267      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
268      Amount = (Amount+Align-1)/Align*Align;
269
270      // Replace the pseudo instruction with a new instruction...
271      if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
272        BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
273      } else {
274        assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
275        BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
276      }
277    }
278  }
279  MBB.erase(I);
280}
281
282void
283PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
284  unsigned i = 0;
285  MachineInstr &MI = *II;
286  MachineBasicBlock &MBB = *MI.getParent();
287  MachineFunction &MF = *MBB.getParent();
288
289  while (!MI.getOperand(i).isFrameIndex()) {
290    ++i;
291    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
292  }
293
294  int FrameIndex = MI.getOperand(i).getFrameIndex();
295
296  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
297  MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
298
299  // Take into account whether it's an add or mem instruction
300  unsigned OffIdx = (i == 2) ? 1 : 2;
301
302  // Now add the frame object offset to the offset from r1.
303  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
304               MI.getOperand(OffIdx).getImmedValue();
305
306  // If we're not using a Frame Pointer that has been set to the value of the
307  // SP before having the stack size subtracted from it, then add the stack size
308  // to Offset to get the correct offset.
309  Offset += MF.getFrameInfo()->getStackSize();
310
311  if (Offset > 32767 || Offset < -32768) {
312    // Insert a set of r0 with the full offset value before the ld, st, or add
313    MachineBasicBlock *MBB = MI.getParent();
314    BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
315    BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
316
317    // convert into indexed form of the instruction
318    // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
319    // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
320    assert(ImmToIdxMap.count(MI.getOpcode()) &&
321           "No indexed form of load or store available!");
322    unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
323    MI.setOpcode(NewOpcode);
324    MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
325    MI.SetMachineOperandReg(2, PPC::R0);
326  } else {
327    switch (MI.getOpcode()) {
328    case PPC::LWA:
329    case PPC::LD:
330    case PPC::STD:
331    case PPC::STD_32:
332      assert((Offset & 3) == 0 && "Invalid frame offset!");
333      Offset >>= 2;    // The actual encoded value has the low two bits zero.
334      break;
335    }
336    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
337                              Offset);
338  }
339}
340
341/// VRRegNo - Map from a numbered VR register to its enum value.
342///
343static const unsigned short VRRegNo[] = {
344 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
345 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
346 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
347 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
348};
349
350/// RemoveVRSaveCode - We have found that this function does not need any code
351/// to manipulate the VRSAVE register, even though it uses vector registers.
352/// This can happen when the only registers used are known to be live in or out
353/// of the function.  Remove all of the VRSAVE related code from the function.
354static void RemoveVRSaveCode(MachineInstr *MI) {
355  MachineBasicBlock *Entry = MI->getParent();
356  MachineFunction *MF = Entry->getParent();
357
358  // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
359  MachineBasicBlock::iterator MBBI = MI;
360  ++MBBI;
361  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
362  MBBI->eraseFromParent();
363
364  bool RemovedAllMTVRSAVEs = true;
365  // See if we can find and remove the MTVRSAVE instruction from all of the
366  // epilog blocks.
367  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
368  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
369    // If last instruction is a return instruction, add an epilogue
370    if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
371      bool FoundIt = false;
372      for (MBBI = I->end(); MBBI != I->begin(); ) {
373        --MBBI;
374        if (MBBI->getOpcode() == PPC::MTVRSAVE) {
375          MBBI->eraseFromParent();  // remove it.
376          FoundIt = true;
377          break;
378        }
379      }
380      RemovedAllMTVRSAVEs &= FoundIt;
381    }
382  }
383
384  // If we found and removed all MTVRSAVE instructions, remove the read of
385  // VRSAVE as well.
386  if (RemovedAllMTVRSAVEs) {
387    MBBI = MI;
388    assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
389    --MBBI;
390    assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
391    MBBI->eraseFromParent();
392  }
393
394  // Finally, nuke the UPDATE_VRSAVE.
395  MI->eraseFromParent();
396}
397
398// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
399// instruction selector.  Based on the vector registers that have been used,
400// transform this into the appropriate ORI instruction.
401static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
402  unsigned UsedRegMask = 0;
403  for (unsigned i = 0; i != 32; ++i)
404    if (UsedRegs[VRRegNo[i]])
405      UsedRegMask |= 1 << (31-i);
406
407  // Live in and live out values already must be in the mask, so don't bother
408  // marking them.
409  MachineFunction *MF = MI->getParent()->getParent();
410  for (MachineFunction::livein_iterator I =
411       MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
412    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
413    if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
414      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
415  }
416  for (MachineFunction::liveout_iterator I =
417       MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
418    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
419    if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
420      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
421  }
422
423  unsigned SrcReg = MI->getOperand(1).getReg();
424  unsigned DstReg = MI->getOperand(0).getReg();
425  // If no registers are used, turn this into a copy.
426  if (UsedRegMask == 0) {
427    // Remove all VRSAVE code.
428    RemoveVRSaveCode(MI);
429    return;
430  } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
431    BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
432        .addReg(SrcReg).addImm(UsedRegMask);
433  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
434    BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
435        .addReg(SrcReg).addImm(UsedRegMask >> 16);
436  } else {
437    BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
438       .addReg(SrcReg).addImm(UsedRegMask >> 16);
439    BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
440      .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
441  }
442
443  // Remove the old UPDATE_VRSAVE instruction.
444  MI->eraseFromParent();
445}
446
447
448void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
449  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
450  MachineBasicBlock::iterator MBBI = MBB.begin();
451  MachineFrameInfo *MFI = MF.getFrameInfo();
452  MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
453
454  // Do we have a frame pointer for this function?
455  bool HasFP = hasFP(MF);
456
457  // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
458  // process it.
459  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
460    if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
461      HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
462      break;
463    }
464  }
465
466  // Move MBBI back to the beginning of the function.
467  MBBI = MBB.begin();
468
469  // Get the number of bytes to allocate from the FrameInfo
470  unsigned NumBytes = MFI->getStackSize();
471
472  // Get the alignments provided by the target, and the maximum alignment
473  // (if any) of the fixed frame objects.
474  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
475  unsigned MaxAlign = MFI->getMaxAlignment();
476
477  // If we have calls, we cannot use the red zone to store callee save registers
478  // and we must set up a stack frame, so calculate the necessary size here.
479  if (MFI->hasCalls()) {
480    // We reserve argument space for call sites in the function immediately on
481    // entry to the current function.  This eliminates the need for add/sub
482    // brackets around call sites.
483    NumBytes += MFI->getMaxCallFrameSize();
484  }
485
486  // If we are a leaf function, and use up to 224 bytes of stack space,
487  // and don't have a frame pointer, then we do not need to adjust the stack
488  // pointer (we fit in the Red Zone).
489  if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
490                          MaxAlign <= TargetAlign)) {
491    MFI->setStackSize(0);
492    return;
493  }
494
495  // Add the size of R1 to  NumBytes size for the store of R1 to the bottom
496  // of the stack and round the size to a multiple of the alignment.
497  unsigned Align = std::max(TargetAlign, MaxAlign);
498  unsigned GPRSize = 4;
499  unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
500  NumBytes = (NumBytes+Size+Align-1)/Align*Align;
501
502  // Update frame info to pretend that this is part of the stack...
503  MFI->setStackSize(NumBytes);
504  int NegNumbytes = -NumBytes;
505
506  // Adjust stack pointer: r1 -= numbytes.
507  // If there is a preferred stack alignment, align R1 now
508  if (MaxAlign > TargetAlign) {
509    assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
510    assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!");
511    BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
512      .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
513    BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
514      .addSImm(MaxAlign-NumBytes);
515    BuildMI(MBB, MBBI, PPC::STWUX, 3)
516      .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
517  } else if (NumBytes <= 32768) {
518    BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
519      .addReg(PPC::R1);
520  } else {
521    BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
522    BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
523      .addImm(NegNumbytes & 0xFFFF);
524    BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
525      .addReg(PPC::R0);
526  }
527
528  if (DebugInfo && DebugInfo->hasInfo()) {
529    std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
530    unsigned LabelID = DebugInfo->NextLabelID();
531
532    // Show update of SP.
533    MachineLocation Dst(MachineLocation::VirtualFP);
534    MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
535    Moves.push_back(new MachineMove(LabelID, Dst, Src));
536
537    BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
538  }
539
540  // If there is a frame pointer, copy R1 (SP) into R31 (FP)
541  if (HasFP) {
542    BuildMI(MBB, MBBI, PPC::STW, 3)
543      .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
544    BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
545  }
546}
547
548void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
549                                   MachineBasicBlock &MBB) const {
550  MachineBasicBlock::iterator MBBI = prior(MBB.end());
551  assert(MBBI->getOpcode() == PPC::BLR &&
552         "Can only insert epilog into returning blocks");
553
554  // Get alignment info so we know how to restore r1
555  const MachineFrameInfo *MFI = MF.getFrameInfo();
556  unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
557
558  // Get the number of bytes allocated from the FrameInfo.
559  unsigned NumBytes = MFI->getStackSize();
560  unsigned GPRSize = 4;
561
562  if (NumBytes != 0) {
563    // If this function has a frame pointer, load the saved stack pointer from
564    // its stack slot.
565    if (hasFP(MF)) {
566      BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
567          .addSImm(GPRSize).addReg(PPC::R31);
568    }
569
570    // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
571    // on entry to the function.  Add this offset back now.
572    if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
573      BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
574          .addReg(PPC::R1).addSImm(NumBytes);
575    } else {
576      BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
577    }
578  }
579}
580
581unsigned PPCRegisterInfo::getRARegister() const {
582  return PPC::LR;
583}
584
585unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
586  return hasFP(MF) ? PPC::R31 : PPC::R1;
587}
588
589void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
590                                                                         const {
591  // Initial state is the frame pointer is R1.
592  MachineLocation Dst(MachineLocation::VirtualFP);
593  MachineLocation Src(PPC::R1, 0);
594  Moves.push_back(new MachineMove(0, Dst, Src));
595}
596
597#include "PPCGenRegisterInfo.inc"
598
599