CodeGenTarget.cpp revision 764811f1452808ff8a6d84f4ec2637355356e22e
1//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class wrap target description classes used by the various code 11// generation TableGen backends. This makes it easier to access the data and 12// provides a single place that needs to check it for validity. All of these 13// classes throw exceptions on error conditions. 14// 15//===----------------------------------------------------------------------===// 16 17#include "CodeGenTarget.h" 18#include "CodeGenIntrinsics.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/Support/CommandLine.h" 22#include <set> 23#include <algorithm> 24using namespace llvm; 25 26static cl::opt<unsigned> 27AsmWriterNum("asmwriternum", cl::init(0), 28 cl::desc("Make -gen-asm-writer emit assembly writer #N")); 29 30/// getValueType - Return the MCV::ValueType that the specified TableGen record 31/// corresponds to. 32MVT::ValueType llvm::getValueType(Record *Rec, const CodeGenTarget *CGT) { 33 return (MVT::ValueType)Rec->getValueAsInt("Value"); 34} 35 36std::string llvm::getName(MVT::ValueType T) { 37 switch (T) { 38 case MVT::Other: return "UNKNOWN"; 39 case MVT::i1: return "i1"; 40 case MVT::i8: return "i8"; 41 case MVT::i16: return "i16"; 42 case MVT::i32: return "i32"; 43 case MVT::i64: return "i64"; 44 case MVT::i128: return "i128"; 45 case MVT::f32: return "f32"; 46 case MVT::f64: return "f64"; 47 case MVT::f80: return "f80"; 48 case MVT::f128: return "f128"; 49 case MVT::Flag: return "Flag"; 50 case MVT::isVoid:return "void"; 51 case MVT::v8i8: return "v8i8"; 52 case MVT::v4i16: return "v4i16"; 53 case MVT::v2i32: return "v2i32"; 54 case MVT::v16i8: return "v16i8"; 55 case MVT::v8i16: return "v8i16"; 56 case MVT::v4i32: return "v4i32"; 57 case MVT::v2i64: return "v2i64"; 58 case MVT::v2f32: return "v2f32"; 59 case MVT::v4f32: return "v4f32"; 60 case MVT::v2f64: return "v2f64"; 61 case MVT::iPTR: return "TLI.getPointerTy()"; 62 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 63 } 64} 65 66std::string llvm::getEnumName(MVT::ValueType T) { 67 switch (T) { 68 case MVT::Other: return "MVT::Other"; 69 case MVT::i1: return "MVT::i1"; 70 case MVT::i8: return "MVT::i8"; 71 case MVT::i16: return "MVT::i16"; 72 case MVT::i32: return "MVT::i32"; 73 case MVT::i64: return "MVT::i64"; 74 case MVT::i128: return "MVT::i128"; 75 case MVT::f32: return "MVT::f32"; 76 case MVT::f64: return "MVT::f64"; 77 case MVT::f80: return "MVT::f80"; 78 case MVT::f128: return "MVT::f128"; 79 case MVT::Flag: return "MVT::Flag"; 80 case MVT::isVoid:return "MVT::isVoid"; 81 case MVT::v8i8: return "MVT::v8i8"; 82 case MVT::v4i16: return "MVT::v4i16"; 83 case MVT::v2i32: return "MVT::v2i32"; 84 case MVT::v16i8: return "MVT::v16i8"; 85 case MVT::v8i16: return "MVT::v8i16"; 86 case MVT::v4i32: return "MVT::v4i32"; 87 case MVT::v2i64: return "MVT::v2i64"; 88 case MVT::v2f32: return "MVT::v2f32"; 89 case MVT::v4f32: return "MVT::v4f32"; 90 case MVT::v2f64: return "MVT::v2f64"; 91 case MVT::iPTR: return "TLI.getPointerTy()"; 92 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 93 } 94} 95 96 97std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) { 98 return OS << getName(T); 99} 100 101 102/// getTarget - Return the current instance of the Target class. 103/// 104CodeGenTarget::CodeGenTarget() { 105 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 106 if (Targets.size() == 0) 107 throw std::string("ERROR: No 'Target' subclasses defined!"); 108 if (Targets.size() != 1) 109 throw std::string("ERROR: Multiple subclasses of Target defined!"); 110 TargetRec = Targets[0]; 111} 112 113 114const std::string &CodeGenTarget::getName() const { 115 return TargetRec->getName(); 116} 117 118Record *CodeGenTarget::getInstructionSet() const { 119 return TargetRec->getValueAsDef("InstructionSet"); 120} 121 122/// getAsmWriter - Return the AssemblyWriter definition for this target. 123/// 124Record *CodeGenTarget::getAsmWriter() const { 125 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 126 if (AsmWriterNum >= LI.size()) 127 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; 128 return LI[AsmWriterNum]; 129} 130 131void CodeGenTarget::ReadRegisters() const { 132 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 133 if (Regs.empty()) 134 throw std::string("No 'Register' subclasses defined!"); 135 136 Registers.reserve(Regs.size()); 137 Registers.assign(Regs.begin(), Regs.end()); 138} 139 140CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { 141 DeclaredSpillSize = R->getValueAsInt("SpillSize"); 142 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); 143} 144 145const std::string &CodeGenRegister::getName() const { 146 return TheDef->getName(); 147} 148 149void CodeGenTarget::ReadRegisterClasses() const { 150 std::vector<Record*> RegClasses = 151 Records.getAllDerivedDefinitions("RegisterClass"); 152 if (RegClasses.empty()) 153 throw std::string("No 'RegisterClass' subclasses defined!"); 154 155 RegisterClasses.reserve(RegClasses.size()); 156 RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); 157} 158 159std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const { 160 std::vector<unsigned char> Result; 161 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 162 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 163 const CodeGenRegisterClass &RC = RegisterClasses[i]; 164 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { 165 if (R == RC.Elements[ei]) { 166 const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes(); 167 for (unsigned i = 0, e = InVTs.size(); i != e; ++i) 168 Result.push_back(InVTs[i]); 169 } 170 } 171 } 172 return Result; 173} 174 175 176CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { 177 // Rename anonymous register classes. 178 if (R->getName().size() > 9 && R->getName()[9] == '.') { 179 static unsigned AnonCounter = 0; 180 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 181 } 182 183 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 184 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 185 Record *Type = TypeList[i]; 186 if (!Type->isSubClassOf("ValueType")) 187 throw "RegTypes list member '" + Type->getName() + 188 "' does not derive from the ValueType class!"; 189 VTs.push_back(getValueType(Type)); 190 } 191 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 192 193 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); 194 for (unsigned i = 0, e = RegList.size(); i != e; ++i) { 195 Record *Reg = RegList[i]; 196 if (!Reg->isSubClassOf("Register")) 197 throw "Register Class member '" + Reg->getName() + 198 "' does not derive from the Register class!"; 199 Elements.push_back(Reg); 200 } 201 202 // Allow targets to override the size in bits of the RegisterClass. 203 unsigned Size = R->getValueAsInt("Size"); 204 205 Namespace = R->getValueAsString("Namespace"); 206 SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]); 207 SpillAlignment = R->getValueAsInt("Alignment"); 208 MethodBodies = R->getValueAsCode("MethodBodies"); 209 MethodProtos = R->getValueAsCode("MethodProtos"); 210} 211 212const std::string &CodeGenRegisterClass::getName() const { 213 return TheDef->getName(); 214} 215 216void CodeGenTarget::ReadLegalValueTypes() const { 217 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 218 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 219 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) 220 LegalValueTypes.push_back(RCs[i].VTs[ri]); 221 222 // Remove duplicates. 223 std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); 224 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 225 LegalValueTypes.end()), 226 LegalValueTypes.end()); 227} 228 229 230void CodeGenTarget::ReadInstructions() const { 231 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 232 if (Insts.size() <= 2) 233 throw std::string("No 'Instruction' subclasses defined!"); 234 235 // Parse the instructions defined in the .td file. 236 std::string InstFormatName = 237 getAsmWriter()->getValueAsString("InstFormatName"); 238 239 for (unsigned i = 0, e = Insts.size(); i != e; ++i) { 240 std::string AsmStr = Insts[i]->getValueAsString(InstFormatName); 241 Instructions.insert(std::make_pair(Insts[i]->getName(), 242 CodeGenInstruction(Insts[i], AsmStr))); 243 } 244} 245 246/// getInstructionsByEnumValue - Return all of the instructions defined by the 247/// target, ordered by their enum value. 248void CodeGenTarget:: 249getInstructionsByEnumValue(std::vector<const CodeGenInstruction*> 250 &NumberedInstructions) { 251 std::map<std::string, CodeGenInstruction>::const_iterator I; 252 I = getInstructions().find("PHI"); 253 if (I == Instructions.end()) throw "Could not find 'PHI' instruction!"; 254 const CodeGenInstruction *PHI = &I->second; 255 256 I = getInstructions().find("INLINEASM"); 257 if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!"; 258 const CodeGenInstruction *INLINEASM = &I->second; 259 260 // Print out the rest of the instructions now. 261 NumberedInstructions.push_back(PHI); 262 NumberedInstructions.push_back(INLINEASM); 263 for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II) 264 if (&II->second != PHI &&&II->second != INLINEASM) 265 NumberedInstructions.push_back(&II->second); 266} 267 268 269/// isLittleEndianEncoding - Return whether this target encodes its instruction 270/// in little-endian format, i.e. bits laid out in the order [0..n] 271/// 272bool CodeGenTarget::isLittleEndianEncoding() const { 273 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 274} 275 276CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) 277 : TheDef(R), AsmString(AsmStr) { 278 Name = R->getValueAsString("Name"); 279 Namespace = R->getValueAsString("Namespace"); 280 281 isReturn = R->getValueAsBit("isReturn"); 282 isBranch = R->getValueAsBit("isBranch"); 283 isBarrier = R->getValueAsBit("isBarrier"); 284 isCall = R->getValueAsBit("isCall"); 285 isLoad = R->getValueAsBit("isLoad"); 286 isStore = R->getValueAsBit("isStore"); 287 isTwoAddress = R->getValueAsBit("isTwoAddress"); 288 isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress"); 289 isCommutable = R->getValueAsBit("isCommutable"); 290 isTerminator = R->getValueAsBit("isTerminator"); 291 hasDelaySlot = R->getValueAsBit("hasDelaySlot"); 292 usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); 293 hasCtrlDep = R->getValueAsBit("hasCtrlDep"); 294 noResults = R->getValueAsBit("noResults"); 295 hasVariableNumberOfOperands = false; 296 297 DagInit *DI; 298 try { 299 DI = R->getValueAsDag("OperandList"); 300 } catch (...) { 301 // Error getting operand list, just ignore it (sparcv9). 302 AsmString.clear(); 303 OperandList.clear(); 304 return; 305 } 306 307 unsigned MIOperandNo = 0; 308 std::set<std::string> OperandNames; 309 for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) { 310 DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i)); 311 if (!Arg) 312 throw "Illegal operand for the '" + R->getName() + "' instruction!"; 313 314 Record *Rec = Arg->getDef(); 315 std::string PrintMethod = "printOperand"; 316 unsigned NumOps = 1; 317 DagInit *MIOpInfo = 0; 318 if (Rec->isSubClassOf("Operand")) { 319 PrintMethod = Rec->getValueAsString("PrintMethod"); 320 NumOps = Rec->getValueAsInt("NumMIOperands"); 321 MIOpInfo = Rec->getValueAsDag("MIOperandInfo"); 322 } else if (Rec->getName() == "variable_ops") { 323 hasVariableNumberOfOperands = true; 324 continue; 325 } else if (!Rec->isSubClassOf("RegisterClass")) 326 throw "Unknown operand class '" + Rec->getName() + 327 "' in instruction '" + R->getName() + "' instruction!"; 328 329 // Check that the operand has a name and that it's unique. 330 if (DI->getArgName(i).empty()) 331 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) + 332 " has no name!"; 333 if (!OperandNames.insert(DI->getArgName(i)).second) 334 throw "In instruction '" + R->getName() + "', operand #" + utostr(i) + 335 " has the same name as a previous operand!"; 336 337 OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod, 338 MIOperandNo, NumOps, MIOpInfo)); 339 MIOperandNo += NumOps; 340 } 341} 342 343 344 345/// getOperandNamed - Return the index of the operand with the specified 346/// non-empty name. If the instruction does not have an operand with the 347/// specified name, throw an exception. 348/// 349unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const { 350 assert(!Name.empty() && "Cannot search for operand with no name!"); 351 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) 352 if (OperandList[i].Name == Name) return i; 353 throw "Instruction '" + TheDef->getName() + 354 "' does not have an operand named '$" + Name + "'!"; 355} 356 357//===----------------------------------------------------------------------===// 358// ComplexPattern implementation 359// 360ComplexPattern::ComplexPattern(Record *R) { 361 Ty = ::getValueType(R->getValueAsDef("Ty")); 362 NumOperands = R->getValueAsInt("NumOperands"); 363 SelectFunc = R->getValueAsString("SelectFunc"); 364 RootNodes = R->getValueAsListOfDefs("RootNodes"); 365} 366 367//===----------------------------------------------------------------------===// 368// CodeGenIntrinsic Implementation 369//===----------------------------------------------------------------------===// 370 371std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) { 372 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic"); 373 374 std::vector<CodeGenIntrinsic> Result; 375 376 // If we are in the context of a target .td file, get the target info so that 377 // we can decode the current intptr_t. 378 CodeGenTarget *CGT = 0; 379 if (Records.getClass("Target") && 380 Records.getAllDerivedDefinitions("Target").size() == 1) 381 CGT = new CodeGenTarget(); 382 383 for (unsigned i = 0, e = I.size(); i != e; ++i) 384 Result.push_back(CodeGenIntrinsic(I[i], CGT)); 385 delete CGT; 386 return Result; 387} 388 389CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget *CGT) { 390 TheDef = R; 391 std::string DefName = R->getName(); 392 ModRef = WriteMem; 393 394 if (DefName.size() <= 4 || 395 std::string(DefName.begin(), DefName.begin()+4) != "int_") 396 throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; 397 EnumName = std::string(DefName.begin()+4, DefName.end()); 398 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 399 GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); 400 TargetPrefix = R->getValueAsString("TargetPrefix"); 401 Name = R->getValueAsString("LLVMName"); 402 if (Name == "") { 403 // If an explicit name isn't specified, derive one from the DefName. 404 Name = "llvm."; 405 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 406 if (EnumName[i] == '_') 407 Name += '.'; 408 else 409 Name += EnumName[i]; 410 } else { 411 // Verify it starts with "llvm.". 412 if (Name.size() <= 5 || 413 std::string(Name.begin(), Name.begin()+5) != "llvm.") 414 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; 415 } 416 417 // If TargetPrefix is specified, make sure that Name starts with 418 // "llvm.<targetprefix>.". 419 if (!TargetPrefix.empty()) { 420 if (Name.size() < 6+TargetPrefix.size() || 421 std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size()) 422 != (TargetPrefix+".")) 423 throw "Intrinsic '" + DefName + "' does not start with 'llvm." + 424 TargetPrefix + ".'!"; 425 } 426 427 // Parse the list of argument types. 428 ListInit *TypeList = R->getValueAsListInit("Types"); 429 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 430 DefInit *DI = dynamic_cast<DefInit*>(TypeList->getElement(i)); 431 assert(DI && "Invalid list type!"); 432 Record *TyEl = DI->getDef(); 433 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 434 ArgTypes.push_back(TyEl->getValueAsString("TypeVal")); 435 436 if (CGT) 437 ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), CGT)); 438 ArgTypeDefs.push_back(TyEl); 439 } 440 if (ArgTypes.size() == 0) 441 throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!"; 442 443 // Parse the intrinsic properties. 444 ListInit *PropList = R->getValueAsListInit("Properties"); 445 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { 446 DefInit *DI = dynamic_cast<DefInit*>(PropList->getElement(i)); 447 assert(DI && "Invalid list type!"); 448 Record *Property = DI->getDef(); 449 assert(Property->isSubClassOf("IntrinsicProperty") && 450 "Expected a property!"); 451 452 if (Property->getName() == "IntrNoMem") 453 ModRef = NoMem; 454 else if (Property->getName() == "IntrReadArgMem") 455 ModRef = ReadArgMem; 456 else if (Property->getName() == "IntrReadMem") 457 ModRef = ReadMem; 458 else if (Property->getName() == "IntrWriteArgMem") 459 ModRef = WriteArgMem; 460 else if (Property->getName() == "IntrWriteMem") 461 ModRef = WriteMem; 462 else 463 assert(0 && "Unknown property!"); 464 } 465} 466