CodeGenTarget.cpp revision b0e103d46bf8799ac5523157a6ed4a78d1751a89 
1//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class wrap target description classes used by the various code
11// generation TableGen backends.  This makes it easier to access the data and
12// provides a single place that needs to check it for validity.  All of these
13// classes throw exceptions on error conditions.
14//
15//===----------------------------------------------------------------------===//
16
17#include "CodeGenTarget.h"
18#include "Record.h"
19#include "llvm/ADT/StringExtras.h"
20#include "llvm/Support/CommandLine.h"
21#include <set>
22#include <algorithm>
23using namespace llvm;
24
25static cl::opt<unsigned>
26AsmWriterNum("asmwriternum", cl::init(0),
27             cl::desc("Make -gen-asm-writer emit assembly writer #N"));
28
29/// getValueType - Return the MCV::ValueType that the specified TableGen record
30/// corresponds to.
31MVT::ValueType llvm::getValueType(Record *Rec) {
32  return (MVT::ValueType)Rec->getValueAsInt("Value");
33}
34
35std::string llvm::getName(MVT::ValueType T) {
36  switch (T) {
37  case MVT::Other: return "UNKNOWN";
38  case MVT::i1:    return "i1";
39  case MVT::i8:    return "i8";
40  case MVT::i16:   return "i16";
41  case MVT::i32:   return "i32";
42  case MVT::i64:   return "i64";
43  case MVT::i128:  return "i128";
44  case MVT::f32:   return "f32";
45  case MVT::f64:   return "f64";
46  case MVT::f80:   return "f80";
47  case MVT::f128:  return "f128";
48  case MVT::isVoid:return "void";
49  default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
50  }
51}
52
53std::string llvm::getEnumName(MVT::ValueType T) {
54  switch (T) {
55  case MVT::Other: return "Other";
56  case MVT::i1:    return "i1";
57  case MVT::i8:    return "i8";
58  case MVT::i16:   return "i16";
59  case MVT::i32:   return "i32";
60  case MVT::i64:   return "i64";
61  case MVT::i128:  return "i128";
62  case MVT::f32:   return "f32";
63  case MVT::f64:   return "f64";
64  case MVT::f80:   return "f80";
65  case MVT::f128:  return "f128";
66  case MVT::isVoid:return "isVoid";
67  default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
68  }
69}
70
71
72std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
73  return OS << getName(T);
74}
75
76
77/// getTarget - Return the current instance of the Target class.
78///
79CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) {
80  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
81  if (Targets.size() == 0)
82    throw std::string("ERROR: No 'Target' subclasses defined!");
83  if (Targets.size() != 1)
84    throw std::string("ERROR: Multiple subclasses of Target defined!");
85  TargetRec = Targets[0];
86
87  // Read in all of the CalleeSavedRegisters.
88  CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters");
89  PointerType = getValueType(TargetRec->getValueAsDef("PointerType"));
90}
91
92
93const std::string &CodeGenTarget::getName() const {
94  return TargetRec->getName();
95}
96
97Record *CodeGenTarget::getInstructionSet() const {
98  return TargetRec->getValueAsDef("InstructionSet");
99}
100
101/// getAsmWriter - Return the AssemblyWriter definition for this target.
102///
103Record *CodeGenTarget::getAsmWriter() const {
104  std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
105  if (AsmWriterNum >= LI.size())
106    throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
107  return LI[AsmWriterNum];
108}
109
110void CodeGenTarget::ReadRegisters() const {
111  std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
112  if (Regs.empty())
113    throw std::string("No 'Register' subclasses defined!");
114
115  Registers.reserve(Regs.size());
116  Registers.assign(Regs.begin(), Regs.end());
117}
118
119CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
120  DeclaredSpillSize = R->getValueAsInt("SpillSize");
121  DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
122}
123
124const std::string &CodeGenRegister::getName() const {
125  return TheDef->getName();
126}
127
128void CodeGenTarget::ReadRegisterClasses() const {
129  std::vector<Record*> RegClasses =
130    Records.getAllDerivedDefinitions("RegisterClass");
131  if (RegClasses.empty())
132    throw std::string("No 'RegisterClass' subclasses defined!");
133
134  RegisterClasses.reserve(RegClasses.size());
135  RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
136}
137
138CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
139  // Rename anonymous register classes.
140  if (R->getName().size() > 9 && R->getName()[9] == '.') {
141    static unsigned AnonCounter = 0;
142    R->setName("AnonRegClass_"+utostr(AnonCounter++));
143  }
144
145  Namespace = R->getValueAsString("Namespace");
146  SpillSize = R->getValueAsInt("Size");
147  SpillAlignment = R->getValueAsInt("Alignment");
148  VT = getValueType(R->getValueAsDef("RegType"));
149
150  MethodBodies = R->getValueAsCode("MethodBodies");
151  MethodProtos = R->getValueAsCode("MethodProtos");
152
153  std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
154  for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
155    Record *Reg = RegList[i];
156    if (!Reg->isSubClassOf("Register"))
157      throw "Register Class member '" + Reg->getName() +
158            "' does not derive from the Register class!";
159    Elements.push_back(Reg);
160  }
161}
162
163const std::string &CodeGenRegisterClass::getName() const {
164  return TheDef->getName();
165}
166
167void CodeGenTarget::ReadLegalValueTypes() const {
168  const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
169  for (unsigned i = 0, e = RCs.size(); i != e; ++i)
170    LegalValueTypes.push_back(RCs[i].VT);
171
172  // Remove duplicates.
173  std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
174  LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
175                                    LegalValueTypes.end()),
176                        LegalValueTypes.end());
177}
178
179
180void CodeGenTarget::ReadInstructions() const {
181  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
182
183  if (Insts.empty())
184    throw std::string("No 'Instruction' subclasses defined!");
185
186  std::string InstFormatName =
187    getAsmWriter()->getValueAsString("InstFormatName");
188
189  for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
190    std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
191    Instructions.insert(std::make_pair(Insts[i]->getName(),
192                                       CodeGenInstruction(Insts[i], AsmStr)));
193  }
194}
195
196/// getPHIInstruction - Return the designated PHI instruction.
197///
198const CodeGenInstruction &CodeGenTarget::getPHIInstruction() const {
199  Record *PHI = getInstructionSet()->getValueAsDef("PHIInst");
200  std::map<std::string, CodeGenInstruction>::const_iterator I =
201    getInstructions().find(PHI->getName());
202  if (I == Instructions.end())
203    throw "Could not find PHI instruction named '" + PHI->getName() + "'!";
204  return I->second;
205}
206
207/// getInstructionsByEnumValue - Return all of the instructions defined by the
208/// target, ordered by their enum value.
209void CodeGenTarget::
210getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
211                                                 &NumberedInstructions) {
212
213  // Print out the rest of the instructions now.
214  unsigned i = 0;
215  const CodeGenInstruction *PHI = &getPHIInstruction();
216  NumberedInstructions.push_back(PHI);
217  for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
218    if (&II->second != PHI)
219      NumberedInstructions.push_back(&II->second);
220}
221
222
223/// isLittleEndianEncoding - Return whether this target encodes its instruction
224/// in little-endian format, i.e. bits laid out in the order [0..n]
225///
226bool CodeGenTarget::isLittleEndianEncoding() const {
227  return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
228}
229
230CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
231  : TheDef(R), AsmString(AsmStr) {
232  Name      = R->getValueAsString("Name");
233  Namespace = R->getValueAsString("Namespace");
234
235  isReturn     = R->getValueAsBit("isReturn");
236  isBranch     = R->getValueAsBit("isBranch");
237  isBarrier    = R->getValueAsBit("isBarrier");
238  isCall       = R->getValueAsBit("isCall");
239  isLoad       = R->getValueAsBit("isLoad");
240  isStore      = R->getValueAsBit("isStore");
241  isTwoAddress = R->getValueAsBit("isTwoAddress");
242  isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
243  isCommutable = R->getValueAsBit("isCommutable");
244  isTerminator = R->getValueAsBit("isTerminator");
245  hasDelaySlot = R->getValueAsBit("hasDelaySlot");
246  usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
247  hasVariableNumberOfOperands = false;
248
249  DagInit *DI;
250  try {
251    DI = R->getValueAsDag("OperandList");
252  } catch (...) {
253    // Error getting operand list, just ignore it (sparcv9).
254    AsmString.clear();
255    OperandList.clear();
256    return;
257  }
258
259  unsigned MIOperandNo = 0;
260  std::set<std::string> OperandNames;
261  for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
262    DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
263    if (!Arg)
264      throw "Illegal operand for the '" + R->getName() + "' instruction!";
265
266    Record *Rec = Arg->getDef();
267    MVT::ValueType Ty;
268    std::string PrintMethod = "printOperand";
269    unsigned NumOps = 1;
270    if (Rec->isSubClassOf("RegisterClass")) {
271      Ty = getValueType(Rec->getValueAsDef("RegType"));
272    } else if (Rec->isSubClassOf("Operand")) {
273      Ty = getValueType(Rec->getValueAsDef("Type"));
274      PrintMethod = Rec->getValueAsString("PrintMethod");
275      NumOps = Rec->getValueAsInt("NumMIOperands");
276    } else if (Rec->getName() == "variable_ops") {
277      hasVariableNumberOfOperands = true;
278      continue;
279    } else
280      throw "Unknown operand class '" + Rec->getName() +
281            "' in instruction '" + R->getName() + "' instruction!";
282
283    // Check that the operand has a name and that it's unique.
284    if (DI->getArgName(i).empty())
285      throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
286        " has no name!";
287    if (!OperandNames.insert(DI->getArgName(i)).second)
288      throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
289        " has the same name as a previous operand!";
290
291    OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
292                                      PrintMethod, MIOperandNo, NumOps));
293    MIOperandNo += NumOps;
294  }
295}
296
297
298
299/// getOperandNamed - Return the index of the operand with the specified
300/// non-empty name.  If the instruction does not have an operand with the
301/// specified name, throw an exception.
302///
303unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
304  assert(!Name.empty() && "Cannot search for operand with no name!");
305  for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
306    if (OperandList[i].Name == Name) return i;
307  throw "Instruction '" + TheDef->getName() +
308        "' does not have an operand named '$" + Name + "'!";
309}
310