CodeGenTarget.cpp revision f1b4eafbfec976f939ec0ea3e8acf91cef5363e3
1//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class wraps target description classes used by the various code 11// generation TableGen backends. This makes it easier to access the data and 12// provides a single place that needs to check it for validity. All of these 13// classes throw exceptions on error conditions. 14// 15//===----------------------------------------------------------------------===// 16 17#include "CodeGenTarget.h" 18#include "CodeGenIntrinsics.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/Support/CommandLine.h" 23#include <algorithm> 24using namespace llvm; 25 26static cl::opt<unsigned> 27AsmParserNum("asmparsernum", cl::init(0), 28 cl::desc("Make -gen-asm-parser emit assembly parser #N")); 29 30static cl::opt<unsigned> 31AsmWriterNum("asmwriternum", cl::init(0), 32 cl::desc("Make -gen-asm-writer emit assembly writer #N")); 33 34/// getValueType - Return the MVT::SimpleValueType that the specified TableGen 35/// record corresponds to. 36MVT::SimpleValueType llvm::getValueType(Record *Rec) { 37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 38} 39 40std::string llvm::getName(MVT::SimpleValueType T) { 41 switch (T) { 42 case MVT::Other: return "UNKNOWN"; 43 case MVT::iPTR: return "TLI.getPointerTy()"; 44 case MVT::iPTRAny: return "TLI.getPointerTy()"; 45 default: return getEnumName(T); 46 } 47} 48 49std::string llvm::getEnumName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "MVT::Other"; 52 case MVT::i1: return "MVT::i1"; 53 case MVT::i8: return "MVT::i8"; 54 case MVT::i16: return "MVT::i16"; 55 case MVT::i32: return "MVT::i32"; 56 case MVT::i64: return "MVT::i64"; 57 case MVT::i128: return "MVT::i128"; 58 case MVT::iAny: return "MVT::iAny"; 59 case MVT::fAny: return "MVT::fAny"; 60 case MVT::vAny: return "MVT::vAny"; 61 case MVT::f32: return "MVT::f32"; 62 case MVT::f64: return "MVT::f64"; 63 case MVT::f80: return "MVT::f80"; 64 case MVT::f128: return "MVT::f128"; 65 case MVT::ppcf128: return "MVT::ppcf128"; 66 case MVT::x86mmx: return "MVT::x86mmx"; 67 case MVT::Glue: return "MVT::Glue"; 68 case MVT::isVoid: return "MVT::isVoid"; 69 case MVT::v2i8: return "MVT::v2i8"; 70 case MVT::v4i8: return "MVT::v4i8"; 71 case MVT::v8i8: return "MVT::v8i8"; 72 case MVT::v16i8: return "MVT::v16i8"; 73 case MVT::v32i8: return "MVT::v32i8"; 74 case MVT::v2i16: return "MVT::v2i16"; 75 case MVT::v4i16: return "MVT::v4i16"; 76 case MVT::v8i16: return "MVT::v8i16"; 77 case MVT::v16i16: return "MVT::v16i16"; 78 case MVT::v2i32: return "MVT::v2i32"; 79 case MVT::v4i32: return "MVT::v4i32"; 80 case MVT::v8i32: return "MVT::v8i32"; 81 case MVT::v1i64: return "MVT::v1i64"; 82 case MVT::v2i64: return "MVT::v2i64"; 83 case MVT::v4i64: return "MVT::v4i64"; 84 case MVT::v8i64: return "MVT::v8i64"; 85 case MVT::v2f32: return "MVT::v2f32"; 86 case MVT::v4f32: return "MVT::v4f32"; 87 case MVT::v8f32: return "MVT::v8f32"; 88 case MVT::v2f64: return "MVT::v2f64"; 89 case MVT::v4f64: return "MVT::v4f64"; 90 case MVT::Metadata: return "MVT::Metadata"; 91 case MVT::iPTR: return "MVT::iPTR"; 92 case MVT::iPTRAny: return "MVT::iPTRAny"; 93 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 94 } 95} 96 97/// getQualifiedName - Return the name of the specified record, with a 98/// namespace qualifier if the record contains one. 99/// 100std::string llvm::getQualifiedName(const Record *R) { 101 std::string Namespace = R->getValueAsString("Namespace"); 102 if (Namespace.empty()) return R->getName(); 103 return Namespace + "::" + R->getName(); 104} 105 106 107 108 109/// getTarget - Return the current instance of the Target class. 110/// 111CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) { 112 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 113 if (Targets.size() == 0) 114 throw std::string("ERROR: No 'Target' subclasses defined!"); 115 if (Targets.size() != 1) 116 throw std::string("ERROR: Multiple subclasses of Target defined!"); 117 TargetRec = Targets[0]; 118} 119 120 121const std::string &CodeGenTarget::getName() const { 122 return TargetRec->getName(); 123} 124 125std::string CodeGenTarget::getInstNamespace() const { 126 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) { 127 // Make sure not to pick up "TargetOpcode" by accidentally getting 128 // the namespace off the PHI instruction or something. 129 if ((*i)->Namespace != "TargetOpcode") 130 return (*i)->Namespace; 131 } 132 133 return ""; 134} 135 136Record *CodeGenTarget::getInstructionSet() const { 137 return TargetRec->getValueAsDef("InstructionSet"); 138} 139 140 141/// getAsmParser - Return the AssemblyParser definition for this target. 142/// 143Record *CodeGenTarget::getAsmParser() const { 144 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 145 if (AsmParserNum >= LI.size()) 146 throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!"; 147 return LI[AsmParserNum]; 148} 149 150/// getAsmWriter - Return the AssemblyWriter definition for this target. 151/// 152Record *CodeGenTarget::getAsmWriter() const { 153 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 154 if (AsmWriterNum >= LI.size()) 155 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; 156 return LI[AsmWriterNum]; 157} 158 159void CodeGenTarget::ReadRegisters() const { 160 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 161 if (Regs.empty()) 162 throw std::string("No 'Register' subclasses defined!"); 163 std::sort(Regs.begin(), Regs.end(), LessRecord()); 164 165 Registers.reserve(Regs.size()); 166 Registers.assign(Regs.begin(), Regs.end()); 167} 168 169CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { 170 DeclaredSpillSize = R->getValueAsInt("SpillSize"); 171 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); 172} 173 174const std::string &CodeGenRegister::getName() const { 175 return TheDef->getName(); 176} 177 178void CodeGenTarget::ReadSubRegIndices() const { 179 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); 180 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); 181} 182 183void CodeGenTarget::ReadRegisterClasses() const { 184 std::vector<Record*> RegClasses = 185 Records.getAllDerivedDefinitions("RegisterClass"); 186 if (RegClasses.empty()) 187 throw std::string("No 'RegisterClass' subclasses defined!"); 188 189 RegisterClasses.reserve(RegClasses.size()); 190 RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); 191} 192 193/// getRegisterByName - If there is a register with the specific AsmName, 194/// return it. 195const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 196 const std::vector<CodeGenRegister> &Regs = getRegisters(); 197 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 198 const CodeGenRegister &Reg = Regs[i]; 199 if (Reg.TheDef->getValueAsString("AsmName") == Name) 200 return &Reg; 201 } 202 203 return 0; 204} 205 206std::vector<MVT::SimpleValueType> CodeGenTarget:: 207getRegisterVTs(Record *R) const { 208 std::vector<MVT::SimpleValueType> Result; 209 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 210 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 211 const CodeGenRegisterClass &RC = RegisterClasses[i]; 212 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { 213 if (R == RC.Elements[ei]) { 214 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); 215 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 216 } 217 } 218 } 219 220 // Remove duplicates. 221 array_pod_sort(Result.begin(), Result.end()); 222 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 223 return Result; 224} 225 226 227CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { 228 // Rename anonymous register classes. 229 if (R->getName().size() > 9 && R->getName()[9] == '.') { 230 static unsigned AnonCounter = 0; 231 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 232 } 233 234 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 235 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 236 Record *Type = TypeList[i]; 237 if (!Type->isSubClassOf("ValueType")) 238 throw "RegTypes list member '" + Type->getName() + 239 "' does not derive from the ValueType class!"; 240 VTs.push_back(getValueType(Type)); 241 } 242 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 243 244 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); 245 for (unsigned i = 0, e = RegList.size(); i != e; ++i) { 246 Record *Reg = RegList[i]; 247 if (!Reg->isSubClassOf("Register")) 248 throw "Register Class member '" + Reg->getName() + 249 "' does not derive from the Register class!"; 250 Elements.push_back(Reg); 251 } 252 253 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags. 254 ListInit *SRC = R->getValueAsListInit("SubRegClasses"); 255 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { 256 DagInit *DAG = dynamic_cast<DagInit*>(*i); 257 if (!DAG) throw "SubRegClasses must contain DAGs"; 258 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator()); 259 Record *RCRec; 260 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) 261 throw "Operator '" + DAG->getOperator()->getAsString() + 262 "' in SubRegClasses is not a RegisterClass"; 263 // Iterate over args, all SubRegIndex instances. 264 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); 265 ai != ae; ++ai) { 266 DefInit *Idx = dynamic_cast<DefInit*>(*ai); 267 Record *IdxRec; 268 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) 269 throw "Argument '" + (*ai)->getAsString() + 270 "' in SubRegClasses is not a SubRegIndex"; 271 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) 272 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; 273 } 274 } 275 276 // Allow targets to override the size in bits of the RegisterClass. 277 unsigned Size = R->getValueAsInt("Size"); 278 279 Namespace = R->getValueAsString("Namespace"); 280 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); 281 SpillAlignment = R->getValueAsInt("Alignment"); 282 CopyCost = R->getValueAsInt("CopyCost"); 283 MethodBodies = R->getValueAsCode("MethodBodies"); 284 MethodProtos = R->getValueAsCode("MethodProtos"); 285} 286 287const std::string &CodeGenRegisterClass::getName() const { 288 return TheDef->getName(); 289} 290 291void CodeGenTarget::ReadLegalValueTypes() const { 292 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 293 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 294 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) 295 LegalValueTypes.push_back(RCs[i].VTs[ri]); 296 297 // Remove duplicates. 298 std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); 299 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 300 LegalValueTypes.end()), 301 LegalValueTypes.end()); 302} 303 304 305void CodeGenTarget::ReadInstructions() const { 306 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 307 if (Insts.size() <= 2) 308 throw std::string("No 'Instruction' subclasses defined!"); 309 310 // Parse the instructions defined in the .td file. 311 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 312 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i]); 313} 314 315static const CodeGenInstruction * 316GetInstByName(const char *Name, 317 const DenseMap<const Record*, CodeGenInstruction*> &Insts, 318 RecordKeeper &Records) { 319 const Record *Rec = Records.getDef(Name); 320 321 DenseMap<const Record*, CodeGenInstruction*>::const_iterator 322 I = Insts.find(Rec); 323 if (Rec == 0 || I == Insts.end()) 324 throw std::string("Could not find '") + Name + "' instruction!"; 325 return I->second; 326} 327 328namespace { 329/// SortInstByName - Sorting predicate to sort instructions by name. 330/// 331struct SortInstByName { 332 bool operator()(const CodeGenInstruction *Rec1, 333 const CodeGenInstruction *Rec2) const { 334 return Rec1->TheDef->getName() < Rec2->TheDef->getName(); 335 } 336}; 337} 338 339/// getInstructionsByEnumValue - Return all of the instructions defined by the 340/// target, ordered by their enum value. 341void CodeGenTarget::ComputeInstrsByEnum() const { 342 // The ordering here must match the ordering in TargetOpcodes.h. 343 const char *const FixedInstrs[] = { 344 "PHI", 345 "INLINEASM", 346 "PROLOG_LABEL", 347 "EH_LABEL", 348 "GC_LABEL", 349 "KILL", 350 "EXTRACT_SUBREG", 351 "INSERT_SUBREG", 352 "IMPLICIT_DEF", 353 "SUBREG_TO_REG", 354 "COPY_TO_REGCLASS", 355 "DBG_VALUE", 356 "REG_SEQUENCE", 357 "COPY", 358 0 359 }; 360 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions(); 361 for (const char *const *p = FixedInstrs; *p; ++p) { 362 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 363 assert(Instr && "Missing target independent instruction"); 364 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 365 InstrsByEnum.push_back(Instr); 366 } 367 unsigned EndOfPredefines = InstrsByEnum.size(); 368 369 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator 370 I = Insts.begin(), E = Insts.end(); I != E; ++I) { 371 const CodeGenInstruction *CGI = I->second; 372 if (CGI->Namespace != "TargetOpcode") 373 InstrsByEnum.push_back(CGI); 374 } 375 376 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 377 378 // All of the instructions are now in random order based on the map iteration. 379 // Sort them by name. 380 std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(), 381 SortInstByName()); 382} 383 384 385/// isLittleEndianEncoding - Return whether this target encodes its instruction 386/// in little-endian format, i.e. bits laid out in the order [0..n] 387/// 388bool CodeGenTarget::isLittleEndianEncoding() const { 389 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 390} 391 392//===----------------------------------------------------------------------===// 393// ComplexPattern implementation 394// 395ComplexPattern::ComplexPattern(Record *R) { 396 Ty = ::getValueType(R->getValueAsDef("Ty")); 397 NumOperands = R->getValueAsInt("NumOperands"); 398 SelectFunc = R->getValueAsString("SelectFunc"); 399 RootNodes = R->getValueAsListOfDefs("RootNodes"); 400 401 // Parse the properties. 402 Properties = 0; 403 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 404 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 405 if (PropList[i]->getName() == "SDNPHasChain") { 406 Properties |= 1 << SDNPHasChain; 407 } else if (PropList[i]->getName() == "SDNPOptInFlag") { 408 Properties |= 1 << SDNPOptInFlag; 409 } else if (PropList[i]->getName() == "SDNPMayStore") { 410 Properties |= 1 << SDNPMayStore; 411 } else if (PropList[i]->getName() == "SDNPMayLoad") { 412 Properties |= 1 << SDNPMayLoad; 413 } else if (PropList[i]->getName() == "SDNPSideEffect") { 414 Properties |= 1 << SDNPSideEffect; 415 } else if (PropList[i]->getName() == "SDNPMemOperand") { 416 Properties |= 1 << SDNPMemOperand; 417 } else if (PropList[i]->getName() == "SDNPVariadic") { 418 Properties |= 1 << SDNPVariadic; 419 } else if (PropList[i]->getName() == "SDNPWantRoot") { 420 Properties |= 1 << SDNPWantRoot; 421 } else if (PropList[i]->getName() == "SDNPWantParent") { 422 Properties |= 1 << SDNPWantParent; 423 } else { 424 errs() << "Unsupported SD Node property '" << PropList[i]->getName() 425 << "' on ComplexPattern '" << R->getName() << "'!\n"; 426 exit(1); 427 } 428} 429 430//===----------------------------------------------------------------------===// 431// CodeGenIntrinsic Implementation 432//===----------------------------------------------------------------------===// 433 434std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, 435 bool TargetOnly) { 436 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic"); 437 438 std::vector<CodeGenIntrinsic> Result; 439 440 for (unsigned i = 0, e = I.size(); i != e; ++i) { 441 bool isTarget = I[i]->getValueAsBit("isTarget"); 442 if (isTarget == TargetOnly) 443 Result.push_back(CodeGenIntrinsic(I[i])); 444 } 445 return Result; 446} 447 448CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { 449 TheDef = R; 450 std::string DefName = R->getName(); 451 ModRef = ReadWriteMem; 452 isOverloaded = false; 453 isCommutative = false; 454 455 if (DefName.size() <= 4 || 456 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 457 throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; 458 459 EnumName = std::string(DefName.begin()+4, DefName.end()); 460 461 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 462 GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); 463 464 TargetPrefix = R->getValueAsString("TargetPrefix"); 465 Name = R->getValueAsString("LLVMName"); 466 467 if (Name == "") { 468 // If an explicit name isn't specified, derive one from the DefName. 469 Name = "llvm."; 470 471 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 472 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 473 } else { 474 // Verify it starts with "llvm.". 475 if (Name.size() <= 5 || 476 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 477 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; 478 } 479 480 // If TargetPrefix is specified, make sure that Name starts with 481 // "llvm.<targetprefix>.". 482 if (!TargetPrefix.empty()) { 483 if (Name.size() < 6+TargetPrefix.size() || 484 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 485 != (TargetPrefix + ".")) 486 throw "Intrinsic '" + DefName + "' does not start with 'llvm." + 487 TargetPrefix + ".'!"; 488 } 489 490 // Parse the list of return types. 491 std::vector<MVT::SimpleValueType> OverloadedVTs; 492 ListInit *TypeList = R->getValueAsListInit("RetTypes"); 493 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 494 Record *TyEl = TypeList->getElementAsRecord(i); 495 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 496 MVT::SimpleValueType VT; 497 if (TyEl->isSubClassOf("LLVMMatchType")) { 498 unsigned MatchTy = TyEl->getValueAsInt("Number"); 499 assert(MatchTy < OverloadedVTs.size() && 500 "Invalid matching number!"); 501 VT = OverloadedVTs[MatchTy]; 502 // It only makes sense to use the extended and truncated vector element 503 // variants with iAny types; otherwise, if the intrinsic is not 504 // overloaded, all the types can be specified directly. 505 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 506 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 507 VT == MVT::iAny || VT == MVT::vAny) && 508 "Expected iAny or vAny type"); 509 } else { 510 VT = getValueType(TyEl->getValueAsDef("VT")); 511 } 512 if (EVT(VT).isOverloaded()) { 513 OverloadedVTs.push_back(VT); 514 isOverloaded = true; 515 } 516 517 // Reject invalid types. 518 if (VT == MVT::isVoid) 519 throw "Intrinsic '" + DefName + " has void in result type list!"; 520 521 IS.RetVTs.push_back(VT); 522 IS.RetTypeDefs.push_back(TyEl); 523 } 524 525 // Parse the list of parameter types. 526 TypeList = R->getValueAsListInit("ParamTypes"); 527 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 528 Record *TyEl = TypeList->getElementAsRecord(i); 529 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 530 MVT::SimpleValueType VT; 531 if (TyEl->isSubClassOf("LLVMMatchType")) { 532 unsigned MatchTy = TyEl->getValueAsInt("Number"); 533 assert(MatchTy < OverloadedVTs.size() && 534 "Invalid matching number!"); 535 VT = OverloadedVTs[MatchTy]; 536 // It only makes sense to use the extended and truncated vector element 537 // variants with iAny types; otherwise, if the intrinsic is not 538 // overloaded, all the types can be specified directly. 539 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 540 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 541 VT == MVT::iAny || VT == MVT::vAny) && 542 "Expected iAny or vAny type"); 543 } else 544 VT = getValueType(TyEl->getValueAsDef("VT")); 545 546 if (EVT(VT).isOverloaded()) { 547 OverloadedVTs.push_back(VT); 548 isOverloaded = true; 549 } 550 551 // Reject invalid types. 552 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 553 throw "Intrinsic '" + DefName + " has void in result type list!"; 554 555 IS.ParamVTs.push_back(VT); 556 IS.ParamTypeDefs.push_back(TyEl); 557 } 558 559 // Parse the intrinsic properties. 560 ListInit *PropList = R->getValueAsListInit("Properties"); 561 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { 562 Record *Property = PropList->getElementAsRecord(i); 563 assert(Property->isSubClassOf("IntrinsicProperty") && 564 "Expected a property!"); 565 566 if (Property->getName() == "IntrNoMem") 567 ModRef = NoMem; 568 else if (Property->getName() == "IntrReadArgMem") 569 ModRef = ReadArgMem; 570 else if (Property->getName() == "IntrReadMem") 571 ModRef = ReadMem; 572 else if (Property->getName() == "IntrReadWriteArgMem") 573 ModRef = ReadWriteArgMem; 574 else if (Property->getName() == "Commutative") 575 isCommutative = true; 576 else if (Property->isSubClassOf("NoCapture")) { 577 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 578 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture)); 579 } else 580 assert(0 && "Unknown property!"); 581 } 582} 583