1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CodeGenRegisters.h"
17#include "CodeGenTarget.h"
18#include "SequenceToOffsetTable.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/Twine.h"
23#include "llvm/Support/Format.h"
24#include "llvm/TableGen/Error.h"
25#include "llvm/TableGen/Record.h"
26#include "llvm/TableGen/TableGenBackend.h"
27#include <algorithm>
28#include <set>
29#include <vector>
30using namespace llvm;
31
32namespace {
33class RegisterInfoEmitter {
34  RecordKeeper &Records;
35public:
36  RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
37
38  // runEnums - Print out enum values for all of the registers.
39  void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
40
41  // runMCDesc - Print out MC register descriptions.
42  void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
43
44  // runTargetHeader - Emit a header fragment for the register info emitter.
45  void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46                       CodeGenRegBank &Bank);
47
48  // runTargetDesc - Output the target register and register file descriptions.
49  void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50                     CodeGenRegBank &Bank);
51
52  // run - Output the register file description.
53  void run(raw_ostream &o);
54
55private:
56  void EmitRegMapping(raw_ostream &o,
57                      const std::vector<CodeGenRegister*> &Regs, bool isCtor);
58  void EmitRegMappingTables(raw_ostream &o,
59                            const std::vector<CodeGenRegister*> &Regs,
60                            bool isCtor);
61  void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
62
63  void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
64                           const std::string &ClassName);
65};
66} // End anonymous namespace
67
68// runEnums - Print out enum values for all of the registers.
69void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70                                   CodeGenTarget &Target, CodeGenRegBank &Bank) {
71  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
72
73  // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74  assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
75
76  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
77
78  emitSourceFileHeader("Target Register Enum Values", OS);
79
80  OS << "\n#ifdef GET_REGINFO_ENUM\n";
81  OS << "#undef GET_REGINFO_ENUM\n";
82
83  OS << "namespace llvm {\n\n";
84
85  OS << "class MCRegisterClass;\n"
86     << "extern const MCRegisterClass " << Namespace
87     << "MCRegisterClasses[];\n\n";
88
89  if (!Namespace.empty())
90    OS << "namespace " << Namespace << " {\n";
91  OS << "enum {\n  NoRegister,\n";
92
93  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
94    OS << "  " << Registers[i]->getName() << " = " <<
95      Registers[i]->EnumValue << ",\n";
96  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
97         "Register enum value mismatch!");
98  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
99  OS << "};\n";
100  if (!Namespace.empty())
101    OS << "}\n";
102
103  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
104  if (!RegisterClasses.empty()) {
105
106    // RegisterClass enums are stored as uint16_t in the tables.
107    assert(RegisterClasses.size() <= 0xffff &&
108           "Too many register classes to fit in tables");
109
110    OS << "\n// Register classes\n";
111    if (!Namespace.empty())
112      OS << "namespace " << Namespace << " {\n";
113    OS << "enum {\n";
114    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
115      if (i) OS << ",\n";
116      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
117      OS << " = " << i;
118    }
119    OS << "\n  };\n";
120    if (!Namespace.empty())
121      OS << "}\n";
122  }
123
124  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
125  // If the only definition is the default NoRegAltName, we don't need to
126  // emit anything.
127  if (RegAltNameIndices.size() > 1) {
128    OS << "\n// Register alternate name indices\n";
129    if (!Namespace.empty())
130      OS << "namespace " << Namespace << " {\n";
131    OS << "enum {\n";
132    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
133      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
134    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
135    OS << "};\n";
136    if (!Namespace.empty())
137      OS << "}\n";
138  }
139
140  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
141  if (!SubRegIndices.empty()) {
142    OS << "\n// Subregister indices\n";
143    std::string Namespace =
144      SubRegIndices[0]->getNamespace();
145    if (!Namespace.empty())
146      OS << "namespace " << Namespace << " {\n";
147    OS << "enum {\n  NoSubRegister,\n";
148    for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
149      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
150    OS << "  NUM_TARGET_SUBREGS\n};\n";
151    if (!Namespace.empty())
152      OS << "}\n";
153  }
154
155  OS << "} // End llvm namespace \n";
156  OS << "#endif // GET_REGINFO_ENUM\n\n";
157}
158
159void RegisterInfoEmitter::
160EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
161                    const std::string &ClassName) {
162  unsigned NumRCs = RegBank.getRegClasses().size();
163  unsigned NumSets = RegBank.getNumRegPressureSets();
164
165  OS << "/// Get the weight in units of pressure for this register class.\n"
166     << "const RegClassWeight &" << ClassName << "::\n"
167     << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
168     << "  static const RegClassWeight RCWeightTable[] = {\n";
169  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
170    const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
171    const CodeGenRegister::Set &Regs = RC.getMembers();
172    if (Regs.empty())
173      OS << "    {0, 0";
174    else {
175      std::vector<unsigned> RegUnits;
176      RC.buildRegUnitSet(RegUnits);
177      OS << "    {" << (*Regs.begin())->getWeight(RegBank)
178         << ", " << RegBank.getRegUnitSetWeight(RegUnits);
179    }
180    OS << "},  \t// " << RC.getName() << "\n";
181  }
182  OS << "    {0, 0} };\n"
183     << "  return RCWeightTable[RC->getID()];\n"
184     << "}\n\n";
185
186  OS << "\n"
187     << "// Get the number of dimensions of register pressure.\n"
188     << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
189     << "  return " << NumSets << ";\n}\n\n";
190
191  OS << "// Get the name of this register unit pressure set.\n"
192     << "const char *" << ClassName << "::\n"
193     << "getRegPressureSetName(unsigned Idx) const {\n"
194     << "  static const char *PressureNameTable[] = {\n";
195  for (unsigned i = 0; i < NumSets; ++i ) {
196    OS << "    \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
197  }
198  OS << "    0 };\n"
199     << "  return PressureNameTable[Idx];\n"
200     << "}\n\n";
201
202  OS << "// Get the register unit pressure limit for this dimension.\n"
203     << "// This limit must be adjusted dynamically for reserved registers.\n"
204     << "unsigned " << ClassName << "::\n"
205     << "getRegPressureSetLimit(unsigned Idx) const {\n"
206     << "  static const unsigned PressureLimitTable[] = {\n";
207  for (unsigned i = 0; i < NumSets; ++i ) {
208    const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
209    OS << "    " << RegBank.getRegUnitSetWeight(RegUnits.Units)
210       << ",  \t// " << i << ": " << RegUnits.Name << "\n";
211  }
212  OS << "    0 };\n"
213     << "  return PressureLimitTable[Idx];\n"
214     << "}\n\n";
215
216  OS << "/// Get the dimensions of register pressure "
217     << "impacted by this register class.\n"
218     << "/// Returns a -1 terminated array of pressure set IDs\n"
219     << "const int* " << ClassName << "::\n"
220     << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
221     << "  static const int RCSetsTable[] = {\n    ";
222  std::vector<unsigned> RCSetStarts(NumRCs);
223  for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
224    RCSetStarts[i] = StartIdx;
225    ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
226    for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
227           PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
228      OS << *PSetI << ",  ";
229      ++StartIdx;
230    }
231    OS << "-1,  \t// " << RegBank.getRegClasses()[i]->getName() << "\n    ";
232    ++StartIdx;
233  }
234  OS << "-1 };\n";
235  OS << "  static const unsigned RCSetStartTable[] = {\n    ";
236  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
237    OS << RCSetStarts[i] << ",";
238  }
239  OS << "0 };\n"
240     << "  unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
241     << "  return &RCSetsTable[SetListStart];\n"
242     << "}\n\n";
243}
244
245void
246RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
247                                       const std::vector<CodeGenRegister*> &Regs,
248                                          bool isCtor) {
249  // Collect all information about dwarf register numbers
250  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
251  DwarfRegNumsMapTy DwarfRegNums;
252
253  // First, just pull all provided information to the map
254  unsigned maxLength = 0;
255  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
256    Record *Reg = Regs[i]->TheDef;
257    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
258    maxLength = std::max((size_t)maxLength, RegNums.size());
259    if (DwarfRegNums.count(Reg))
260      PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
261                   getQualifiedName(Reg) + "specified multiple times");
262    DwarfRegNums[Reg] = RegNums;
263  }
264
265  if (!maxLength)
266    return;
267
268  // Now we know maximal length of number list. Append -1's, where needed
269  for (DwarfRegNumsMapTy::iterator
270       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
271    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
272      I->second.push_back(-1);
273
274  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
275
276  OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
277
278  // Emit reverse information about the dwarf register numbers.
279  for (unsigned j = 0; j < 2; ++j) {
280    for (unsigned i = 0, e = maxLength; i != e; ++i) {
281      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
282      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
283      OS << i << "Dwarf2L[]";
284
285      if (!isCtor) {
286        OS << " = {\n";
287
288        // Store the mapping sorted by the LLVM reg num so lookup can be done
289        // with a binary search.
290        std::map<uint64_t, Record*> Dwarf2LMap;
291        for (DwarfRegNumsMapTy::iterator
292               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
293          int DwarfRegNo = I->second[i];
294          if (DwarfRegNo < 0)
295            continue;
296          Dwarf2LMap[DwarfRegNo] = I->first;
297        }
298
299        for (std::map<uint64_t, Record*>::iterator
300               I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
301          OS << "  { " << I->first << "U, " << getQualifiedName(I->second)
302             << " },\n";
303
304        OS << "};\n";
305      } else {
306        OS << ";\n";
307      }
308
309      // We have to store the size in a const global, it's used in multiple
310      // places.
311      OS << "extern const unsigned " << Namespace
312         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
313      if (!isCtor)
314        OS << " = sizeof(" << Namespace
315           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
316           << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
317      else
318        OS << ";\n\n";
319    }
320  }
321
322  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
323    Record *Reg = Regs[i]->TheDef;
324    const RecordVal *V = Reg->getValue("DwarfAlias");
325    if (!V || !V->getValue())
326      continue;
327
328    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
329    Record *Alias = DI->getDef();
330    DwarfRegNums[Reg] = DwarfRegNums[Alias];
331  }
332
333  // Emit information about the dwarf register numbers.
334  for (unsigned j = 0; j < 2; ++j) {
335    for (unsigned i = 0, e = maxLength; i != e; ++i) {
336      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
337      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
338      OS << i << "L2Dwarf[]";
339      if (!isCtor) {
340        OS << " = {\n";
341        // Store the mapping sorted by the Dwarf reg num so lookup can be done
342        // with a binary search.
343        for (DwarfRegNumsMapTy::iterator
344               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
345          int RegNo = I->second[i];
346          if (RegNo == -1) // -1 is the default value, don't emit a mapping.
347            continue;
348
349          OS << "  { " << getQualifiedName(I->first) << ", " << RegNo
350             << "U },\n";
351        }
352        OS << "};\n";
353      } else {
354        OS << ";\n";
355      }
356
357      // We have to store the size in a const global, it's used in multiple
358      // places.
359      OS << "extern const unsigned " << Namespace
360         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
361      if (!isCtor)
362        OS << " = sizeof(" << Namespace
363           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
364           << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
365      else
366        OS << ";\n\n";
367    }
368  }
369}
370
371void
372RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
373                                    const std::vector<CodeGenRegister*> &Regs,
374                                    bool isCtor) {
375  // Emit the initializer so the tables from EmitRegMappingTables get wired up
376  // to the MCRegisterInfo object.
377  unsigned maxLength = 0;
378  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
379    Record *Reg = Regs[i]->TheDef;
380    maxLength = std::max((size_t)maxLength,
381                         Reg->getValueAsListOfInts("DwarfNumbers").size());
382  }
383
384  if (!maxLength)
385    return;
386
387  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
388
389  // Emit reverse information about the dwarf register numbers.
390  for (unsigned j = 0; j < 2; ++j) {
391    OS << "  switch (";
392    if (j == 0)
393      OS << "DwarfFlavour";
394    else
395      OS << "EHFlavour";
396    OS << ") {\n"
397     << "  default:\n"
398     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
399
400    for (unsigned i = 0, e = maxLength; i != e; ++i) {
401      OS << "  case " << i << ":\n";
402      OS << "    ";
403      if (!isCtor)
404        OS << "RI->";
405      std::string Tmp;
406      raw_string_ostream(Tmp) << Namespace
407                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
408                              << "Dwarf2L";
409      OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
410      if (j == 0)
411          OS << "false";
412        else
413          OS << "true";
414      OS << ");\n";
415      OS << "    break;\n";
416    }
417    OS << "  }\n";
418  }
419
420  // Emit information about the dwarf register numbers.
421  for (unsigned j = 0; j < 2; ++j) {
422    OS << "  switch (";
423    if (j == 0)
424      OS << "DwarfFlavour";
425    else
426      OS << "EHFlavour";
427    OS << ") {\n"
428       << "  default:\n"
429       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
430
431    for (unsigned i = 0, e = maxLength; i != e; ++i) {
432      OS << "  case " << i << ":\n";
433      OS << "    ";
434      if (!isCtor)
435        OS << "RI->";
436      std::string Tmp;
437      raw_string_ostream(Tmp) << Namespace
438                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
439                              << "L2Dwarf";
440      OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
441      if (j == 0)
442          OS << "false";
443        else
444          OS << "true";
445      OS << ");\n";
446      OS << "    break;\n";
447    }
448    OS << "  }\n";
449  }
450}
451
452// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
453// Width is the number of bits per hex number.
454static void printBitVectorAsHex(raw_ostream &OS,
455                                const BitVector &Bits,
456                                unsigned Width) {
457  assert(Width <= 32 && "Width too large");
458  unsigned Digits = (Width + 3) / 4;
459  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
460    unsigned Value = 0;
461    for (unsigned j = 0; j != Width && i + j != e; ++j)
462      Value |= Bits.test(i + j) << j;
463    OS << format("0x%0*x, ", Digits, Value);
464  }
465}
466
467// Helper to emit a set of bits into a constant byte array.
468class BitVectorEmitter {
469  BitVector Values;
470public:
471  void add(unsigned v) {
472    if (v >= Values.size())
473      Values.resize(((v/8)+1)*8); // Round up to the next byte.
474    Values[v] = true;
475  }
476
477  void print(raw_ostream &OS) {
478    printBitVectorAsHex(OS, Values, 8);
479  }
480};
481
482static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
483  OS << getEnumName(VT);
484}
485
486static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
487  OS << Idx->EnumValue;
488}
489
490// Differentially encoded register and regunit lists allow for better
491// compression on regular register banks. The sequence is computed from the
492// differential list as:
493//
494//   out[0] = InitVal;
495//   out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
496//
497// The initial value depends on the specific list. The list is terminated by a
498// 0 differential which means we can't encode repeated elements.
499
500typedef SmallVector<uint16_t, 4> DiffVec;
501
502// Differentially encode a sequence of numbers into V. The starting value and
503// terminating 0 are not added to V, so it will have the same size as List.
504static
505DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
506  assert(V.empty() && "Clear DiffVec before diffEncode.");
507  uint16_t Val = uint16_t(InitVal);
508  for (unsigned i = 0; i != List.size(); ++i) {
509    uint16_t Cur = List[i];
510    V.push_back(Cur - Val);
511    Val = Cur;
512  }
513  return V;
514}
515
516template<typename Iter>
517static
518DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
519  assert(V.empty() && "Clear DiffVec before diffEncode.");
520  uint16_t Val = uint16_t(InitVal);
521  for (Iter I = Begin; I != End; ++I) {
522    uint16_t Cur = (*I)->EnumValue;
523    V.push_back(Cur - Val);
524    Val = Cur;
525  }
526  return V;
527}
528
529static void printDiff16(raw_ostream &OS, uint16_t Val) {
530  OS << Val;
531}
532
533//
534// runMCDesc - Print out MC register descriptions.
535//
536void
537RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
538                               CodeGenRegBank &RegBank) {
539  emitSourceFileHeader("MC Register Information", OS);
540
541  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
542  OS << "#undef GET_REGINFO_MC_DESC\n";
543
544  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
545
546  // The lists of sub-registers, super-registers, and overlaps all go in the
547  // same array. That allows us to share suffixes.
548  typedef std::vector<const CodeGenRegister*> RegVec;
549
550  // Differentially encoded lists.
551  SequenceToOffsetTable<DiffVec> DiffSeqs;
552  SmallVector<DiffVec, 4> SubRegLists(Regs.size());
553  SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
554  SmallVector<DiffVec, 4> OverlapLists(Regs.size());
555  SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
556  SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
557
558  // Keep track of sub-register names as well. These are not differentially
559  // encoded.
560  typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
561  SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs;
562  SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
563
564  SequenceToOffsetTable<std::string> RegStrings;
565
566  // Precompute register lists for the SequenceToOffsetTable.
567  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
568    const CodeGenRegister *Reg = Regs[i];
569
570    RegStrings.add(Reg->getName());
571
572    // Compute the ordered sub-register list.
573    SetVector<const CodeGenRegister*> SR;
574    Reg->addSubRegsPreOrder(SR, RegBank);
575    diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
576    DiffSeqs.add(SubRegLists[i]);
577
578    // Compute the corresponding sub-register indexes.
579    SubRegIdxVec &SRIs = SubRegIdxLists[i];
580    for (unsigned j = 0, je = SR.size(); j != je; ++j)
581      SRIs.push_back(Reg->getSubRegIndex(SR[j]));
582    SubRegIdxSeqs.add(SRIs);
583
584    // Super-registers are already computed.
585    const RegVec &SuperRegList = Reg->getSuperRegs();
586    diffEncode(SuperRegLists[i], Reg->EnumValue,
587               SuperRegList.begin(), SuperRegList.end());
588    DiffSeqs.add(SuperRegLists[i]);
589
590    // The list of overlaps doesn't need to have any particular order, and Reg
591    // itself must be omitted.
592    DiffVec &OverlapList = OverlapLists[i];
593    CodeGenRegister::Set OSet;
594    Reg->computeOverlaps(OSet, RegBank);
595    OSet.erase(Reg);
596    diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end());
597    DiffSeqs.add(OverlapList);
598
599    // Differentially encode the register unit list, seeded by register number.
600    // First compute a scale factor that allows more diff-lists to be reused:
601    //
602    //   D0 -> (S0, S1)
603    //   D1 -> (S2, S3)
604    //
605    // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
606    // value for the differential decoder is the register number multiplied by
607    // the scale.
608    //
609    // Check the neighboring registers for arithmetic progressions.
610    unsigned ScaleA = ~0u, ScaleB = ~0u;
611    ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
612    if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
613      ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
614    if (i+1 != Regs.size() &&
615        Regs[i+1]->getNativeRegUnits().size() == RUs.size())
616      ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
617    unsigned Scale = std::min(ScaleB, ScaleA);
618    // Default the scale to 0 if it can't be encoded in 4 bits.
619    if (Scale >= 16)
620      Scale = 0;
621    RegUnitInitScale[i] = Scale;
622    DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
623  }
624
625  // Compute the final layout of the sequence table.
626  DiffSeqs.layout();
627  SubRegIdxSeqs.layout();
628
629  OS << "namespace llvm {\n\n";
630
631  const std::string &TargetName = Target.getName();
632
633  // Emit the shared table of differential lists.
634  OS << "extern const uint16_t " << TargetName << "RegDiffLists[] = {\n";
635  DiffSeqs.emit(OS, printDiff16);
636  OS << "};\n\n";
637
638  // Emit the table of sub-register indexes.
639  OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
640  SubRegIdxSeqs.emit(OS, printSubRegIndex);
641  OS << "};\n\n";
642
643  // Emit the string table.
644  RegStrings.layout();
645  OS << "extern const char " << TargetName << "RegStrings[] = {\n";
646  RegStrings.emit(OS, printChar);
647  OS << "};\n\n";
648
649  OS << "extern const MCRegisterDesc " << TargetName
650     << "RegDesc[] = { // Descriptors\n";
651  OS << "  { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
652
653  // Emit the register descriptors now.
654  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
655    const CodeGenRegister *Reg = Regs[i];
656    OS << "  { " << RegStrings.get(Reg->getName()) << ", "
657       << DiffSeqs.get(OverlapLists[i]) << ", "
658       << DiffSeqs.get(SubRegLists[i]) << ", "
659       << DiffSeqs.get(SuperRegLists[i]) << ", "
660       << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
661       << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
662  }
663  OS << "};\n\n";      // End of register descriptors...
664
665  // Emit the table of register unit roots. Each regunit has one or two root
666  // registers.
667  OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
668  for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
669    ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
670    assert(!Roots.empty() && "All regunits must have a root register.");
671    assert(Roots.size() <= 2 && "More than two roots not supported yet.");
672    OS << "  { " << getQualifiedName(Roots.front()->TheDef);
673    for (unsigned r = 1; r != Roots.size(); ++r)
674      OS << ", " << getQualifiedName(Roots[r]->TheDef);
675    OS << " },\n";
676  }
677  OS << "};\n\n";
678
679  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
680
681  // Loop over all of the register classes... emitting each one.
682  OS << "namespace {     // Register classes...\n";
683
684  // Emit the register enum value arrays for each RegisterClass
685  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
686    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
687    ArrayRef<Record*> Order = RC.getOrder();
688
689    // Give the register class a legal C name if it's anonymous.
690    std::string Name = RC.getName();
691
692    // Emit the register list now.
693    OS << "  // " << Name << " Register Class...\n"
694       << "  const uint16_t " << Name
695       << "[] = {\n    ";
696    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
697      Record *Reg = Order[i];
698      OS << getQualifiedName(Reg) << ", ";
699    }
700    OS << "\n  };\n\n";
701
702    OS << "  // " << Name << " Bit set.\n"
703       << "  const uint8_t " << Name
704       << "Bits[] = {\n    ";
705    BitVectorEmitter BVE;
706    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
707      Record *Reg = Order[i];
708      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
709    }
710    BVE.print(OS);
711    OS << "\n  };\n\n";
712
713  }
714  OS << "}\n\n";
715
716  OS << "extern const MCRegisterClass " << TargetName
717     << "MCRegisterClasses[] = {\n";
718
719  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
720    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
721
722    // Asserts to make sure values will fit in table assuming types from
723    // MCRegisterInfo.h
724    assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
725    assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
726    assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
727
728    OS << "  { " << '\"' << RC.getName() << "\", "
729       << RC.getName() << ", " << RC.getName() << "Bits, "
730       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
731       << RC.getQualifiedName() + "RegClassID" << ", "
732       << RC.SpillSize/8 << ", "
733       << RC.SpillAlignment/8 << ", "
734       << RC.CopyCost << ", "
735       << RC.Allocatable << " },\n";
736  }
737
738  OS << "};\n\n";
739
740  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
741
742  EmitRegMappingTables(OS, Regs, false);
743
744  // Emit Reg encoding table
745  OS << "extern const uint16_t " << TargetName;
746  OS << "RegEncodingTable[] = {\n";
747  // Add entry for NoRegister
748  OS << "  0,\n";
749  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
750    Record *Reg = Regs[i]->TheDef;
751    BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
752    uint64_t Value = 0;
753    for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
754      if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(b)))
755      Value |= (uint64_t)B->getValue() << b;
756    }
757    OS << "  " << Value << ",\n";
758  }
759  OS << "};\n";       // End of HW encoding table
760
761  // MCRegisterInfo initialization routine.
762  OS << "static inline void Init" << TargetName
763     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
764     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n"
765     << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
766     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
767     << RegisterClasses.size() << ", "
768     << TargetName << "RegUnitRoots, "
769     << RegBank.getNumNativeRegUnits() << ", "
770     << TargetName << "RegDiffLists, "
771     << TargetName << "RegStrings, "
772     << TargetName << "SubRegIdxLists, "
773     << SubRegIndices.size() << ",\n"
774     << "  " << TargetName << "RegEncodingTable);\n\n";
775
776  EmitRegMapping(OS, Regs, false);
777
778  OS << "}\n\n";
779
780  OS << "} // End llvm namespace \n";
781  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
782}
783
784void
785RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
786                                     CodeGenRegBank &RegBank) {
787  emitSourceFileHeader("Register Information Header Fragment", OS);
788
789  OS << "\n#ifdef GET_REGINFO_HEADER\n";
790  OS << "#undef GET_REGINFO_HEADER\n";
791
792  const std::string &TargetName = Target.getName();
793  std::string ClassName = TargetName + "GenRegisterInfo";
794
795  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
796
797  OS << "namespace llvm {\n\n";
798
799  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
800     << "  explicit " << ClassName
801     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
802     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
803     << "     { return false; }\n";
804  if (!RegBank.getSubRegIndices().empty()) {
805    OS << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
806      << "  const TargetRegisterClass *"
807      "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
808  }
809  OS << "  const RegClassWeight &getRegClassWeight("
810     << "const TargetRegisterClass *RC) const;\n"
811     << "  unsigned getNumRegPressureSets() const;\n"
812     << "  const char *getRegPressureSetName(unsigned Idx) const;\n"
813     << "  unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
814     << "  const int *getRegClassPressureSets("
815     << "const TargetRegisterClass *RC) const;\n"
816     << "};\n\n";
817
818  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
819
820  if (!RegisterClasses.empty()) {
821    OS << "namespace " << RegisterClasses[0]->Namespace
822       << " { // Register classes\n";
823
824    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
825      const CodeGenRegisterClass &RC = *RegisterClasses[i];
826      const std::string &Name = RC.getName();
827
828      // Output the extern for the instance.
829      OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
830    }
831    OS << "} // end of namespace " << TargetName << "\n\n";
832  }
833  OS << "} // End llvm namespace \n";
834  OS << "#endif // GET_REGINFO_HEADER\n\n";
835}
836
837//
838// runTargetDesc - Output the target register and register file descriptions.
839//
840void
841RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
842                                   CodeGenRegBank &RegBank){
843  emitSourceFileHeader("Target Register and Register Classes Information", OS);
844
845  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
846  OS << "#undef GET_REGINFO_TARGET_DESC\n";
847
848  OS << "namespace llvm {\n\n";
849
850  // Get access to MCRegisterClass data.
851  OS << "extern const MCRegisterClass " << Target.getName()
852     << "MCRegisterClasses[];\n";
853
854  // Start out by emitting each of the register classes.
855  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
856  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
857
858  // Collect all registers belonging to any allocatable class.
859  std::set<Record*> AllocatableRegs;
860
861  // Collect allocatable registers.
862  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
863    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
864    ArrayRef<Record*> Order = RC.getOrder();
865
866    if (RC.Allocatable)
867      AllocatableRegs.insert(Order.begin(), Order.end());
868  }
869
870  // Build a shared array of value types.
871  SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
872  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
873    VTSeqs.add(RegisterClasses[rc]->VTs);
874  VTSeqs.layout();
875  OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
876  VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
877  OS << "};\n";
878
879  // Emit SubRegIndex names, skipping 0
880  OS << "\nstatic const char *const SubRegIndexTable[] = { \"";
881  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
882    OS << SubRegIndices[i]->getName();
883    if (i+1 != e)
884      OS << "\", \"";
885  }
886  OS << "\" };\n\n";
887
888  OS << "\n";
889
890  // Now that all of the structs have been emitted, emit the instances.
891  if (!RegisterClasses.empty()) {
892    OS << "\nstatic const TargetRegisterClass *const "
893       << "NullRegClasses[] = { NULL };\n\n";
894
895    // Emit register class bit mask tables. The first bit mask emitted for a
896    // register class, RC, is the set of sub-classes, including RC itself.
897    //
898    // If RC has super-registers, also create a list of subreg indices and bit
899    // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
900    // SuperRC, that satisfies:
901    //
902    //   For all SuperReg in SuperRC: SuperReg:Idx in RC
903    //
904    // The 0-terminated list of subreg indices starts at:
905    //
906    //   RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
907    //
908    // The corresponding bitmasks follow the sub-class mask in memory. Each
909    // mask has RCMaskWords uint32_t entries.
910    //
911    // Every bit mask present in the list has at least one bit set.
912
913    // Compress the sub-reg index lists.
914    typedef std::vector<const CodeGenSubRegIndex*> IdxList;
915    SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
916    SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
917    BitVector MaskBV(RegisterClasses.size());
918
919    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
920      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
921      OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n  ";
922      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
923
924      // Emit super-reg class masks for any relevant SubRegIndices that can
925      // project into RC.
926      IdxList &SRIList = SuperRegIdxLists[rc];
927      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
928        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
929        MaskBV.reset();
930        RC.getSuperRegClasses(Idx, MaskBV);
931        if (MaskBV.none())
932          continue;
933        SRIList.push_back(Idx);
934        OS << "\n  ";
935        printBitVectorAsHex(OS, MaskBV, 32);
936        OS << "// " << Idx->getName();
937      }
938      SuperRegIdxSeqs.add(SRIList);
939      OS << "\n};\n\n";
940    }
941
942    OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
943    SuperRegIdxSeqs.layout();
944    SuperRegIdxSeqs.emit(OS, printSubRegIndex);
945    OS << "};\n\n";
946
947    // Emit NULL terminated super-class lists.
948    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
949      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
950      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
951
952      // Skip classes without supers.  We can reuse NullRegClasses.
953      if (Supers.empty())
954        continue;
955
956      OS << "static const TargetRegisterClass *const "
957         << RC.getName() << "Superclasses[] = {\n";
958      for (unsigned i = 0; i != Supers.size(); ++i)
959        OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
960      OS << "  NULL\n};\n\n";
961    }
962
963    // Emit methods.
964    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
965      const CodeGenRegisterClass &RC = *RegisterClasses[i];
966      if (!RC.AltOrderSelect.empty()) {
967        OS << "\nstatic inline unsigned " << RC.getName()
968           << "AltOrderSelect(const MachineFunction &MF) {"
969           << RC.AltOrderSelect << "}\n\n"
970           << "static ArrayRef<uint16_t> " << RC.getName()
971           << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
972        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
973          ArrayRef<Record*> Elems = RC.getOrder(oi);
974          if (!Elems.empty()) {
975            OS << "  static const uint16_t AltOrder" << oi << "[] = {";
976            for (unsigned elem = 0; elem != Elems.size(); ++elem)
977              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
978            OS << " };\n";
979          }
980        }
981        OS << "  const MCRegisterClass &MCR = " << Target.getName()
982           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
983           << "  const ArrayRef<uint16_t> Order[] = {\n"
984           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
985        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
986          if (RC.getOrder(oi).empty())
987            OS << "),\n    ArrayRef<uint16_t>(";
988          else
989            OS << "),\n    makeArrayRef(AltOrder" << oi;
990        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
991           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
992           << ");\n  return Order[Select];\n}\n";
993        }
994    }
995
996    // Now emit the actual value-initialized register class instances.
997    OS << "namespace " << RegisterClasses[0]->Namespace
998       << " {   // Register class instances\n";
999
1000    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1001      const CodeGenRegisterClass &RC = *RegisterClasses[i];
1002      OS << "  extern const TargetRegisterClass "
1003         << RegisterClasses[i]->getName() << "RegClass = {\n    "
1004         << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1005         << "RegClassID],\n    "
1006         << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
1007         << RC.getName() << "SubClassMask,\n    SuperRegIdxSeqs + "
1008         << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n    ";
1009      if (RC.getSuperClasses().empty())
1010        OS << "NullRegClasses,\n    ";
1011      else
1012        OS << RC.getName() << "Superclasses,\n    ";
1013      if (RC.AltOrderSelect.empty())
1014        OS << "0\n";
1015      else
1016        OS << RC.getName() << "GetRawAllocationOrder\n";
1017      OS << "  };\n\n";
1018    }
1019
1020    OS << "}\n";
1021  }
1022
1023  OS << "\nnamespace {\n";
1024  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
1025  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1026    OS << "    &" << RegisterClasses[i]->getQualifiedName()
1027       << "RegClass,\n";
1028  OS << "  };\n";
1029  OS << "}\n";       // End of anonymous namespace...
1030
1031  // Emit extra information about registers.
1032  const std::string &TargetName = Target.getName();
1033  OS << "\nstatic const TargetRegisterInfoDesc "
1034     << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1035  OS << "  { 0, 0 },\n";
1036
1037  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1038  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1039    const CodeGenRegister &Reg = *Regs[i];
1040    OS << "  { ";
1041    OS << Reg.CostPerUse << ", "
1042       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1043  }
1044  OS << "};\n";      // End of register descriptors...
1045
1046
1047  std::string ClassName = Target.getName() + "GenRegisterInfo";
1048
1049  // Emit composeSubRegIndices
1050  if (!SubRegIndices.empty()) {
1051    OS << "unsigned " << ClassName
1052      << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
1053      << "  switch (IdxA) {\n"
1054      << "  default:\n    return IdxB;\n";
1055    for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1056      bool Open = false;
1057      for (unsigned j = 0; j != e; ++j) {
1058        if (CodeGenSubRegIndex *Comp =
1059            SubRegIndices[i]->compose(SubRegIndices[j])) {
1060          if (!Open) {
1061            OS << "  case " << SubRegIndices[i]->getQualifiedName()
1062              << ": switch(IdxB) {\n    default: return IdxB;\n";
1063            Open = true;
1064          }
1065          OS << "    case " << SubRegIndices[j]->getQualifiedName()
1066            << ": return " << Comp->getQualifiedName() << ";\n";
1067        }
1068      }
1069      if (Open)
1070        OS << "    }\n";
1071    }
1072    OS << "  }\n}\n\n";
1073  }
1074
1075  // Emit getSubClassWithSubReg.
1076  if (!SubRegIndices.empty()) {
1077    OS << "const TargetRegisterClass *" << ClassName
1078       << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1079       << " const {\n";
1080    // Use the smallest type that can hold a regclass ID with room for a
1081    // sentinel.
1082    if (RegisterClasses.size() < UINT8_MAX)
1083      OS << "  static const uint8_t Table[";
1084    else if (RegisterClasses.size() < UINT16_MAX)
1085      OS << "  static const uint16_t Table[";
1086    else
1087      throw "Too many register classes.";
1088    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1089    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1090      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1091      OS << "    {\t// " << RC.getName() << "\n";
1092      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1093        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1094        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1095          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1096             << " -> " << SRC->getName() << "\n";
1097        else
1098          OS << "      0,\t// " << Idx->getName() << "\n";
1099      }
1100      OS << "    },\n";
1101    }
1102    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
1103       << "  if (!Idx) return RC;\n  --Idx;\n"
1104       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1105       << "  unsigned TV = Table[RC->getID()][Idx];\n"
1106       << "  return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
1107  }
1108
1109  EmitRegUnitPressure(OS, RegBank, ClassName);
1110
1111  // Emit the constructor of the class...
1112  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1113  OS << "extern const uint16_t " << TargetName << "RegDiffLists[];\n";
1114  OS << "extern const char " << TargetName << "RegStrings[];\n";
1115  OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
1116  OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1117  OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1118
1119  EmitRegMappingTables(OS, Regs, true);
1120
1121  OS << ClassName << "::\n" << ClassName
1122     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1123     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1124     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1125     << "             SubRegIndexTable) {\n"
1126     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
1127     << Regs.size()+1 << ", RA,\n                     " << TargetName
1128     << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1129     << "                     " << TargetName << "RegUnitRoots,\n"
1130     << "                     " << RegBank.getNumNativeRegUnits() << ",\n"
1131     << "                     " << TargetName << "RegDiffLists,\n"
1132     << "                     " << TargetName << "RegStrings,\n"
1133     << "                     " << TargetName << "SubRegIdxLists,\n"
1134     << "                     " << SubRegIndices.size() << ",\n"
1135     << "                     " << TargetName << "RegEncodingTable);\n\n";
1136
1137  EmitRegMapping(OS, Regs, true);
1138
1139  OS << "}\n\n";
1140
1141
1142  // Emit CalleeSavedRegs information.
1143  std::vector<Record*> CSRSets =
1144    Records.getAllDerivedDefinitions("CalleeSavedRegs");
1145  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1146    Record *CSRSet = CSRSets[i];
1147    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1148    assert(Regs && "Cannot expand CalleeSavedRegs instance");
1149
1150    // Emit the *_SaveList list of callee-saved registers.
1151    OS << "static const uint16_t " << CSRSet->getName()
1152       << "_SaveList[] = { ";
1153    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1154      OS << getQualifiedName((*Regs)[r]) << ", ";
1155    OS << "0 };\n";
1156
1157    // Emit the *_RegMask bit mask of call-preserved registers.
1158    OS << "static const uint32_t " << CSRSet->getName()
1159       << "_RegMask[] = { ";
1160    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1161    OS << "};\n";
1162  }
1163  OS << "\n\n";
1164
1165  OS << "} // End llvm namespace \n";
1166  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1167}
1168
1169void RegisterInfoEmitter::run(raw_ostream &OS) {
1170  CodeGenTarget Target(Records);
1171  CodeGenRegBank &RegBank = Target.getRegBank();
1172  RegBank.computeDerivedInfo();
1173
1174  runEnums(OS, Target, RegBank);
1175  runMCDesc(OS, Target, RegBank);
1176  runTargetHeader(OS, Target, RegBank);
1177  runTargetDesc(OS, Target, RegBank);
1178}
1179
1180namespace llvm {
1181
1182void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1183  RegisterInfoEmitter(RK).run(OS);
1184}
1185
1186} // End llvm namespace
1187