1#ifndef HW_PC_H
2#define HW_PC_H
3
4#include "qemu-common.h"
5
6/* PC-style peripherals (also used by other machines).  */
7
8/* serial.c */
9
10SerialState *serial_init(int base, qemu_irq irq, int baudbase,
11                         CharDriverState *chr);
12SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
13                             qemu_irq irq, int baudbase,
14                             CharDriverState *chr, int ioregister);
15uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
16void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
17uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
18void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
19uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
20void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
21
22/* parallel.c */
23
24typedef struct ParallelState ParallelState;
25ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
26ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
27
28/* i8259.c */
29
30typedef struct PicState2 PicState2;
31extern PicState2 *isa_pic;
32void pic_set_irq(int irq, int level);
33void pic_set_irq_new(void *opaque, int irq, int level);
34qemu_irq *i8259_init(qemu_irq parent_irq);
35void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
36                          void *alt_irq_opaque);
37int pic_read_irq(PicState2 *s);
38void pic_update_irq(PicState2 *s);
39uint32_t pic_intack_read(PicState2 *s);
40void pic_info(Monitor *mon);
41void irq_info(Monitor *mon);
42
43/* APIC */
44typedef struct IOAPICState IOAPICState;
45void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
46                             uint8_t delivery_mode,
47                             uint8_t vector_num, uint8_t polarity,
48                             uint8_t trigger_mode);
49int apic_init(CPUState *env);
50int apic_accept_pic_intr(CPUState *env);
51void apic_deliver_pic_intr(CPUState *env, int level);
52int apic_get_interrupt(CPUState *env);
53IOAPICState *ioapic_init(void);
54void ioapic_set_irq(void *opaque, int vector, int level);
55void apic_reset_irq_delivered(void);
56int apic_get_irq_delivered(void);
57
58/* i8254.c */
59
60#define PIT_FREQ 1193182
61
62typedef struct PITState PITState;
63
64PITState *pit_init(int base, qemu_irq irq);
65void pit_set_gate(PITState *pit, int channel, int val);
66int pit_get_gate(PITState *pit, int channel);
67int pit_get_initial_count(PITState *pit, int channel);
68int pit_get_mode(PITState *pit, int channel);
69int pit_get_out(PITState *pit, int channel, int64_t current_time);
70
71void hpet_pit_disable(void);
72void hpet_pit_enable(void);
73
74/* vmport.c */
75void vmport_init(void);
76void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
77
78/* vmmouse.c */
79void *vmmouse_init(void *m);
80
81/* pckbd.c */
82
83void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
84void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
85                   target_phys_addr_t base, ram_addr_t size,
86                   target_phys_addr_t mask);
87
88/* mc146818rtc.c */
89
90typedef struct RTCState RTCState;
91
92RTCState *rtc_init(int base, qemu_irq irq, int base_year);
93RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year);
94RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
95                      int base_year);
96void rtc_set_memory(RTCState *s, int addr, int val);
97void rtc_set_date(RTCState *s, const struct tm *tm);
98void cmos_set_s3_resume(void);
99
100/* pc.c */
101extern int fd_bootchk;
102
103void ioport_set_a20(int enable);
104int ioport_get_a20(void);
105
106/* acpi.c */
107extern int acpi_enabled;
108extern char *acpi_tables;
109extern size_t acpi_tables_len;
110
111i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
112                       qemu_irq sci_irq);
113void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
114void acpi_bios_init(void);
115int acpi_table_add(const char *table_desc);
116
117/* hpet.c */
118extern int no_hpet;
119
120/* pcspk.c */
121void pcspk_init(PITState *);
122int pcspk_audio_init(qemu_irq *pic);
123
124/* piix_pci.c */
125PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
126void i440fx_set_smm(PCIDevice *d, int val);
127int piix3_init(PCIBus *bus, int devfn);
128void i440fx_init_memory_mappings(PCIDevice *d);
129
130extern PCIDevice *piix4_dev;
131int piix4_init(PCIBus *bus, int devfn);
132
133/* vga.c */
134enum vga_retrace_method {
135    VGA_RETRACE_DUMB,
136    VGA_RETRACE_PRECISE
137};
138
139extern enum vga_retrace_method vga_retrace_method;
140
141int isa_vga_init(void);
142int pci_vga_init(PCIBus *bus,
143                 unsigned long vga_bios_offset, int vga_bios_size);
144int isa_vga_mm_init(target_phys_addr_t vram_base,
145                    target_phys_addr_t ctrl_base, int it_shift);
146
147/* cirrus_vga.c */
148void pci_cirrus_vga_init(PCIBus *bus);
149void isa_cirrus_vga_init(void);
150
151/* ide.c */
152void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
153                  BlockDriverState *hd0, BlockDriverState *hd1);
154void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
155                         int secondary_ide_enabled);
156void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
157                        qemu_irq *pic);
158void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
159                        qemu_irq *pic);
160
161/* ne2000.c */
162
163void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
164
165int cpu_is_bsp(CPUState *env);
166#endif
167