1/*
2 * Copyright (C) 2006 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16/*
17 *  memset32.S
18 *
19 */
20
21    .text
22    .align
23
24    .global android_memset32
25    .type   android_memset32, %function
26    .global android_memset16
27    .type   android_memset16, %function
28
29        /*
30         * Optimized memset32 and memset16 for ARM.
31         *
32         * void android_memset16(uint16_t* dst, uint16_t value, size_t size);
33         * void android_memset32(uint32_t* dst, uint32_t value, size_t size);
34         *
35         */
36
37android_memset16:
38        .fnstart
39        cmp         r2, #1
40        bxle        lr
41
42        /* expand the data to 32 bits */
43        mov         r1, r1, lsl #16
44        orr         r1, r1, r1, lsr #16
45
46        /* align to 32 bits */
47        tst         r0, #2
48        strneh      r1, [r0], #2
49        subne       r2, r2, #2
50        .fnend
51
52android_memset32:
53        .fnstart
54        .save       {lr}
55        str         lr, [sp, #-4]!
56
57        /* align the destination to a cache-line */
58        mov         r12, r1
59        mov         lr, r1
60        rsb         r3, r0, #0
61        ands        r3, r3, #0x1C
62        beq         .Laligned32
63        cmp         r3, r2
64        andhi       r3, r2, #0x1C
65        sub         r2, r2, r3
66
67        /* conditionally writes 0 to 7 words (length in r3) */
68        movs        r3, r3, lsl #28
69        stmcsia     r0!, {r1, lr}
70        stmcsia     r0!, {r1, lr}
71        stmmiia     r0!, {r1, lr}
72        movs        r3, r3, lsl #2
73        strcs       r1, [r0], #4
74
75.Laligned32:
76        mov         r3, r1
771:      subs        r2, r2, #32
78        stmhsia     r0!, {r1,r3,r12,lr}
79        stmhsia     r0!, {r1,r3,r12,lr}
80        bhs         1b
81        add         r2, r2, #32
82
83        /* conditionally stores 0 to 30 bytes */
84        movs        r2, r2, lsl #28
85        stmcsia     r0!, {r1,r3,r12,lr}
86        stmmiia     r0!, {r1,lr}
87        movs        r2, r2, lsl #2
88        strcs       r1, [r0], #4
89        strmih      lr, [r0], #2
90
91        ldr         lr, [sp], #4
92        bx          lr
93        .fnend
94