| c05d30601ced172b55be81bb529df6be91d6ae15 |
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06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
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06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 1300f3019e5d590231bbc3d907626708515d3212 |
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16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 |
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17-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37 |
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11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| a4e1ba53ddedd08669886b2849926bb33facc198 |
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03-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a new target independent COPY instruction and code to lower it.
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 65766ce7df779ac0e7f6ee0171562b56769ae1dd |
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02-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.
Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| d8ab9b415de10320315644a72ce6c5d3b8f6bc9b |
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09-Jun-2010 |
Bill Wendling <isanbard@gmail.com> |
- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it
is used to assert that an *implicit* zext is performed.
- Fix grammar-o in INSERT_SUBREG. (required reformatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| b55c8bed9d0f3eaa454a657746d8ec11aae9dea3 |
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01-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.
This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.
This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.
Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
= use v1024
= use v1028
But this adds pseudo live interval overlap between v1024 and v1025.
We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
= use v1024
= use v1026
After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
= use v1026<3>
= use v1026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 2516d0d7b1062f512bd57d142c966b3ae18ada7c |
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01-Mar-2010 |
Dan Gohman <gohman@apple.com> |
Use Doxygen comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
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| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
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09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/Target/TargetOpcodes.h
|