| 43600e95ec3690b37d458a6d3d56941ad84cddcb |
|
13-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.
The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.
When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| acf2077ca497980a066e8e7bb81ceec0de82d5da |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| c1f6f42049696e7357fb4837e1b25dabbaed3fe6 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes to match coding standards. Fix an issue or two exposed by that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| c01810eeb7227010f73cb39e3c4fa0197a3c4ef0 |
|
29-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM implement TargetInstrInfo::getNoopForMachoTarget()
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b |
|
05-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e |
|
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| aa9f0a57d03b1eef5a58c48b05f6657d2a5a0d0a |
|
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide an option to restore old-style if-conversion heuristics for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| b20b85168c0e9819e6545f08281e9b83c82108f0 |
|
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| ac2736670034e8942939b9fccf8e4618a0bda908 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
|
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 |
|
22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 68fc2daf8fa446be04d2ed2b3cbb1b00c382458f |
|
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| fdc834046efd427d474e3b899ec69354c05071e0 |
|
08-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 31c24bf5b39cc8391d4cfdbf8cf5163975fdb81e |
|
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup of file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| d457e6e9a5cd975baf4d1f0578382ab8373e6153 |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 78e5c1140adc926e7c004748c1c912bfddd875b4 |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| bd79fc8ef2543c16239f840a03b6c338cf42399d |
|
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| b9803a8fa65f043c96612fa9c5aeeee12739db2b |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 6495f63945e8dbde81f03a1dc2ab421993b9a495 |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 5732ca084aaa0cd26149e50dd4b487efff37fe41 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 5ff58b5c3ab6df332600678798ea5c69c5e943d3 |
|
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| b53cc014d0f47b898c9daca34566c16dda6c4c1e |
|
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcf |
|
17-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 |
|
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| 334c26473bba3ad8b88341bb0d25d0ac2008bb8d |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|
| b50ea5c48f8b1ce259e034ca5c16dc14af1a582c |
|
03-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.h
|