| 90c64cbaa124e0e8541680efeaa56f0e6eb78d9a |
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07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add proper formal parameter handling for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| c018ecac2f2f475b6e1023e90d0e48fcf9bd6e1d |
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26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add folding helper
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| e3111964a0902bc38440980b0915b189f829c395 |
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18-Feb-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| e9ba1830df2efef3da113a740909195e839ebd36 |
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16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| d66bd704cc92fed8292e06018e4f26547d1c96d0 |
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08-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Dump the function name when TargetLowering::LowerCall() fails
Also output a more useful error message.
NOTE: This is a candidate for the Mesa stable branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
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06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| 29b15a378045762ce09642ab9dd741ece41f59a3 |
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05-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: improve inputs/interpolation handling
Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.
Patch By: Vadim Girlin
v2[Vincent Lejeune]: Rebased against current llvm master
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| c7e1888d93f4cb2982266986f3af7e99df631fa1 |
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23-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add a CONST_ADDRESS node to model constant buf read
Patch by: Vincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|