| 7c1ac767691b2cb5d3367e667e51714f34eb675b |
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29-Jan-2013 |
Hans Wennborg <hans@hanshq.net> |
Fix typo in X86BaseInfo.h that I introduced in r157818.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| be02a90de17f857ba65bbd8a11653ca1bad30adc |
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08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 305b515c2787f47adecbe120e4b4bef55c5e5525 |
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20-Jun-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Remove 'static' from inline functions defined in header files.
There is a pretty staggering amount of this in LLVM's header files, this
is not all of the instances I'm afraid. These include all of the
functions that (in my build) are used by a non-static inline (or
external) function. Specifically, these issues were caught by the new
'-Winternal-linkage-in-inline' warning.
I'll try to just clean up the remainder of the clearly redundant "static
inline" cases on functions (not methods!) defined within headers if
I can do so in a reliable way.
There were even several cases of a missing 'inline' altogether, or my
personal favorite "static bool inline". Go figure. ;]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| d01d693c0b337cfcbf524a3a38c8123a6c5fe54e |
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04-Jun-2012 |
Hans Wennborg <hans@hanshq.net> |
Better comments for TLS-related X86 MachineOperand flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| f0234fcbc9be9798c10dedc3e3c134b7afbc6511 |
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01-Jun-2012 |
Hans Wennborg <hans@hanshq.net> |
Implement the local-dynamic TLS model for x86 (PR3985)
This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 228756c744a1f877f7150c8fc91e074ff58c9d66 |
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11-May-2012 |
Hans Wennborg <hans@hanshq.net> |
Implement initial-exec TLS model for 32-bit PIC x86
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 6942f706aad24c45b55d30256250e4ae472b3b07 |
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30-Apr-2012 |
Pete Cooper <peter_cooper@apple.com> |
Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 28a713b20ad17f9a02d4677d8a2fea0edb208418 |
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19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
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18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| d4a19b6a72d19a6f90b676aac37118664b7b7a84 |
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11-Feb-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add support for implicit TLS model used with MS VC runtime.
Patch by Kai Nacke!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 6d1263acb9704b38a8d90fd6ce94f49193cd4dde |
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05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable in X86 Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 5d1a38cbfac62f75ee22cc0c9195616ea5fe5553 |
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30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| ebebe35d1c5ad689caf31cdc4da5b7a9539ffa5c |
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12-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
XOP encoding bits and logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 1b9b377975b3f437acef8c2ba90de582add52f65 |
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25-Nov-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 75485d6746f8b5b23c17cf6d2364e7e1e0705992 |
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23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
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16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 17730847d59c919d97f097d46a3fcba1888e5300 |
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16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
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15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 6744a17dcfb941d9fdd869b9f06e20660e18ff88 |
|
04-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
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| 8c3fee59038d8fd98db2a01b6a309a8941a16a3f |
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25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor X86 target to separate MC code from Target code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
|