| b118a073d7434727a4ea5a5762f54e54e72bef4f |
|
20-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Re-work X86 code generation of atomic ops with spin-loop
- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop
previously the spin-loop looks like
thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB
the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:
thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:
* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.
* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td
* Fix issues in PR13458
- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.
- Revise tests due to the new spin-loop generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 127eea87d666ccc9fe7025f41148c33af0f8c84b |
|
02-Aug-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Add more comments and use early returns to reduce nesting in isLoadFoldable.
Also disable folding for V_SET0 to avoid introducing a const pool entry and
a const pool load.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2d |
|
02-Aug-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
This patch is a rework of r160919 and was tested on clang self-host on my local
machine.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e8b4a4a9d173d67e35e4b1d32e20140381db6bde |
|
29-Jul-2012 |
Manman Ren <mren@apple.com> |
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 0eb3edea9cb6819334173a7d288da85943201fe5 |
|
28-Jul-2012 |
Manman Ren <mren@apple.com> |
X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
rdar://10554090 and rdar://11873276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2af66dc51a7a0f3490c7e89c636e4015431195cd |
|
06-Jul-2012 |
Manman Ren <mren@apple.com> |
X86: peephole optimization to remove cmp instruction
For each Cmp, we check whether there is an earlier Sub which make Cmp
redundant. We handle the case where SUB operates on the same source operands as
Cmp, including the case where the two source operands are swapped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 59bde4d8a1065d3c48c5ea94a570b2c4d2f294a8 |
|
04-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add early if-conversion support to X86.
Implement the TII hooks needed by EarlyIfConversion to create cmov
instructions and estimate their latency.
Early if-conversion is still not enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f318457547ade1ca210386fb69da97f070423998 |
|
23-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Make helper method static since it doesn't use anything in the class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2afde7782dfa56b2e46f79598bdb5f1e09471941 |
|
07-Jun-2012 |
Manman Ren <mren@apple.com> |
Revert r157755.
The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c73ea9102b711d6c2bfd33a86e1c07565c83ffe7 |
|
03-Jun-2012 |
Manman Ren <mren@apple.com> |
Revert r157831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 73c2f7f5ed767a6fc062fd198551be902b7b7d5b |
|
01-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: peephole optimization to remove cmp instruction
This patch will optimize the following:
sub r1, r3
cmp r3, r1 or cmp r1, r3
bge L1
TO
sub r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 241c15ffaa9fbe820d3aa55f17e0b569235691f3 |
|
01-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove a trailing space and fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 91c5346d91973a1d3458a20f8c6b0e899b732e38 |
|
31-May-2012 |
Manman Ren <mren@apple.com> |
X86: replace SUB with CMP if possible
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar: 11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 177cf1e1a3685209ab805f82897902a8d2b61661 |
|
31-May-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c2ecf3efbf375fc82bb1cea6afd7448498f9ae75 |
|
15-Nov-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Break false dependencies before partial register updates.
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.
The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.
The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 92fb79b7a611ab4c1043f04e8acd08f963d073ad |
|
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Expand the x86 V_SET0* pseudos right after register allocation.
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 98e933f9ad3cc2ede3a0a337144a504265d614cd |
|
28-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| cbf479df8abe5e208f1438092a9632a145551cbc |
|
08-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2df3f58a0b3937f2cbd76d3417d2905ca86cf8fa |
|
08-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8c3fee59038d8fd98db2a01b6a309a8941a16a3f |
|
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Refactor X86 target to separate MC code from Target code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1b47720391d7c1917156f52b39c74ff371e1e124 |
|
25-May-2011 |
Francois Pichet <pichet2000@gmail.com> |
Remove unused OpcodeMask enumerator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d9e57c146d3084d7efe2de48dc2cd1f99d4fa656 |
|
25-May-2011 |
Francois Pichet <pichet2000@gmail.com> |
Fix MSVC warning: "is out of range for enum constant"
MSVC doesn't support 64 bit enum.
OpcodeMask is not used anywhere in the code base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c15a91dfc84822037c40ae9d37f63ce1b1a763bb |
|
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Make OpcodeMask an unsigned long long literal to deal with overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
|
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 229e4523f2f12929defa09ac4ef9f3652f21f1ec |
|
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e0ef509aeb47b396cf1bdc170ca4f468f799719f |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8d4a4225135f1f4647e675902359b64cc21af7ef |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 87ca0e077d91b96a765b3b24cadfa8891026a33a |
|
22-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement xgetbv and xsetbv.
Patch by Jai Menon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| cd775ceff0b25a0b026f643a7990c2924bd310a3 |
|
28-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move callee-saved regs spills / reloads to TFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 21d272874b750201272ef3f00441b58932c3d769 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
tidy up, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2312842de0c641107dd04d7e056d02491cc781ca |
|
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 98694138025fdb0cec0cda5727201ad00ded3d63 |
|
19-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 11e8b74a7ae9ecd59b64180a59143e39bc3b9514 |
|
19-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add a hook for target to determine whether an instruction def is
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 45a1cb26a3b92c3c1bec0db9d67449c17b43c8fd |
|
08-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Reduce casting in various tables by defining the table
with the right types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 548abfcbd671b1144bf517b17643259dcae76f4f |
|
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Implement support for the bizarre 3DNow! encoding (which is unlike anything
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 40cc3f8783a4e426a0d439bb2b070b5c072b5947 |
|
17-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8444631 - encoder crash on 'enter'
What a weird instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| beac75da3784929aee9f0357fc5cd76d49d6c3d7 |
|
05-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e943c15621035fa7fbeda7b4922d06a8c2b05b2d |
|
26-Aug-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR7748 without using microsoft extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 59f8a6a66621f7c6f45b838e48fbf210af9d1fb5 |
|
19-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR7465, mishandling of lcall and ljmp: intersegment long
call and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 134d8eec8789184c7a7290ee101ca3d6f62f384a |
|
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 456fdaf0cea4bd195eacc9796fedb71b62290cfe |
|
22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
instead of migrating it to the MC instruction encoder, just
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and
terrible in other ways. Since "GetInstSizeInBytes" is really
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code. I will rip out the
NeedsExactSize hook next.
This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
|
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 87a85c7ef0d1a96c73473de90d3b2b28d24538a5 |
|
13-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
AVX 256-bit conversion instructions
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4ea8771535f16480c40481749397955190787554 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| be95c15903c80b5bc340a9308d1fa334235e23e7 |
|
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
fields to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ac0ed5dc082dff9ce359af5422f5b82047b4fe6b |
|
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 751e1123cecc4b5c2a86849bb39de317b396c303 |
|
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
introduce a new X86II::getMemoryOperandNo method, which
returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 320bdcbfe2691021702085f718db1617b1d4df49 |
|
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement X86InstrInfo::copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9fc05227a2596c545b845ed9a72673995e49d16b |
|
08-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 07de40629f73fb018a2a7f0a5bbd1ee4defe95fd |
|
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX vblendvpd, vblendvps and vpblendvb instructions
Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 6596a6207627ed59f568883924a21e642934c083 |
|
01-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c3d57b179c33ef010ebbff003ce8c5d908cf9c01 |
|
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX MOV{SS,SD}{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
|
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 99405df044f2c584242e711cc9023ec90356da82 |
|
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
|
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
|
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 30ef0e5658b0b8b04437f73f74162d5d72923f29 |
|
03-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Add first pass at darwin tls compiler support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9edf7deb37f0f97664f279040fa15d89f32e23d9 |
|
03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2457f2c66184e978d4ed8fa9e2128effff26cb0b |
|
22-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
|
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ee9eb411fffddbb8fe70418c05946a131889b487 |
|
27-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
on darwin empty functions need to codegen into something of non-zero length,
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 962021bc7f6721c20c7dfe8ca809e2d98b1c554a |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 357be7f28940d45822dae8dfb1502348aa8ae425 |
|
31-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Renumber SSE execution domains for better code size.
SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e4b94b4efb9a4670f25a5a80dd3b97f9583de202 |
|
30-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Basic implementation of SSEDomainFix pass.
Cross-block inference is primitive and wrong, but the pass is working otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 352aa503faee6c58e9cdb5054cc5ec1d90c696b4 |
|
25-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| fe4b92baf11785bf0bfc26b256ca841c9848f77a |
|
24-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."
This reverts commit 99345. It was breaking buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c75c5fa12582956fc6b7d7d756b2bdd49fa61f71 |
|
24-Mar-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| b779033a23c49c2e5e02b15a87bbae42973287b3 |
|
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add encoder support and tests for rdtscp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a599de241041eebc84867ac8e4cb76668cabd236 |
|
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 835acabce13993e210b7cef0020a585125f9cb1e |
|
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
implement infrastructure to support fixups for rip-rel
addressing. This isn't complete because I need an MCContext
to generate new MCExprs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a0331199fc1a6edc5cf0b41d4745c843b82b51e9 |
|
12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
enhance the immediate field encoding to know whether the immediate
is pc relative or not, mark call and branches as pcrel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 0d8db8e0a8492ab2d4bef725ec61b519471b97ec |
|
12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add a bunch of mod/rm encoding types for fixed mod/rm bytes.
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c96f6d606fb243f36046767b7a2c6a0dedffb139 |
|
12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
revert r95949, it turns out that adding new prefixes is not a
great solution for the disassembler, we'll go with "plan b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 239a1edbab18f7f42ea2e4b96efbf8474ccb3640 |
|
12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add another bit of space for new kinds of instruction prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 39a612e6f9e63806af410a0ab0d81895391e4c79 |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
port X86InstrInfo::determineREX over to the new encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 74a2151392a08e202f497ece7a3129663526d431 |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move functions for decoding X86II values into the X86II namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a62fe66f9916079f97d317f7152f1ac428b4f65a |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
constant propagate a method away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a3a0db01217efc6403d90eec2a6ceb919f5031bc |
|
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
change getSizeOfImm and getBaseOpcodeFor to just take
TSFlags directly instead of a TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1e80f403e225a72016581e34b05dca9b5ebd9445 |
|
03-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
enhance new encoder to support prefixes + RawFrm
instructions with no operands. It can now handle
define void @test2() nounwind { ret void }
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 96dc115ef3ee019cb91d7c112358a77536c38a53 |
|
22-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add two target hooks to determine whether two loads are near and should be scheduled together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 7da9ecf9677b751d81515f95168ae3cb2df54160 |
|
13-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2 |
|
12-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified
instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 656e51454ac70f5d500565fd33c883f6dea549f2 |
|
11-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to 3-addressify 16-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 29dbf50b180bb3342af84ff042a3ff06405c5071 |
|
04-Dec-2009 |
David Greene <greened@obbligato.org> |
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
|
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4a66e5bfc2a18a11b64c45b82862fb0f10109a98 |
|
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Based on the testcase for pr3120, running on my MacPro with Xeon processors,
it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d57cdd5683ea926e489067364fb7ffe5fd5d35ee |
|
14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| dda3978d7877d2d60390833c73ed24857295e89c |
|
13-Nov-2009 |
David Greene <greened@obbligato.org> |
Fix a bootstrap failure.
Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands. This uses a heuristic so it isn't reliable for correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| b87bc95db075dae3033a3c541b55b4cb711c332c |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a
machine instruction loads or stores from/to a stack slot. Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand). This helps AsmPrinter determine when
to print a spill/reload comment.
This is only a hint since we may not be able to figure this out in all
cases. As such, it should not be relied upon for correctness.
Implement for X86. Return false by default for other architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 0115e164bad632572e2cfbaf72f0f0882d5319de |
|
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Fix MachineLICM to use the correct virtual register class when
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3731bc026cc6c4fb7deb7ac67e2c3be0c22498be |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Replace X86's CanRematLoadWithDispOperand by calling the target-independent
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 91e69c37153eb7d8cd149d9c2484c3115027b90f |
|
09-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Add basic infrastructure and x86 support for preserving MachineMemOperand
information when unfolding memory references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e33f44cfc547359bc28526e4c5e1852b600b4448 |
|
07-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 01a76ce8d910c0ffee89beaa3819d3448791950f |
|
05-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Remove explicit enum integer values. They don't appear to be needed, and
they make it less convenient to add new entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9cef48eae9a4776ef2f42687072e7c61cb33e10d |
|
11-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.
rdar://7170444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 63476a80404125e5196b6c09113c1d4796da0604 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| b4dc13cab7ef894d3bb17657fa993b9f09af476b |
|
08-Aug-2009 |
Eric Christopher <echristo@apple.com> |
Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 378445303b10b092a898a75131141a8259cff50b |
|
16-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f9b36f08efbc66670910a8a85dd89f03d36196d4 |
|
15-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move load / store folding alignment require into the table(s).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 19a2011194399849ecdf1499c7615e8276a8e68c |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Undo my brain cramp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 49ddb61612725f9910146b2b85565242d91c821e |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
CMOVxx doesn't swap operands which it's commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 7478ab8502a52815413d8b388898f719484ab1a9 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a predicate to determine if a global var reference requires a
PIC-base to be added in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3b6b36d6f54e780a2947cb1b9efe4eed7c40dc11 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
change isGlobalStubReference to take target flags instead of a MachineOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 281bada3b03b97dad0ac9890706a057ab31a5dd3 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a new predicate method that says whether a GlobalValue
MachineOperand is a reference to a stub, not a reference to the
global variable itself. Look no context needed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 75cdf27f48f0b81f778b6aa50efcefa0497a9dae |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move reasoning about darwin $non_lazy_ptr stubs from asmprinter into
isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 74e726e3270c99169cc90fb3c676eeaae273f48c |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make isel decide whether to emit $stub's on darwin instead of asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4aa21aa6d13b8ea00eb0817e53f24e5416ed3038 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move handling of dllimport linkage in isel, not in asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| b903bed0feaa35a2b5e404923db724a62b433787 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Move all the TLS processing logic into isel, don't do it in asmprinter at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 55e7c827301da0e5e03b26835bff259c320b3bf7 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
start adding logic in isel to determine asm printer semantics, step N of M.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ac5e887a6cf0a6182664d8c11beb0d2270272b02 |
|
25-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
Use target-specific machine operand flags to eliminate a gross hack
from the asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 094fad37b90946c91a09eb9270a0dbe800f49d87 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 044b5344c4a97b3c709a05b9c5f9296656477652 |
|
08-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 |
|
07-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| da945e3bb2069c1a7194bcd10579a03ff925a031 |
|
28-Mar-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Have only one definition of X86AddrNumOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
|
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4350eb86a7cdc83fa6a5f4819a7f0534ace5cd58 |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
|
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 653456c351d9bf908ebd982f6ae9df3449c5f34b |
|
07-Jan-2009 |
Dan Gohman <gohman@apple.com> |
X86_COND_C and X86_COND_NC are alternate mnemonics for
X86_COND_B and X86_COND_AE, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
|
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3fafd935607844085a23c012e2a8778fa97206a0 |
|
26-Nov-2008 |
Bill Wendling <isanbard@gmail.com> |
Generate something sensible for an [SU]ADDO op when the overflow/carry flag is
the conditional for the BRCOND statement. For instance, it will generate:
addl %eax, %ecx
jo LOF
instead of
addl %eax, %ecx
; About 10 instructions to compare the signs of LHS, RHS, and sum.
jl LOF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 23066288fdf4867f53f208f9aaf2952b1c049394 |
|
27-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 279c22e6da2612f024b70e5509ffb0cad32f38b2 |
|
21-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 244911bdeece7b45d6b75ea2b5a17f18d9ba6d95 |
|
17-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
getX86RegNum has long been moved to X86RegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ef93cecd80ebdecb0ea2b2c316370998151308e2 |
|
11-Oct-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add ability to override segment (mostly for code emitter purposes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 57c3dac0df7ac1b53ae7c0e5d2adc459fc7bd37c |
|
30-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8b746969baee26237e4c52de9862d06795eabcda |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Move the code for initializing the global base reg out of
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 94a50da93cb9fdc45f3c3ab06f68380b31dd0c1c |
|
30-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Backing out 55521. Not safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4d46d0af583b95a5d4f7d490f542c4fb65b9e824 |
|
29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Swap fp comparison operands and change predicate to allow load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
|
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
|
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f660c171c838793b87b7e58e91609cecf256378d |
|
03-Jul-2008 |
Owen Anderson <resistor@mac.com> |
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1c4b5eaa4628935c4db3e422aa10f2031e6d1679 |
|
28-Jun-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make intel asmprinter child of generic asmprinter, not x86 shared asm printer. This leads to some code duplication, which will be resolved later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
|
16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
|
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9f8fea3531f8f8d04d1e183ff570be37d41d13f5 |
|
12-May-2008 |
Bill Wendling <isanbard@gmail.com> |
Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
|
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
|
31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 950a4c40b823cd4f09dc71be635229246dfd6cac |
|
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 6634e26aa11b0e2eabde8b3b463bb943364f8d9d |
|
13-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1fab4a6bbb6eb5d44d35c8aade2493143b44d288 |
|
11-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Recommitting parts of r48130. These do not appear to cause the observed failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4499e495eabe8de7d595416a03c56af4688df507 |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3feb0170a8d65984ce5c01a85e7dfd4005f8bb35 |
|
10-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ea7da50e5a7f291295c10d91fc3fdba76d339579 |
|
01-Mar-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
|
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a22edc82cab86be4cb8876da1e6e78f82bb47a3e |
|
11-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| cc8cd0cbf12c12916d4b38ef0de5be5501c8270e |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d94b6a16fec7d5021e3922b0e34f9ddb268d54b1 |
|
05-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more functionality from MRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3100afaf3f2f3b0224fc03038062fc57f1a9a796 |
|
02-Jan-2008 |
Bill Wendling <isanbard@gmail.com> |
Machine LICM will check that operands are defined outside of the loop. Also
check that register isn't 0 before going further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
|
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 641055225092833197efe8e5bce01d50bcf1daae |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
|
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 6259d51c91d7da9bf16114849236b5bdfa85f35e |
|
30-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
If we have a load of a global address that's not modified during the
function, then go ahead and hoist it out of the loop. This is the result:
$ cat a.c
volatile int G;
int A(int N) {
for (; N > 0; --N)
G++;
}
$ llc -o - -relocation-model=pic
_A:
...
LBB1_2: # bb
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
incl (%esi)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...
$ llc -o - -relocation-model=pic -machine-licm
_A:
...
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
incl (%eax)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...
I'm limiting this to the MOV32rm x86 instruction for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 627c00b663f881600b4af1ae135af6ee2cb19c1a |
|
18-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 041b3f835682588cb63df7e609d726369dd6b7d3 |
|
09-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Reverting 44702. It wasn't correct to rename them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 320c630c1b55e17fa00249d499f974cb1a4238f8 |
|
08-Dec-2007 |
Bill Wendling <isanbard@gmail.com> |
Renaming:
isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ee465749313579ccd91575ca8acf70b75c221a2c |
|
29-Aug-2007 |
Duncan Sands <baldrick@free.fr> |
Move getX86RegNum into X86RegisterInfo and use it
in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d45eddd214061bf12ad1e6b86497a41725e61d75 |
|
26-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 82a87a01723c095176c6940bcc63d3a7c8007b4b |
|
19-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 318093b6f8d21ac8eab34573b0526984895fe941 |
|
15-Jun-2007 |
Dale Johannesen <dalej@apple.com> |
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c101e95cb6aae1fd6a0727ba4b518a7894ae3089 |
|
14-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 6ae3626a4fda14e6250ac8d8ff487efb8952cdf7 |
|
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| bb1ee05253d965e0944351a21e9970c02b1aebfe |
|
11-Apr-2007 |
Bill Wendling <isanbard@gmail.com> |
Add support for our first SSSE3 instruction "pmulhrsw".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 19f2ffce4598c4c70f32eed7c6740b43185200b1 |
|
05-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ba59a1e453e110f7b84233f07613f9c5d9a39b87 |
|
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c24ff8ed12d01a1b1d2fac57876fc7580024ec49 |
|
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
add another target hook for branch folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9cd68759178f9fe25c72253d338e78e414f1d770 |
|
21-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement support for branch condition reversal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 7fbe9723e32ff35c4ad765c88209ef9321475a1b |
|
20-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
Implement branch analysis/xform hooks required by the branch folding pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ae1dc403274d3a64bcee31f15e2d25e4b7178811 |
|
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d77ddbc0ba4614f4c9ef548e82ba6bc68c586cb5 |
|
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
remove some dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| aa3c1410b427909da350f2b5e8d4ec3db62a3618 |
|
30-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fix a build breaker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 751458dac9fec1c9436065a6e1ea0dd0a9cf3ec3 |
|
18-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
ImmMask should be 3 for a two-bit field; Compact X86II
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 408396014742a05cad1c91949d2226169e3f9d80 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3c55c54a877b3e5a79053df8f6080f505c9d1ff4 |
|
01-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
- Use xor to clear integer registers (set R, 0).
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9eb59ec548b861d6ede05b4e6dc22aabf645e665 |
|
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f63be7d3959939b2ffaf0bba5519b71216ec9ee6 |
|
06-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 0e0a7a45d3d0a8c865a078459d2e1c6d8967a100 |
|
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
* Remove trailing whitespace
* Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 41e431ba045eb317ebf0ec45b563a5d96c212f5c |
|
19-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| bcea4d6f283a5ae6f93dc8e10898311fe53d23a3 |
|
02-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Implement the convertToThreeAddress method, add support for inverting JP/JNP
branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19247 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| c96bb817aa6a1539b4ea4e167ef994058345d8a5 |
|
11-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Remove a bunch of ad-hoc target-specific flags that were only used by the
old asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| a35ce87e2e7647e401d6535ef34adaf20da5ba72 |
|
01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Eliminate 3 of the X86 printImplicit* flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 36f506eddb25d5198240a1e3fabcb0912111c7ee |
|
31-Jul-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Implement insertGoto and reverseBranchCondition for the X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| ab8deccb82460527562d1c36a787537e4edaa9dd |
|
11-Jun-2004 |
Chris Lattner <sabre@nondot.org> |
Introduce a new FP instruction type to separate the compare cases from the
twoarg cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 266538350a1a478b5fe053bfda42c0d03e371570 |
|
13-Apr-2004 |
Chris Lattner <sabre@nondot.org> |
Add support for the printImplicitDefsBefore flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4ffff9e2fa97a99d6e7de84bcb0866f70d330260 |
|
08-Apr-2004 |
John Criswell <criswell@uiuc.edu> |
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| f1ac50ec53889a4cf16ddc80907edc54119360d0 |
|
01-Apr-2004 |
Chris Lattner <sabre@nondot.org> |
Wrap at 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1c54a8544788156d6864430182a3a79b8839b7da |
|
01-Apr-2004 |
Chris Lattner <sabre@nondot.org> |
Add FP conditional move instructions, which annoyingly have special properties
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1ddf475b6a3d748427546ab8f65a712c8eea3a0f |
|
29-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
These two virtual methods are never called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 5ab29b504d49d3fa84d76f79e73704260f900682 |
|
28-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Each instruction now has both an ImmType and a MemType. This describes
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 169584ed45f62f91599bed3d019640e168d815ea |
|
27-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 915e5e56d7cc8e140d33202eed6244ed0356ed1f |
|
12-Feb-2004 |
Chris Lattner <sabre@nondot.org> |
Add support for the rep movs[bwd] instructions, and emit them when code
generating the llvm.memcpy intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 79b13735adcc034a6869f1fd5670051c6dd0a28a |
|
30-Jan-2004 |
Chris Lattner <sabre@nondot.org> |
Add a new flag, which is only used for symmetry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 5e30002af70ef09a42cac155d9196f7f0f3b1695 |
|
28-Dec-2003 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Add TargetInstrInfo::isMoveInstr() to support coalescing in register
allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 1e60a9165dc4d6ce5650dacc026f2942696af920 |
|
20-Dec-2003 |
Chris Lattner <sabre@nondot.org> |
Rip JIT specific stuff out of TargetMachine, as per PR176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d0fde30ce850b78371fd1386338350591f9ff494 |
|
11-Nov-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Put all LLVM code into the llvm namespace, as per bug 109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 856ba76200ec2302f2fe500bc507f426c7d566c8 |
|
21-Oct-2003 |
John Criswell <criswell@uiuc.edu> |
Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 2959b6ec49be09096cf0a5e7504d2a1ec15ef2b3 |
|
06-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Completely eliminate the isVoid TSFlag, shifting over all other fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 4d18d5ce1e62779e7736ca0811e2e1cb06e4ea36 |
|
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Lump the base opcode in with the X86 TargetSpecific flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| d7908f679eeadc108e09e2aca5faba0b5410ea4a |
|
27-Jun-2003 |
Brian Gaeke <gaeke@uiuc.edu> |
Nice tasty llc fixes. These should fix LLC for x86 for everything in
SingleSource except oopack and Oscar. (Sorry, Oscar.)
include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add
accessors for ImplicitUses/Defs.
lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you
really wanted this, just use MI->print(O, TM); instead...
lib/Target/X86:
FloatingPoint.cpp: ...like this.
X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses
target-specific flag bit.
X86InstrInfo.def: Add the PrintImplUses flag to all the instructions
which implicitly use CL, because the assembler needs to see the CL in
order to generate the right instruction.
Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName
to name constants in the constant pool for each function instead. This
avoids keeping state between runOnMachineFunction() invocations, which
is a no-no. Having MangledGlobals be global is a bogon I'd like to get
rid of too, but making it a static member of Printer causes link errors
(why???).
Make NumberForBB into a member of Printer instead of a global, too.
Make printOp and printMemReference into methods of Printer.
X86InstrInfo::print is now Printer::printMachineInstruction, because
TargetInstrInfo::print is history. (Because of this, we have to qualify
the names of some TargetInstrInfo methods we call.)
Print out the ImplicitUses field of any instruction we print that has
the PrintImplUses bit set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 12745c55e1d5a6e76d41684f1b507ea7c6b888ac |
|
24-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Reword to remove reference to how things worked in the past.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| e9d883828ad92f3a1d06e3c9e98c4e3df937197d |
|
24-May-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 3501feab811c86c9659248a4875fc31a3165f84d |
|
14-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 0c514f4e2711ab57bf75f26806f7b8584dfbee6f |
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13-Jan-2003 |
Chris Lattner <sabre@nondot.org> |
* Some instructions take 64 bit integers, add an Arg type for it
* Add flags for different types of FP pseudo instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 0ef73f3e2975d240cb6a7fa62c438e7c928df043 |
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28-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
* Remove implementations of previously pure virtual functions that are not any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 4c299f5da1013cd36563a82f188c731b2758074d |
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25-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Add FP instr prefix byte support
Add Pseudo instr class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| a0f38c867cea507401dab03076dd5ace69f65edd |
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13-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Rename MemArg* to Arg*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 86764d778e833a314dcca5b9694ba42fa2476d66 |
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05-Dec-2002 |
Brian Gaeke <gaeke@uiuc.edu> |
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 4aff92860d495907dbb04d1e8c088ed92eb4101d |
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02-Dec-2002 |
Chris Lattner <sabre@nondot.org> |
Eliminate OtherFrm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 15207f45db9d95105ea4b17e2fb7d0c516a21ac6 |
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21-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Add fixme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 85b39f229f3146e57d059f1c774400e4bde23987 |
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21-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Add support for /0 /1, etc type instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 11e53e3c384e9e25f53a0aec3acf0a725efafeab |
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21-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Add new prefix flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| f21dfcddcf199444440004bfa74bb222e2d3ce9e |
|
18-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Expose base opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 6aab9cf65cd1e96f9d0fa99f8453da454648bba1 |
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18-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Start to add more information to instr.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 239dcfd215b47cab1f82822afa7fbae402ea2c79 |
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18-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Add instruction annotation about whether it has a 0x0F opcode prefix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 927dd095c435788655d7fe2a16f26efe65355fd2 |
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18-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Arrange to have a TargetMachine available in X86InstrInfo::print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| dbb61c6445513f5cfd057c74da9e5c8299353c68 |
|
17-Nov-2002 |
Chris Lattner <sabre@nondot.org> |
Reorganize printing interface a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9d17740295838f94120646ef619b2e187f2d71bd |
|
30-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Add flag to specify when no value is produced by an instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 055c965bff7c8567e7fae90ffe1e10e109856064 |
|
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Rename X86InstructionInfo to X86InstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 33f53b554acfff0b15f08d551fce5b0701b443c0 |
|
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Minor renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|
| 9bbf439e388c1d015558815fc47a56919de5ae3b |
|
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Implement MachineInstrInfo interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 75276f150e081464300810c58934abcc9c4b9f53 |
|
29-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Initial stab at MachineInstr'ication
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
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| 726140821f96e3472a8eccef0c67c0b5ad65a1d9 |
|
26-Oct-2002 |
Chris Lattner <sabre@nondot.org> |
Initial checkin of X86 backend.
We can instruction select exactly one instruction 'ret void'. Wow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86InstrInfo.h
|