History log of /external/llvm/utils/TableGen/CodeGenRegisters.h
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
26369a930c523b75fe8f4ba18456ff86f68d5612 17-Mar-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Use ArrayRef<MVT::SimpleValueType> when possible.

Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
eca1fcf3d2d8246c45648fea59bd21a4091f9115 05-Dec-2012 Andrew Trick <atrick@apple.com> RegisterPressure API. Add support for physical register units.

At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).

Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
4ffd89fa4d2788611187d1a534d2ed46adf1702c 04-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Sort the #include lines for utils/...

I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
94c22716d60ff5edf6a98a3c67e0faa001be1142 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7e2c793a2b5c746344652b6579e958ee42fafdcc 27-Sep-2012 Sylvestre Ledru <sylvestre@debian.org> Fix a typo 'iff' => 'if'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
d2c699706ceae4a118a8dcafbef73b85093e5390 12-Sep-2012 Owen Anderson <resistor@mac.com> Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
a6035773d8d29827a124e65c258adbf0dcbb1a5a 11-Sep-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TRI::getSubRegIndexLaneMask().

Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
de0250728b1a9e69ca593168f1ea2ecef8e9bf95 11-Sep-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Clean the sub-reg index composition maps at emission.

Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
c97eda2c9e34f4c491f59bbac81af2fd63fef49d 15-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Make synthesized sub-register indexes available in the target namespace.

TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.

Also take this opportunity to stop creating new Record objects for
synthetic indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
dee3be60292ecfafe584baf4ed84b634b8f4c7c7 30-May-2012 Benjamin Kramer <benny.kra@googlemail.com> Remove little semicolon that caused a lot of warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
f52baf72c116d9cf8680d25a8e751ce354c7d44b 30-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit register unit lists for each register.

Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.

The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.

Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
a9fdbbc55f640fecd3bb8df12fd205694c2f71a2 22-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Also compute TopoSigs in synthetic register classes.

CodeGenRegisterClass has two constructors. Both need to compute the
TopoSigs BitVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
3778aeb74864390bf763424c45cc355ac330fbc9 17-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Use RegUnits to compute overlapping registers.

TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.

This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
40c6fb397d1e485aef8b4e1729ba9804784990c1 15-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Create a struct representing register units in TableGen.

Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
31d938a6b1173c642f975d78417459d4d8cd3677 14-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Record the ad hoc aliasing graph in CodeGenRegister.

The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.

Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
b81cbc271faed9fa633920436cd7ae49750a9a42 14-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute topological signatures of registers.

TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.

This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.

TopoSigs are not currently exposed outside TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
79e2045531cb4d1978be42591e9254c38a463d30 11-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Defer computation of SuperRegs.

Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
fcad79671f22c8994663c6780862b9c38d3609c3 11-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute secondary sub-registers.

The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
148f392195dec8772ab4c5ac0d0c3b85fba0e5f8 10-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Precompute lists of explicit sub-registers and indices.

The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
ca313e1efa98910a7a5e7f4bf2ac1a70adb6e4fe 10-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute a backwards SubReg -> SubRegIndex map for each register.

This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
da2be824346c316c6fc840de7b8493e3d587e785 10-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Rename getSubRegs() to computeSubRegs().

That's what it does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7855ec62c3b6b5b7e6d3fada589511abd964fdb3 04-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove TargetRegisterClass::SuperRegClasses.

This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
ec14cd7ddc66d47cd7927f18d8c11844c400367e 11-Apr-2012 Andrew Trick <atrick@apple.com> TableGen's regpressure: emit per-registerclass weight limits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
176194d4ee2774bc135ababc5bd6c6c9f606b2a5 10-Apr-2012 Andrew Trick <atrick@apple.com> Added register unit sets to the target description.

This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
d35ac3c8bc37ab383b10a04b9c8b1087d6b2bc45 10-Apr-2012 Andrew Trick <atrick@apple.com> Added register unit weights to the target description.

This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
aec111a06b595742683b529a7f4391becd7e24ec 10-Apr-2012 Andrew Trick <atrick@apple.com> Fix header comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
dd9a50196cd75dbcb2bd604754cd62f8c1f30357 31-Mar-2012 Andrew Trick <atrick@apple.com> Introduce Register Units: Give each leaf register a number.

First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd 29-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add more constness to CodeGenRegisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
655b8de7b2ab773a977e0c524307e71354d8af29 05-Feb-2012 Craig Topper <craig.topper@gmail.com> Convert assert(0) to llvm_unreachable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
b5af2d943ed568f2f4cac545b6dfb150ae9d73aa 02-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Specify SubRegIndex components on the index itself.

It is simpler to define a composite index directly:

def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

CompositeIndices = [(ssub_2 dsub_1, ssub_0),
(ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
90498b195ba759cf4f2a98da4e46fb9a2b580396 31-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Move the composite map into CodeGenSubRegIndex.

Each SubRegIndex keeps track of how it composes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
5fcc156344e0d38fa5f5eab3d9193b859b27b45e 31-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a TableGen CodeGenSubRegIndex class.

This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
31867660cb81ea2b1d1a6ffa7d09c91acb754a8b 18-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a CoveredBySubRegs property to Register descriptions.

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
ec572539dd5660f9ca42027ac04df3a3f8c0cab1 17-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TableGen support for callee saved registers.

Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
570f9a972e02830d1ca223743dd6b4cc4fdf9549 19-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit a getMatchingSuperRegClass() implementation for every target.

Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
a9f65b9a1f57dcf546399ac32bf89d71d20df5b9 19-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Synthesize register classes for TRI::getMatchingSuperRegClass().

Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.

This produces these new register classes:

ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX

The other targets in the tree are not weird enough to be affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
fec33444c5ca22e0338fdac0fcaee2644bd756af 16-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Extract a method. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7e56831a6804812b2295c5446a05f4ec457b6b3e 15-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Synthesize missing register class intersections.

The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR

X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX

Other targets are unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
1b3d218880a7147caeb58f2604af1df26a409f7d 12-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Extract a method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
830378f6628ad3af1d0293a0b605065532f99e43 11-Oct-2011 Eli Friedman <eli.friedman@gmail.com> Remove extra semicolon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
845d2c0c776abce551d16f7b1b7dc1f4d4df1a27 05-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TRI::getSubClassWithSubReg(RC, Idx) function.

This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
babf0569e2e4f204f9a304416cc4acc349d8f836 04-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Teach TableGen to infer missing register classes.

The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
cc0c975b7db95ce6bc865c56a3016bf0d4f83304 04-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> TableGen: Store all allocation orders together.

There is no need to keep the primary order separate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
6fea31e7300fe012b0b2984d6bc0338d02b054d3 04-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> TableGen: Privatize CodeGenRegisterClass::TheDef and Name.

When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7c788888872233748da10a8177a9a1eb176c1bc8 01-Oct-2011 Peter Collingbourne <peter@pcc.me.uk> Move TableGen's parser and entry point into a library

This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
52e7dfadc65257f05480de6e70da00373a8954d1 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().

All the sub-class bit vectors are computed when first creating the
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
f9a4bb78dadc12c7c1e604c6f17b63a71305c2ca 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute lists of super-classes in CodeGenRegisterClass.

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

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/external/llvm/utils/TableGen/CodeGenRegisters.h
203e0b17dd6049d64cb4ed7c4da09747204e6463 30-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Precompute a bit vector of register sub-classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7dcaa5b0fb56468e774044d3b887c21b2d484a1c 30-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Order register classes topologically.

All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
29f018cee616e4082e5005bc9adee4dc777e621c 30-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Switch to ArrayRef<CodeGenRegisterClass*>.

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
abdbc84b4ed4276ed3def50f554e3ba156325717 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Store CodeGenRegisters as pointers so they won't be reallocated.

Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
54c47c1ce94b9e549ef768e80fd004788d13ce85 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove MethodProtos/MethodBodies and allocation_order_begin/end.

Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
b4c704877d1600852a55ab7bef2918a7c0af5e0d 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Provide AltOrders for specifying alternative allocation orders.

A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
59f26aadce1bb985b9befe841fc106c891e1c728 15-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Use a SetTheory instance to expand register lists in register classes.

This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
ae1920b1efa72c1789d562df4746110d0c2e10bd 15-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Give CodeGenRegisterClass a real sorted member set.

Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
7b9cafde5e3faec22bbfbbc90cca0876968abad9 15-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Move the list of register classes into CodeGenRegBank as well.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
026dc223aeef2579d63f395007491e37d6cde3a0 12-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute lists of sub-regs, super-regs, and overlapping regs.

Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
b5923db192d2aa938ff3c12aaac87d80ab649625 11-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Move the list of registers into CodeGenRegBank.

Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
dc29c447136aabf05f48a7119e48065c3b4cee9b 10-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Move some sub-register index calculations to CodeGenRegisters.cpp

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
f462e3fac7ac67503657d63dc35330d0b19359b3 03-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
69ba413057fe5d73d95e7b51ddfe16a8b0def23c 21-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't allow per-register spill size and alignment.

These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 20-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Prefer cheap registers for busy live ranges.

On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
17fad045cccf34822d3163ada9e70a8f4528746e 11-Mar-2011 Jim Grosbach <grosbach@apple.com> Make the register enum value part of the CodeGenRegister struct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
5d4314ef720630e6547fe41efec1608d4c14c78e 11-Mar-2011 Jim Grosbach <grosbach@apple.com> Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
90fd797dc739319347861d4f3984bc8952ae9a29 06-Nov-2010 Chris Lattner <sabre@nondot.org> add (and document) the ability for alias results to have
fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
a2c9188560eb9a7d494960fefd28cf0998d9a78f 25-Aug-2010 Eric Christopher <echristo@apple.com> Split out register class subclassing to a separate function and clean up
accordingly. No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
09bc0298650c76db1a06e20ca84c1dcb34071600 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
825b72b0571821bf2d378749f69d6c4cfb52d2f9 11-Aug-2009 Owen Anderson <resistor@mac.com> Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
e50ed30282bb5b4a9ed952580523f2dda16215ac 11-Aug-2009 Owen Anderson <resistor@mac.com> Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb 06-Jun-2008 Duncan Sands <baldrick@free.fr> Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


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/external/llvm/utils/TableGen/CodeGenRegisters.h
ae9f3a3b7c915f725aef5a7250e88eaeddda03c6 20-Feb-2008 Anton Korobeynikov <asl@math.spbu.ru> Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.


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/external/llvm/utils/TableGen/CodeGenRegisters.h
3060910e290949a9ac5eda8726d030790c4d60ff 29-Dec-2007 Chris Lattner <sabre@nondot.org> remove attributions from utils.


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/external/llvm/utils/TableGen/CodeGenRegisters.h
a3ca3149f2b59c512c50aab330b5a0d8efddeffa 19-Sep-2007 Evan Cheng <evan.cheng@apple.com> Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.


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/external/llvm/utils/TableGen/CodeGenRegisters.h
cb648f90a26eb05ae8d508d500ca12881df50824 14-Sep-2007 Dan Gohman <gohman@apple.com> Remove spurious consts. This fixes warnings with compilers that
are strict about such things.


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/external/llvm/utils/TableGen/CodeGenRegisters.h
a321125e8b7e50d427d86b8053de2e6793b5df5b 14-Jun-2007 Christopher Lamb <christopher.lamb@gmail.com> Add support to tablegen for specifying subregister classes on a per register class basis.


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/external/llvm/utils/TableGen/CodeGenRegisters.h
b73628b5abee86ef76e1ed8c7f9eaed85bea61a8 30-Dec-2005 Nate Begeman <natebegeman@mac.com> Add support for generating v4i32 altivec code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
5c4736a3da04795ba8d04e152e151afd6942e2f1 05-Dec-2005 Chris Lattner <sabre@nondot.org> Add some methods


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
6510b22cec7de4f0acc9965ec24c3668a6a8a87e 01-Dec-2005 Nate Begeman <natebegeman@mac.com> Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
e9f4ba8dd47de9da2a98db3bbe25b54d5a9607f1 08-Sep-2005 Chris Lattner <sabre@nondot.org> Compute the value types that are natively supported by a target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
ac46893e246748876d1155bb0c9e8892e52acab7 19-Aug-2005 Chris Lattner <sabre@nondot.org> Split register class "Methods" into MethodProtos and MethodBodies


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
c67c18fd2378fd2394c42f12b67897e7eba02d5c 19-Aug-2005 Chris Lattner <sabre@nondot.org> Read the namespace field from register classes


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/external/llvm/utils/TableGen/CodeGenRegisters.h
3da94aec4d429b2ba0f65fa040c33650cade196b 22-Apr-2005 Misha Brukman <brukman+llvm@gmail.com> Remove trailing whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
57677755055be6c95289fbe7a2a1edd88ac39818 21-Aug-2004 Chris Lattner <sabre@nondot.org> Support "Methods" in register classes in CodgeGenRegisterClass


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
056afeface2ac98664ed8fa4799b46178a4a6fe3 21-Aug-2004 Chris Lattner <sabre@nondot.org> Start parsing register classes into a more structured form


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/external/llvm/utils/TableGen/CodeGenRegisters.h
7a680c60646fb3b06085f1fe6a7a1917c35010c6 21-Aug-2004 Chris Lattner <sabre@nondot.org> Read in declared reg sizes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenRegisters.h
8dab6ca9c638709e7b60b942107ab88b3ef7d06d 16-Aug-2004 Chris Lattner <sabre@nondot.org> Add initial support for register and register class representation.
Obviously this is not done.


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/external/llvm/utils/TableGen/CodeGenRegisters.h