| 02fec34de127d23987352b90bf095ad3fac75fb9 |
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18-Mar-2013 |
Andrew Trick <atrick@apple.com> |
TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 1ab961f6d3cdd284f5d6c696f3e26eb3627e2c8b |
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16-Mar-2013 |
Andrew Trick <atrick@apple.com> |
Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.
Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 64110ffc9eecbe999c29ac9d9f6697447a110036 |
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15-Mar-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:
let SchedRW = ... in {
...
}
Which is now possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 1754aca83af1658c832706889c0e2933f8dfa8ee |
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14-Mar-2013 |
Andrew Trick <atrick@apple.com> |
MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.
This allows SandyBridge to be expressed naturally, which will be
checked in shortly.
def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| d9a4f0cbd28351155a7d9bd62aa08d8394435f82 |
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01-Feb-2013 |
Andrew Trick <atrick@apple.com> |
MachineModel: Inconsequential TableGen SubtargetEmitter fix.
Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 4ffd89fa4d2788611187d1a534d2ed46adf1702c |
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04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 322ff8834532915a4de0210a083672008d6499b6 |
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02-Nov-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix a build problem with xlc. The error message was
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+".
"../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate.
Patch by Kai.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 61131ab15fd593a2e295d79fe2714e7bc21f2ec8 |
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25-Oct-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 2c6d71388fb1b68ce6fdbb88642a95a24b27b2a7 |
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25-Oct-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Don't use stack unwinding to provide the location information for
SetTheory, but pass down the location explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 6cfc806a6b82b60a3e923b6b89f2b4da62cdb50b |
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10-Oct-2012 |
Sean Silva <silvas@purdue.edu> |
tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.
There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| dbe6d43dfac78d567973dac8fc2a0190dad5135f |
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10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter cleanup.
Consistently evaluate Aliases and Sequences recursively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 13745262a8db98d6c4513ff9934db4be75a8b26c |
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04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 2062b1260fa9df3e69e7b4d24a657a0ebb7f8710 |
|
04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| fe05d98c253676d1ae6e0f03efde6b75fdae105d |
|
04-Oct-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup TableGen subtarget emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 92649883119aaa8edd9ccf612eaaff5ccc8fcc77 |
|
22-Sep-2012 |
Andrew Trick <atrick@apple.com> |
Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
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| 3b8fb648c6e1c519b7e0f487f4fb511744869d35 |
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19-Sep-2012 |
Andrew Trick <atrick@apple.com> |
SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|
| bc4ff6e3cf129294d10c2366cb157796964c903e |
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18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser: Add getProcResourcesIdx().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|
| 3cbd1786ac06fe751dc4b5ad55e75115cb1d51ce |
|
15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|
| 5e613c260bb3044eb059dea74cd6bccfa9b85bdd |
|
15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Infer SchedClasses from variants defined by the target or subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|
| 48605c340614fc1fb2ae1d975fc565a4188182e0 |
|
15-Sep-2012 |
Andrew Trick <atrick@apple.com> |
TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|
| 2661b411ccc81b1fe19194d3f43b2630cbef3f28 |
|
07-Jul-2012 |
Andrew Trick <atrick@apple.com> |
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/CodeGenSchedule.cpp
|