Cross Reference: /external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines Matching defs:Ins
1849                                           &Ins,
1855       return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1858       return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1861     return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1871                                         &Ins,
1922   CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1983   CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2131                                         &Ins,
2176   for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2179     EVT ObjectVT = Ins[ArgNo].VT;
2182     ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2183     std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2184     CurArgIdx = Ins[ArgNo].OrigArgIndex;
2200       MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2420                                         &Ins,
2473     for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2475       EVT ObjectVT = Ins[ArgNo].VT;
2476       ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2519   // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2523   for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2526     EVT ObjectVT = Ins[ArgNo].VT;
2529     ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2544       MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2858                                       const SmallVectorImpl<ISD::InputArg> &Ins,
2871     for (unsigned i = 0; i != Ins.size(); i++) {
2872        ISD::ArgFlagsTy Flags = Ins[i].Flags;
3278                                    const SmallVectorImpl<ISD::InputArg> &Ins,
3285   CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3330                               const SmallVectorImpl<ISD::InputArg> &Ins,
3410   if (!Ins.empty())
3414                          Ins, dl, DAG, InVals);
3424   SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
3433                                                    Ins, DAG);
3438                               isTailCall, Outs, OutVals, Ins,
3442                               isTailCall, Outs, OutVals, Ins,
3447                           isTailCall, Outs, OutVals, Ins,
3457                                     const SmallVectorImpl<ISD::InputArg> &Ins,
3661                     Ins, InVals);
3689                                     const SmallVectorImpl<ISD::InputArg> &Ins,
4051                     Ins, InVals);
4060                                     const SmallVectorImpl<ISD::InputArg> &Ins,
4399                     Ins, InVals);