Searched defs:Mask (Results 51 - 75 of 79) sorted by relevance

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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp373 APInt Mask = APInt::getHighBitsSet(OrigBitWidth, OrigBitWidth-BitWidth); local
374 if (MaskedValueIsZero(I->getOperand(0), Mask) &&
375 MaskedValueIsZero(I->getOperand(1), Mask)) {
612 // Mask off any bits that are set and won't be shifted away.
H A DInstCombineCompares.cpp1008 Constant *Mask = ConstantInt::get(ICI.getContext(), Val); local
1011 Mask, Shr->getName()+".mask");
1310 Constant *Mask = local
1315 Builder->CreateAnd(LHSI->getOperand(0),Mask, LHSI->getName()+".mask");
1326 Constant *Mask = ConstantInt::get(LHSI->getOperand(0)->getType(), local
1330 Builder->CreateAnd(LHSI->getOperand(0), Mask, LHSI->getName()+".mask");
2504 // a * Cst icmp eq/ne b * Cst --> a & Mask icmp b & Mask
2505 // Mask = -1 >> count-trailing-zeros(Cst).
2508 ConstantInt *Mask local
2667 Value *Mask = Builder->CreateAnd(A, Builder->getInt(MaskV)); local
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/external/v8/src/
H A Dhydrogen-instructions.cc119 int32_t Range::Mask() const { function in class:v8::internal::Range
1362 ? left()->range()->Mask()
1365 ? right()->range()->Mask()
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1123 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1125 const int *Mask; member in class:llvm::SDNode::ShuffleVectorSDNode
1130 : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
1137 return makeArrayRef(Mask, VT.getVectorNumElements());
1141 return Mask[Idx];
1144 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1149 if (Mask[i] != -1)
1150 return Mask[i];
1154 static bool isSplatMask(const int *Mask, EVT VT);
/external/llvm/include/llvm/IR/
H A DIRBuilder.h1317 Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask, argument
1321 if (Constant *MC = dyn_cast<Constant>(Mask))
1323 return Insert(new ShuffleVectorInst(V1, V2, Mask), Name);
H A DInstructions.h1663 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
1666 ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
1672 const Value *Mask);
1690 static int getMaskValue(Constant *Mask, unsigned i);
1698 static void getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result);
1705 SmallVector<int, 16> Mask; local
1706 getShuffleMask(Mask);
1707 return Mask;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp491 SDValue Mask = N->getOperand(0); local
495 Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy));
499 LHS.getValueType(), Mask, LHS, RHS);
1384 // Mask out the high bit, which we know is set.
H A DLegalizeVectorTypes.cpp1094 SDValue Mask = N->getOperand(0); local
1098 EVT MaskVT = Mask.getValueType();
1129 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero);
1131 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts);
H A DSelectionDAG.cpp1303 SDValue N2, const int *Mask) {
1314 // Validate that all indices in Mask are within the range of the elements
1319 assert(Mask[i] < (int)(NElts * 2) && "Index out of range");
1320 MaskVec.push_back(Mask[i]);
1666 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
1667 /// this predicate to simplify operations downstream. Mask is known to be zero
1669 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, argument
1674 return (KnownZero & Mask) == Mask;
1677 /// ComputeMaskedBits - Determine which of the bits specified in Mask ar
1302 getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, const int *Mask) argument
2318 APInt Mask; local
6326 isSplatMask(const int *Mask, EVT VT) argument
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H A DSelectionDAGBuilder.cpp1758 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1809 unsigned PopCount = CountPopulation_64(B.Mask);
1816 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1823 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1832 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
2446 CasesBits[i].Mask |= 1ULL << j;
2463 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2469 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2873 // Utility for visitShuffleVector - Return true if every element in Mask,
2876 isSequentialInRange(const SmallVectorImpl<int> &Mask, unsigned Pos, unsigned Size, int Low) argument
2888 SmallVector<int, 8> Mask; local
2889 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); local
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/external/llvm/lib/IR/
H A DInstructions.cpp1528 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument
1532 cast<VectorType>(Mask->getType())->getNumElements()),
1537 assert(isValidOperands(V1, V2, Mask) &&
1541 Op<2>() = Mask;
1545 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument
1549 cast<VectorType>(Mask->getType())->getNumElements()),
1554 assert(isValidOperands(V1, V2, Mask) &&
1559 Op<2>() = Mask;
1564 const Value *Mask) {
1569 // Mask mus
1563 isValidOperands(const Value *V1, const Value *V2, const Value *Mask) argument
1614 getMaskValue(Constant *Mask, unsigned i) argument
1626 getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result) argument
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H A DCore.cpp2301 LLVMValueRef V2, LLVMValueRef Mask,
2304 unwrap(Mask), Name));
2300 LLVMBuildShuffleVector(LLVMBuilderRef B, LLVMValueRef V1, LLVMValueRef V2, LLVMValueRef Mask, const char *Name) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1309 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); local
1310 assert(Mask && "Missing call preserved mask for calling convention");
1311 Ops.push_back(DAG.getRegisterMask(Mask));
1951 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask(); local
1959 Ops.push_back(DAG.getRegisterMask(Mask));
2458 SDValue &MaskedVal, uint64_t Mask) {
2459 if (!isShiftedMask_64(Mask))
2473 uint64_t LSB = CountTrailingZeros_64(Mask);
2501 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask, argument
2510 Mask
2457 getLSBForBFI(SelectionDAG &DAG, DebugLoc DL, EVT VT, SDValue &MaskedVal, uint64_t Mask) argument
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/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp63 // instructions that for the IT block. Firstcond and Mask correspond to the
65 void setITState(char Firstcond, char Mask) { argument
68 unsigned NumTZ = CountTrailingZeros_32(Mask);
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
796 unsigned Mask = MI.getOperand(1).getImm(); local
797 ITBlock.setITState(Firstcond, Mask);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1880 unsigned Mask = 1; local
1882 if (ErrorInfo & Mask) {
1884 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1886 Mask <<= 1;
2027 unsigned Mask = 1; local
2029 if (ErrorInfoMissingFeature & Mask) {
2031 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2033 Mask <<= 1;
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp769 uint64_t Mask,
779 Mask != (0xffu << ScaleLog))
812 uint64_t Mask,
832 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
879 uint64_t Mask,
887 unsigned MaskLZ = CountLeadingZeros_64(Mask);
888 unsigned MaskTZ = CountTrailingZeros_64(Mask);
899 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
1066 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); local
1070 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask,
768 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
811 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
878 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument
1247 uint64_t Mask = N.getConstantOperandVal(1); local
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/external/llvm/lib/Transforms/Vectorize/
H A DBBVectorize.cpp345 std::vector<Constant*> &Mask);
2242 std::vector<Constant*> &Mask) {
2247 Mask[v+MaskOffset] = UndefValue::get(Type::getInt32Ty(Context));
2253 Mask[v+MaskOffset] =
2276 std::vector<Constant*> Mask(NumElem);
2293 0, Mask);
2297 NumInElemI, Mask);
2299 return ConstantVector::get(Mask);
2497 std::vector<Constant *> Mask(numElem);
2501 Mask[
2239 fillNewShuffleMask(LLVMContext& Context, Instruction *J, unsigned MaskOffset, unsigned NumInElem, unsigned NumInElem1, unsigned IdxOffset, std::vector<Constant*> &Mask) argument
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/external/clang/lib/CodeGen/
H A DCGExpr.cpp1134 llvm::Constant *Mask[] = { local
1140 llvm::Value *MaskV = llvm::ConstantVector::get(Mask);
1231 SmallVector<llvm::Constant*, 4> Mask; local
1232 Mask.push_back(llvm::ConstantInt::get(
1235 Mask.push_back(llvm::ConstantInt::get(
1238 Mask.push_back(llvm::ConstantInt::get(
1241 Mask.push_back(llvm::UndefValue::get(llvm::Type::getInt32Ty(VMContext)));
1243 llvm::Value *MaskV = llvm::ConstantVector::get(Mask);
1375 SmallVector<llvm::Constant*, 4> Mask; local
1377 Mask
1591 SmallVector<llvm::Constant*, 4> Mask; local
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H A DCGExprScalar.cpp860 // Vector Mask Case
865 Value *Mask; local
871 Mask = CGF.EmitScalarExpr(E->getExpr(2));
884 Mask = RHS;
887 llvm::VectorType *MTy = cast<llvm::VectorType>(Mask->getType());
901 // Mask off the high bits of each shuffle index.
904 Mask = Builder.CreateAnd(Mask, MaskBits, "mask");
917 Value *Indx = Builder.CreateExtractElement(Mask, IIndx, "shuf_idx");
1076 llvm::Constant *Mask local
1129 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local
1145 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local
3143 llvm::Constant *Mask = llvm::ConstantVector::get(Args); local
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/external/llvm/bindings/ocaml/llvm/
H A Dllvm_ocaml.c1925 LLVMValueRef Mask,
1927 return LLVMBuildShuffleVector(Builder_val(B), V1, V2, Mask, String_val(Name));
1924 llvm_build_shufflevector(LLVMValueRef V1, LLVMValueRef V2, LLVMValueRef Mask, value Name, value B) argument
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp734 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
750 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
1176 unsigned Mask = RegInfo.createVirtualRegister(RC); local
1233 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1235 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1266 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1271 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1274 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1295 .addReg(OldVal).addReg(Mask);
1412 unsigned Mask local
2572 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); local
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/external/clang/include/clang/AST/
H A DExpr.h1757 enum { MaskBits = 2, Mask = 0x03 }; enumerator in enum:clang::StringLiteral::OffsetOfExpr::OffsetOfNode::__anon3414
1797 return static_cast<Kind>(Data & Mask);
1810 return reinterpret_cast<FieldDecl *>(Data & ~(uintptr_t)Mask);
1820 return reinterpret_cast<CXXBaseSpecifier *>(Data & ~(uintptr_t)Mask);
/external/clang/lib/AST/
H A DExprConstant.cpp5087 uint64_t Mask = ~0ULL >> (64 - PtrSize); local
5088 CompareLHS &= Mask;
5089 CompareRHS &= Mask;
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp57 unsigned Mask:4; // Condition mask for instructions. member in struct:__anon9676::ARMAsmParser::__anon9677
79 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
332 unsigned Mask:4; member in struct:__anon9678::ARMOperand::ITMaskOp
1463 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1536 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> local
1538 Inst.addOperand(MCOperand::CreateImm(Mask));
2029 // Mask in that this is an i8 splat.
2102 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { argument
2104 Op->ITMask.Mask = Mask;
5065 unsigned Mask = 8; local
7384 unsigned Mask = MO.getImm(); local
7577 unsigned Mask = 1; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3351 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); local
3352 assert(Mask && "Missing call preserved mask for calling convention");
3353 Ops.push_back(DAG.getRegisterMask(Mask));

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