Searched defs:Outs (Results 1 - 20 of 20) sorted by relevance

/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
120 unsigned NumOps = Outs
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H A DTargetLoweringBase.cpp1121 SmallVectorImpl<ISD::OutputArg> &Outs,
1162 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
1120 GetReturnInfo(Type* ReturnType, AttributeSet attr, SmallVectorImpl<ISD::OutputArg> &Outs, const TargetLowering &TLI) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
H A DHexagonISelLowering.cpp303 const SmallVectorImpl<ISD::OutputArg> &Outs,
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
432 Outs, OutVals, Ins, DAG);
460 ISD::ArgFlagsTy Flags = Outs[
301 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
1642 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp68 SmallVector<ISD::OutputArg, 4> Outs; local
69 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, TLI);
72 Outs, Fn->getContext());
H A DSelectionDAGBuilder.cpp1188 SmallVector<ISD::OutputArg, 8> Outs; local
1196 // Leave Outs empty so that LowerReturn won't try to load return
1266 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1278 Outs, OutVals, getCurDebugLoc(), DAG);
5207 SmallVector<ISD::OutputArg, 4> Outs; local
5208 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI);
5212 FTy->isVarArg(), Outs,
6394 CLI.Outs.clear();
6459 CLI.Outs.push_back(MyFlags);
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp115 SmallVectorImpl<MachineInstr*> &Outs);
368 SmallVectorImpl<MachineInstr*> &Outs) {
402 Outs.push_back(MI);
367 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
H A DARMFastISel.cpp2108 SmallVector<ISD::OutputArg, 4> Outs; local
2109 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2114 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2149 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2150 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
H A DARMISelLowering.cpp1347 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
1358 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1367 Outs, OutVals, Ins, DAG);
1380 CCInfo.AnalyzeCallOperands(Outs,
1408 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1793 const SmallVectorImpl<ISD::OutputArg> &Outs,
1806 if (isVarArg && !Outs.empty())
1874 if (!Outs
1788 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
1927 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1938 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp82 const SmallVectorImpl<ISD::OutputArg> &Outs,
78 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc DL, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp690 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
714 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
1018 const SmallVectorImpl<ISD::OutputArg> &Outs,
1030 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
1017 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp280 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
298 Outs, OutVals, Ins, dl, DAG, InVals);
408 const SmallVectorImpl<ISD::OutputArg> &Outs,
416 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
424 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
463 &Outs,
473 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
406 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
459 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp82 const SmallVectorImpl<ISD::OutputArg> &Outs,
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
349 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
377 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
378 ISD::ArgFlagsTy Flags = Outs[i].Flags;
411 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
80 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp253 const SmallVectorImpl<ISD::OutputArg> &Outs,
350 if (Outs[i].Flags.isByVal() == false) {
373 unsigned align = Outs[i].Flags.getByValAlign();
415 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
432 assert((Outs.size() == Args.size()) &&
437 for (unsigned i=0, e=Outs.size(); i!=e; ++i) {
438 EVT VT = Outs[i].VT;
440 if (Outs[i].Flags.isByVal() == false) {
466 if (Outs[
251 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment) const argument
1200 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp746 SmallVector<ISD::OutputArg, 4> Outs; local
747 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
753 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
786 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
792 if (Outs[0].Flags.isSExt())
797 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
1667 SmallVector<ISD::OutputArg, 4> Outs;
1668 GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI);
1671 Outs, FT
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H A DX86ISelLowering.cpp1586 const SmallVectorImpl<ISD::OutputArg> &Outs,
1591 return CCInfo.CheckReturn(Outs, RetCC_X86);
1597 const SmallVectorImpl<ISD::OutputArg> &Outs,
1606 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1837 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { argument
1838 if (Outs.empty())
1841 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2280 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
2293 StructReturnType SR = callIsStructReturn(Outs);
1584 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1595 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
2822 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp899 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
919 Outs, OutVals, Ins, dl, DAG, InVals);
931 const SmallVectorImpl<ISD::OutputArg> &Outs,
946 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1227 const SmallVectorImpl<ISD::OutputArg> &Outs,
1231 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1237 const SmallVectorImpl<ISD::OutputArg> &Outs,
1250 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
928 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1225 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
1235 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1008 const SmallVectorImpl<ISD::OutputArg> &Outs,
1019 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1084 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
1097 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1103 Outs, OutVals, Ins, DAG);
1114 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1159 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1393 const SmallVectorImpl<ISD::OutputArg> &Outs,
1006 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
1388 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
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/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2587 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
2607 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2647 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2976 const SmallVectorImpl<ISD::OutputArg> &Outs,
2981 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2987 const SmallVectorImpl<ISD::OutputArg> &Outs,
3001 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat,
3483 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, argument
3485 analyzeReturn(Outs, IsSoftFloa
2974 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
2985 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc DL, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2774 &Outs,
2781 unsigned NumOps = Outs.size();
2792 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2793 EVT ArgVT = Outs[i].VT;
3422 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local
3438 isTailCall, Outs, OutVals, Ins,
3442 isTailCall, Outs, OutVals, Ins,
3447 isTailCall, Outs, OutVals, Ins,
3455 const SmallVectorImpl<ISD::OutputArg> &Outs,
2769 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument
3452 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3684 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4055 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4403 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument
4414 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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