Searched defs:Reg (Results 176 - 193 of 193) sorted by relevance

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/external/valgrind/main/VEX/priv/
H A Dhost_mips_defs.h183 Mam_IR, /* Immediate (signed 16-bit) + Reg */
226 } Reg; member in union:__anon14255::__anon14256
245 /* --------- Reg or imm-8x4 operands --------- */
272 /* --------- Reg or imm5 operands --------- */
H A Dhost_amd64_defs.h125 Aam_IR, /* Immediate + Reg */
175 } Reg; member in union:__anon14076::__anon14077
210 } Reg; member in union:__anon14082::__anon14083
237 } Reg; member in union:__anon14087::__anon14088
H A Dhost_x86_defs.h113 Xam_IR, /* Immediate + Reg */
163 } Reg; member in union:__anon14459::__anon14460
197 } Reg; member in union:__anon14465::__anon14466
224 } Reg; member in union:__anon14470::__anon14471
H A Dhost_ppc_defs.h200 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
248 } Reg; member in union:__anon14318::__anon14319
274 HReg Reg; member in union:__anon14323::__anon14324
300 HReg Reg; member in union:__anon14326::__anon14327
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1447 unsigned Reg; member in class:llvm::SDNode::RegisterSDNode
1450 : SDNode(ISD::Register, DebugLoc(), getSDVTList(VT)), Reg(reg) {
1454 unsigned getReg() const { return Reg; }
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp932 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
934 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp241 unsigned Reg = MO.getReg(); local
243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
247 LV->addVirtualRegisterDead(Reg, NewMI);
253 if (!NewMI->readsRegister(Reg))
255 LV->addVirtualRegisterKilled(Reg, NewMI);
752 unsigned Reg, unsigned SubIdx, unsigned State,
755 return MIB.addReg(Reg, State);
757 if (TargetRegisterInfo::isPhysicalRegister(Reg))
758 return MIB.addReg(TRI->getSubReg(Reg, SubId
751 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) argument
1623 canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) argument
2268 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
3039 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3063 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3285 unsigned Reg = DefMO.getReg(); local
4041 unsigned Reg = MO.getReg(); local
4098 unsigned Reg = MO.getReg(); local
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H A DARMFastISel.cpp62 unsigned Reg; member in union:__anon9662::Address::__anon9664
71 Base.Reg = 0;
899 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
900 return Addr.Base.Reg != 0;
943 Addr.Base.Reg = ResultReg;
950 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
989 MIB.addReg(Addr.Base.Reg);
2030 Addr.Base.Reg
2118 unsigned Reg = getRegForValue(RV); local
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H A DARMISelLowering.cpp2558 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
2559 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2572 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2573 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2742 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
2743 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3415 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); local
3416 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
6665 unsigned Reg = SavedRegs[i]; local
6667 !ARM::tGPRRegClass.contains(Reg)
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp199 struct RegOp Reg; member in union:__anon9798::X86Operand::__anon9799
231 return Reg.RegNo;
487 Res->Reg.RegNo = RegNo;
792 void onRegister(unsigned Reg) { argument
799 TmpReg = Reg;
804 IndexReg = Reg;
1742 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg, argument
1747 TmpInst.addOperand(MCOperand::CreateReg(Reg));
1748 TmpInst.addOperand(MCOperand::CreateReg(Reg));
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp95 void setBaseReg(SDValue Reg) { argument
97 Base_Reg = Reg;
1093 SDValue Reg; local
1100 Reg = MulVal.getNode()->getOperand(0);
1105 Reg = N.getNode()->getOperand(0);
1107 Reg = N.getNode()->getOperand(0);
1110 AM.IndexReg = AM.Base_Reg = Reg;
2522 SDValue Reg = N0.getNode()->getOperand(0); local
2533 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2534 Reg
2558 SDValue Reg = N0.getNode()->getOperand(0); local
2594 SDValue Reg = N0.getNode()->getOperand(0); local
2616 SDValue Reg = N0.getNode()->getOperand(0); local
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H A DX86InstrInfo.cpp1510 unsigned Reg; local
1511 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1512 return Reg;
1532 unsigned Reg; local
1533 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1534 return Reg;
2786 static bool isHReg(unsigned Reg) { argument
2787 return X86::GR8_ABCD_HRegClass.contains(Reg);
2902 static unsigned getLoadStoreRegOpcode(unsigned Reg, argument
2916 if (isHReg(Reg) || X8
3478 unsigned Reg = MO.getReg(); local
3530 unsigned Reg = MIB->getOperand(0).getReg(); local
3820 unsigned Reg = MO.getReg(); local
3838 unsigned Reg = MI->getOperand(OpNum).getReg(); local
4098 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
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H A DX86ISelLowering.cpp1688 unsigned Reg = FuncInfo->getSRetReturnReg(); local
1689 assert(Reg &&
1691 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2015 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
2016 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2056 unsigned Reg = FuncInfo->getSRetReturnReg(); local
2057 if (!Reg) {
2059 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2060 FuncInfo->setSRetReturnReg(Reg);
2062 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVal
3003 unsigned Reg = VA.getLocReg(); local
7832 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; local
10066 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); local
11925 unsigned Reg = 0; local
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/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1981 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); local
1982 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2452 unsigned Reg; local
2463 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2466 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2467 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2472 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2473 if (Reg == Mips::A1 || Reg
2513 getNextIntArgReg(unsigned Reg) argument
2889 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); local
2945 unsigned Reg = MipsFI->getSRetReturnReg(); local
3029 unsigned Reg = MipsFI->getSRetReturnReg(); local
3751 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); local
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/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp142 void CountRegister(const SCEV *Reg, size_t LUIdx);
143 void DropRegister(const SCEV *Reg, size_t LUIdx);
146 bool isRegUsedByUsesOtherThan(const SCEV *Reg, size_t LUIdx) const;
148 const SmallBitVector &getUsedByIndices(const SCEV *Reg) const;
163 RegUseTracker::CountRegister(const SCEV *Reg, size_t LUIdx) { argument
165 RegUsesMap.insert(std::make_pair(Reg, RegSortData()));
168 RegSequence.push_back(Reg);
174 RegUseTracker::DropRegister(const SCEV *Reg, size_t LUIdx) { argument
175 RegUsesTy::iterator It = RegUsesMap.find(Reg);
199 RegUseTracker::isRegUsedByUsesOtherThan(const SCEV *Reg, size_
839 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument
887 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
3471 const SCEV *Reg = *I; local
3488 const SCEV *Reg = *I; local
3710 const SCEV *Reg = *J; local
3968 const SCEV *Reg = *I; local
4065 const SCEV *Reg = *J; local
4298 const SCEV *Reg = *I; local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp611 unsigned Reg, Type *Ty) {
619 Regs.push_back(Reg + i);
621 Reg += NumRegs;
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
1313 unsigned Reg = FuncInfo.InitializeRegForValue(V); local
1314 CopyValueToVirtualRegister(V, Reg);
1673 assert(JT.Reg != -1U && "Should lower JT Header first!");
1676 JT.Reg, PT
610 RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg, Type *Ty) argument
1799 visitBitTestCase(BitTestBlock &BB, MachineBasicBlock* NextMBB, uint32_t BranchWeightToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB) argument
4376 unsigned Reg = 0; local
6559 CopyValueToVirtualRegister(const Value *V, unsigned Reg) argument
6779 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); local
6836 unsigned Reg; local
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/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp429 struct RegOp Reg; member in union:__anon9678::ARMOperand::__anon9679
460 Reg = o.Reg;
543 return Reg.RegNum;
2144 Op->Reg.RegNum = RegNum;
2161 Op->Reg.RegNum = RegNum;
2801 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); local
2802 if (Reg == -1)
2806 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2847 static unsigned getNextRegister(unsigned Reg) { argument
2900 int Reg = tryParseRegister(); local
3077 int Reg = tryParseRegister(); local
3135 int Reg = tryParseRegister(); local
3827 int Reg = tryParseRegister(); local
3908 int Reg = tryParseRegister(); local
5246 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5262 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument
7794 unsigned Reg; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1953 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local
1954 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);

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