Searched defs:Reg0 (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp225 unsigned Reg0 = Op0.getReg(); local
226 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
230 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
232 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp153 unsigned Reg0 = MI->getOperand(0).getReg(); local
161 if (Reg0 == Reg1) {
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local
178 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h513 uint16_t Reg0; member in class:llvm::MCRegUnitRootIterator
518 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
524 return Reg0;
529 return Reg0;
535 Reg0 = Reg1;
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
145 if (HasDef && Reg0 == Reg1 &&
148 Reg0 = Reg2;
150 } else if (HasDef && Reg0 == Reg2 &&
153 Reg0 = Reg1;
164 MI->getOperand(0).setReg(Reg0);
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp328 unsigned Reg0 = MI->getOperand(0).getReg(); local
331 if (isStackReg(Reg0) || isStackReg(Reg1)) {
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp616 unsigned Reg0 = MI->getOperand(0).getReg(); local
622 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
625 if (Reg0 != Reg2) {
628 if (Reg1 != Reg0)
635 } else if (Reg0 != Reg1) {
639 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
645 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
H A DARMISelDAGToDAG.cpp1739 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1751 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1759 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1762 Ops.push_back(Reg0);
1775 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1788 Ops.push_back(Reg0);
1792 Ops.push_back(Reg0);
1866 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1902 // FIXME: VST1/VST2 fixed increment doesn't need Reg0
2030 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2127 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2230 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2659 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2675 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
3504 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
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