/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsDirectObjLower.cpp | 28 int64_t Shift = Inst.getOperand(2).getImm(); local 29 if (Shift <= 31) 31 Shift -= 32; 34 Inst.getOperand(2).setImm(Shift);
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H A D | MipsMCCodeEmitter.cpp | 54 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; local 55 EmitByte((Val >> Shift) & 0xff, OS);
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/external/llvm/include/llvm/Support/ |
H A D | LEB128.h | 83 unsigned Shift = 0; local 85 Value += (*p & 0x7f) << Shift; 86 Shift += 7;
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/external/clang/include/clang/Basic/ |
H A D | OperatorPrecedence.h | 39 Shift = 11, // <<, >> enumerator in enum:clang::prec::Level
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/external/chromium/third_party/libjingle/source/talk/base/ |
H A D | bytebuffer.cc | 202 void ByteBuffer::Shift(size_t size) { function in class:talk_base::ByteBuffer
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/external/qemu/distrib/sdl-1.2.15/src/main/symbian/EKA2/ |
H A D | vectorbuffer.h | 50 TPtrC8 Shift(); 143 //Shift(); //data is lost 149 TPtrC8 TVectorBuffer<C>::Shift() function in class:TVectorBuffer 163 return Shift(); //this happens when buffer is terminated, and data lies in next 200 const T& Shift(); 218 const T& TVector<T, C>::Shift() function in class:TVector 220 const TPtrC8 ptr = TVectorBuffer<C * sizeof(T)>::Shift();
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/external/llvm/lib/Archive/ |
H A D | ArchiveReader.cpp | 28 unsigned Shift = 0; local 34 Result |= (unsigned)((*At++) & 0x7F) << Shift; 35 Shift += 7;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 184 int UImm16, Shift; local 188 if (A64Imms::isMOVZImm(DestWidth, BitPat, UImm16, Shift)) { 191 } else if (A64Imms::isMOVNImm(DestWidth, BitPat, UImm16, Shift)) { 194 } else if (DestWidth == 64 && A64Imms::isMOVNImm(32, BitPat, UImm16, Shift)) { 214 CurDAG->getTargetConstant(Shift, MVT::i32));
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/external/v8/src/ |
H A D | fixed-dtoa.cc | 64 void Shift(int shift_amount) { function in class:v8::internal::UInt128 272 fractionals128.Shift(-exponent - 64);
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/external/webkit/Source/WebCore/inspector/front-end/ |
H A D | KeyboardShortcut.js | 40 Shift: 1, 109 modifiers |= WebInspector.KeyboardShortcut.Modifiers.Shift; 163 if (modifiers & WebInspector.KeyboardShortcut.Modifiers.Shift) 164 res += isMac ? shiftKey : "<Shift> + ";
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 782 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { argument 791 Shift = i / 16; 799 bool A64Imms::isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { argument 810 return isMOVZImm(RegWidth, MOVZEquivalent, UImm16, Shift); 814 int &UImm16, int &Shift) { 815 if (isMOVZImm(RegWidth, Value, UImm16, Shift)) 818 return isMOVNImm(RegWidth, Value, UImm16, Shift); 813 isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) argument
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/external/llvm/lib/Target/R600/ |
H A D | AMDILISelLowering.cpp | 348 SDValue Shift = DAG.getConstant(shiftBits, DVT); local 349 // Shift left by 'Shift' bits. 350 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); 351 // Signed shift Right by 'Shift' bits. 352 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 604 Value *Shift = Builder->CreateLShr(X, ShiftDiffCst); local 607 return BinaryOperator::CreateAnd(Shift, 652 Value *Shift = Builder->CreateShl(X, ShiftDiffCst); 655 return BinaryOperator::CreateAnd(Shift,
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H A D | InstCombinePHI.cpp | 558 unsigned Shift; // The amount shifted. member in struct:__anon9882::PHIUsageRecord 562 : PHIId(pn), Shift(Sh), Inst(User) {} 567 if (Shift < RHS.Shift) return true; 568 if (Shift > RHS.Shift) return false; 576 unsigned Shift; // The amount shifted. member in struct:__anon9882::LoweredPHIRecord 580 : PN(pn), Shift(Sh), Width(Ty->getPrimitiveSizeInBits()) {} 584 : PN(pn), Shift(Sh), Width(0) {} 598 return DenseMapInfo<PHINode*>::getHashValue(Val.PN) ^ (Val.Shift>> 678 unsigned Shift = cast<ConstantInt>(User->getOperand(1))->getZExtValue(); local [all...] |
H A D | InstCombineCompares.cpp | 1146 BinaryOperator *Shift = dyn_cast<BinaryOperator>(LHSI->getOperand(0)); local 1147 if (Shift && !Shift->isShift()) 1148 Shift = 0; 1151 ShAmt = Shift ? dyn_cast<ConstantInt>(Shift->getOperand(1)) : 0; 1152 Type *Ty = Shift ? Shift->getType() : 0; // Type of the shift. 1159 bool CanFold = Shift->isLogicalShift(); 1174 if (Shift [all...] |
/external/chromium/net/server/ |
H A D | http_server.cc | 205 void HttpServer::Connection::Shift(int num_bytes) { function in class:net::HttpServer::Connection 385 connection->Shift(pos); 408 connection->Shift(pos); 414 connection->Shift(pos);
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 407 unsigned Shift = FullImm >> 16; local 409 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 412 Inst.addOperand(MCOperand::CreateImm(Shift));
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 258 A64SE::ShiftExtSpecifiers Shift) { 262 if (Shift == A64SE::LSL && MO.isImm() && MO.getImm() == 0) 265 switch (Shift) { 256 printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, A64SE::ShiftExtSpecifiers Shift) argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 822 bool Shift = false; local 840 Shift = true; 845 Shift = true; 855 if (Shift)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 367 unsigned Shift = 32; local 371 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 376 if (isShiftMask) Mask = Mask << Shift; 378 Indeterminant = ~(0xFFFFFFFFu << Shift); 381 if (isShiftMask) Mask = Mask >> Shift; 383 Indeterminant = ~(0xFFFFFFFFu >> Shift); 385 Shift = 32 - Shift; 917 unsigned Shift = 0; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGISel.cpp | 1690 unsigned Shift = 7; local 1694 Val |= (NextBits&127) << Shift; 1695 Shift += 7;
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H A D | TargetLowering.cpp | 899 SDValue Shift = In.getOperand(1); local 902 Shift = 919 Shift)); 1506 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), local 1509 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1534 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, local 1537 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 2446 // Shift the value upfront if it is even, so the LSB is one. 2508 // Shift right algebraic if shift value is nonzero 2549 unsigned Shift local [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 419 int UImm16, Shift; local 420 return !A64Imms::isMOVZImm(RegWidth, CE->getValue(), UImm16, Shift) 421 && !A64Imms::isMOVNImm(RegWidth, CE->getValue(), UImm16, Shift); 591 int UImm16, Shift; local 604 return isValidImm(RegWidth, Value, UImm16, Shift); 995 int UImm16, Shift; local 1004 bool Valid = isValidImm(RegWidth, Value, UImm16, Shift); 1009 Inst.addOperand(MCOperand::CreateImm(Shift));
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 834 unsigned Shift = Log2_32(IVBump); local 836 // Generate NormR = LSR DistR, Shift. 841 .addImm(Shift);
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H A D | HexagonISelDAGToDAG.cpp | 923 SDValue Shift = N->getOperand(0); local 939 if (Shift.getNode()->getValueType(0) == MVT::i64) { 941 if (Shift.getOpcode() != ISD::SRL) { 945 SDValue ShiftOp0 = Shift.getOperand(0); 946 SDValue ShiftOp1 = Shift.getOperand(1); 948 // Shift by const 32
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