| /external/llvm/include/llvm/MC/ |
| H A D | MachineLocation.h | 51 bool isReg() const { return IsRegister; } function in class:llvm::MachineLocation
|
| H A D | MCInst.h | 56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 188 return isReg() ? 0 : SubReg_TargetFlags;
191 assert(!isReg() && "Register operands can't have target flags");
196 assert(!isReg() && "Register operands can't have target flags");
223 /// isReg - Tests if this is a MO_Register operand.
224 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand
260 assert(isReg() && "This is not a register operand!");
265 assert(isReg() && "Wrong MachineOperand accessor");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg()
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| H A D | MBlazeAsmParser.cpp | 181 bool isReg() const { return Kind == Register; } function in struct:__anon9711::MBlazeOperand
368 if (!Base.isReg()) {
373 if (!Offset.isReg() && !Offset.isImm()) {
379 if (Offset.isReg())
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 154 bool isReg() const { return Kind == CV_Register; } function in class:__anon9758::CountValue
159 assert(isReg() && "Wrong CountValue accessor");
177 if (isReg()) { OS << PrintReg(getReg()); }
391 assert(InitialValue->isReg() && "Expecting register for init value");
464 MI->getOperand(1).isReg() && // could be a frame index instead
481 if (MO.isReg() && MO.isDef() &&
516 if (MO.isReg() && MO.isDef()) {
530 if (OPO.isReg() && OPO.isDef()) {
573 if (!MO.isReg() || !MO.isDef())
683 if (TripCount->isReg()) {
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenInstruction.h | 312 bool isReg() const { return Kind == K_Reg; } function in struct:llvm::CodeGenInstAlias::ResultOperand
317 Record *getRegister() const { assert(isReg()); return R; }
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 408 if (MO.isReg()) {
559 if (MCOp1.isImm() && MCOp2.isReg() &&
743 if (!MO.isReg()) {
823 if (!MO.isReg()) {
994 bool isReg = MO.getReg() != 0; local
997 if (isReg) {
1003 return Binary | (isAdd << 12) | (isReg << 13);
1049 if (!MO.isReg()) {
1121 if (!MO.isReg()) {
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 260 bool isReg() const { return Kind == k_Register; } function in class:__anon9643::AArch64Operand
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 252 bool isReg() const { return Kind == CV_Register; } function in class:__anon9699::CountValue
256 assert(isReg() && "Wrong CountValue accessor");
260 assert(isReg() && "Wrong CountValue accessor");
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
527 if (Op1.isReg()) {
570 if (InitialValue->isReg()) {
597 if (InitialValue->isReg()) {
604 if (EndValue->isReg()) {
630 if (Start->isReg()) {
635 if (End->isReg()) {
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 273 bool isReg() const { return Kind == k_Register; } function in class:__anon9734::MipsOperand
423 assert(RegOp.isReg() && "expected register operand kind");
469 assert(SrcRegOp.isReg() && "expected register operand kind");
471 assert(DstRegOp.isReg() && "expected register operand kind");
511 assert(RegOp.isReg() && "expected register operand kind");
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 444 unsigned isReg = 1; local
446 isReg = 0;
453 DAG.getConstant(isReg, MVT::i32),
463 if (isReg)
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 403 bool isReg() const { return Kind == Register; } function in struct:__anon9798::X86Operand
1607 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1620 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1647 if (isSrcOp(*Op1) && Op2->isReg()) {
1677 if (isDstOp(*Op2) && Op1->isReg()) {
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 893 bool isReg() const { return Kind == k_Register; } function in class:__anon9678::ARMOperand
2576 if (!PrevOp->isReg())
4888 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4889 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4899 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4900 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4903 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4913 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4914 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4945 static_cast<ARMOperand*>(Operands[3])->isReg()
[all...] |
| /external/valgrind/main/VEX/priv/ |
| H A D | guest_x86_toIR.c | 5457 Bool isReg = epartIsReg(modrm); local
5550 if (isReg) {
5588 ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
6355 Bool isReg; local
6371 isReg = epartIsReg(modrm);
6372 if (isReg) {
6384 ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ),
|
| H A D | guest_amd64_toIR.c | 6701 Bool isReg = epartIsReg(modrm); local
6794 if (isReg) {
6832 ( isReg ? nameMMXReg(eregLO3ofRM(modrm)) : dis_buf ),
7758 Bool isReg; local
7772 isReg = epartIsReg(modrm);
7773 if (isReg) {
7785 ( isReg ? nameIRegE(sz, pfx, modrm) : dis_buf ),
|