Searched refs:DL (Results 26 - 50 of 179) sorted by relevance

12345678

/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp39 DebugLoc DL; local
40 if (MI != MBB.end()) DL = MI->getDebugLoc();
51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
67 DebugLoc DL; local
68 if (MI != MBB.end()) DL = MI->getDebugLoc();
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
89 MachineBasicBlock::iterator I, DebugLoc DL,
100 BuildMI(MBB, I, DL, ge
88 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
[all...]
H A DMSP430InstrInfo.h55 MachineBasicBlock::iterator I, DebugLoc DL,
85 DebugLoc DL) const;
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp233 DebugLoc DL) const {
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
281 MachineBasicBlock::iterator I, DebugLoc DL,
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
302 DebugLoc DL; local
280 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
324 DebugLoc DL; local
[all...]
H A DSparcInstrInfo.h83 DebugLoc DL) const;
86 MachineBasicBlock::iterator I, DebugLoc DL,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp200 DebugLoc DL; local
201 BuildMI(MBB, MI, DL, get(PPC::NOP));
374 DebugLoc DL) const {
385 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
387 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
391 BuildMI(&MBB, DL, get(PPC::BCC))
398 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
402 BuildMI(&MBB, DL, get(PPC::BCC))
404 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
409 MachineBasicBlock::iterator I, DebugLoc DL,
408 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
444 DebugLoc DL; local
572 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI) const argument
656 DebugLoc DL; local
[all...]
H A DPPCInstrInfo.h76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
122 DebugLoc DL) const;
124 MachineBasicBlock::iterator I, DebugLoc DL,
144 DebugLoc DL) const;
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp79 DebugLoc DL; local
80 BuildMI(MBB, MI, DL, get(MBlaze::NOP));
85 MachineBasicBlock::iterator I, DebugLoc DL,
88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg)
97 DebugLoc DL; local
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
107 DebugLoc DL; local
108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
190 DebugLoc DL) const {
202 BuildMI(&MBB, DL, ge
84 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
[all...]
H A DMBlazeTargetMachine.h33 const DataLayout DL; // Calculates type size & alignment member in class:llvm::MBlazeTargetMachine
61 { return &DL;}
/external/llvm/include/llvm/CodeGen/
H A DLexicalScopes.h71 void getMachineBasicBlocks(DebugLoc DL,
76 bool dominates(DebugLoc DL, MachineBasicBlock *MBB);
80 LexicalScope *findLexicalScope(DebugLoc DL);
94 LexicalScope *findInlinedScope(DebugLoc DL) { argument
95 return InlinedLexicalScopeMap.lookup(DL);
110 LexicalScope *getOrCreateLexicalScope(DebugLoc DL);
H A DGCMetadata.h65 GCPoint(GC::PointKind K, MCSymbol *L, DebugLoc DL) argument
66 : Kind(K), Label(L), Loc(DL) {}
133 void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) { argument
134 SafePoints.push_back(GCPoint(Kind, Label, DL));
/external/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp163 DebugLoc DL = MII->getDebugLoc(); local
169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
173 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
179 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
H A DHexagonTargetMachine.h30 const DataLayout DL; // Calculates type size & alignment. member in class:llvm::HexagonTargetMachine
71 virtual const DataLayout *getDataLayout() const { return &DL; }
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h58 DebugLoc DL) const;
72 DebugLoc DL) const;
102 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
H A DMipsSERegisterInfo.cpp110 DebugLoc DL = II->getDebugLoc(); local
114 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
H A DMipsSEInstrInfo.h48 MachineBasicBlock::iterator MI, DebugLoc DL,
76 MachineBasicBlock::iterator II, DebugLoc DL,
/external/llvm/lib/Analysis/
H A DPtrUseVisitor.cpp35 return GEPI.accumulateConstantOffset(DL, Offset);
H A DTargetTransformInfo.cpp206 const DataLayout *DL; member in struct:__anon9425::NoTTI
208 NoTTI() : ImmutablePass(ID), DL(0) {
217 DL = getAnalysisIfAvailable<DataLayout>();
256 if (DL && DL->isLegalInteger(OpTy->getScalarSizeInBits()) &&
257 OpTy->getScalarSizeInBits() <= DL->getPointerSizeInBits())
266 if (DL && DL->isLegalInteger(Ty->getScalarSizeInBits()) &&
267 Ty->getScalarSizeInBits() >= DL->getPointerSizeInBits())
276 if (DL
[all...]
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.h71 const DataLayout DL; // Calculates type size & alignment member in class:llvm::ARMTargetMachine
97 virtual const DataLayout *getDataLayout() const { return &DL; }
108 const DataLayout DL; // Calculates type size & alignment member in class:llvm::ThumbTargetMachine
141 virtual const DataLayout *getDataLayout() const { return &DL; }
/external/llvm/lib/Target/X86/
H A DX86TargetMachine.h81 const DataLayout DL; // Calculates type size & alignment member in class:llvm::X86_32TargetMachine
91 virtual const DataLayout *getDataLayout() const { return &DL; }
110 const DataLayout DL; // Calculates type size & alignment member in class:llvm::X86_64TargetMachine
120 virtual const DataLayout *getDataLayout() const { return &DL; }
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp359 DebugLoc DL = Op.getDebugLoc(); local
373 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
377 DL, MVT::f32, SDValue(interp, 0));
381 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
388 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
399 return LowerImplicitParameter(DAG, VT, DL, 0);
401 return LowerImplicitParameter(DAG, VT, DL, 1);
403 return LowerImplicitParameter(DAG, VT, DL, 2);
405 return LowerImplicitParameter(DAG, VT, DL, 3);
407 return LowerImplicitParameter(DAG, VT, DL,
476 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument
507 DebugLoc DL = Op.getDebugLoc(); local
529 DebugLoc DL = Op.getDebugLoc(); local
715 DebugLoc DL = Op.getDebugLoc(); local
827 DebugLoc DL = Op.getDebugLoc(); local
923 DebugLoc DL = Op.getDebugLoc(); local
933 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1112 DebugLoc DL = N->getDebugLoc(); local
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h54 MachineBasicBlock::iterator I, DebugLoc DL,
74 DebugLoc DL) const;
/external/libvpx/libvpx/examples/includes/ASCIIMathPHP-2.0/
H A DASCIIMathPHP-2.0.cfg.php144 'arcsin' => array( 'input'=>'arcsin','tag'=>'mo', 'output'=>'arcsin', 'unary'=>TRUE, 'func'=>TRUE), //2006-9-7 DL
145 'arccos' => array( 'input'=>'arccos', 'tag'=>'mo', 'output'=>'arccos', 'unary'=>TRUE, 'func'=>TRUE), //2006-9-7 DL
146 'arctan' => array( 'input'=>'arctan', 'tag'=>'mo', 'output'=>'arctan', 'unary'=>TRUE, 'func'=>TRUE), //2006-9-7 DL
167 'f' => array( 'input'=>'f','tag'=>'mi', 'output'=>'f', 'unary'=>TRUE, 'func'=>TRUE), //2006-9-7 DL
168 'g' => array( 'input'=>'g', 'tag'=>'mi', 'output'=>'g', 'unary'=>TRUE, 'func'=>TRUE), //2006-9-7 DL
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
342 DebugLoc OldDL = DL;
344 DL = DebugLoc();
355 DL = OldInsertPt.DL;
579 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
644 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
662 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
667 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
671 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, I
865 FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) argument
[all...]
H A DLegalizeVectorOps.cpp577 DebugLoc DL = Op.getDebugLoc(); local
608 Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask,
614 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
624 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
629 return DAG.getNode(ISD::BITCAST, DL, O
656 DebugLoc DL = Op.getDebugLoc(); local
696 DebugLoc DL = Op.getDebugLoc(); local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h42 MachineBasicBlock::iterator I, DebugLoc DL,
48 DebugLoc DL) const;
68 DebugLoc DL) const;

Completed in 1491 milliseconds

12345678