Searched refs:TII (Results 151 - 175 of 193) sorted by relevance

12345678

/external/llvm/lib/Target/MBlaze/
H A DMBlazeRegisterInfo.cpp46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
H A DMBlazeInstrInfo.cpp288 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
291 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
/external/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp107 const TargetInstrInfo *TII = TM.getInstrInfo(); local
111 TII->get(TargetOpcode::BUNDLE));
H A DMachineTraceMetrics.cpp39 : MachineFunctionPass(ID), MF(0), TII(0), TRI(0), MRI(0), Loops(0) {
52 TII = MF->getTarget().getInstrInfo();
58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
775 const TargetInstrInfo *TII,
834 const TargetInstrInfo *TII) {
952 Heights, MTM.SchedModel, MTM.TII))
981 MTM.SchedModel, MTM.TII, MTM.TRI);
985 if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
H A DRegAllocFast.cpp59 const TargetInstrInfo *TII; member in class:__anon9501::RAFast
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
314 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
629 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
867 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
1078 TII = TM->getInstrInfo();
H A DAggressiveAntiDepBreaker.cpp121 TII(MF.getTarget().getInstrInfo()),
368 TII->isPredicated(MI)) {
387 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
435 TII->isPredicated(MI);
461 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
H A DMachineScheduler.cpp203 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
249 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
259 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
765 const TargetInstrInfo *TII; member in class:__anon9482::LoadClusterMutation
770 : TII(tii), TRI(tri) {}
793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
808 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
871 const TargetInstrInfo *TII; member in class:__anon9483::MacroFusion
873 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
889 if (!TII
[all...]
H A DMachineVerifier.cpp67 const TargetInstrInfo *TII; member in struct:__anon9491::MachineVerifier
287 TII = TM->getInstrInfo();
543 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
567 !TII->isPredicated(getBundleStart(&MBB->back()))) {
706 if (MI->isTerminator() && !TII->isPredicated(MI)) {
797 if (!TII->verifyInstruction(MI, ErrorInfo))
890 TII->getRegClass(MCID, MONum, TRI, *MF)) {
917 TII->getRegClass(MCID, MONum, TRI, *MF)) {
H A DRegisterCoalescer.cpp83 const TargetInstrInfo* TII; member in class:__anon9508::RegisterCoalescer
605 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
645 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
753 if (!TII->isTriviallyReMaterializable(DefMI, AA))
756 if (!DefMI->isSafeToMove(TII, AA, SawStore))
769 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
780 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
2138 TII = TM->getInstrInfo();
H A DStrongPHIElimination.cpp145 const TargetInstrInfo *TII; member in class:__anon9542::StrongPHIElimination
235 TII = MF.getTarget().getInstrInfo();
698 TII->get(TargetOpcode::COPY),
767 TII->get(TargetOpcode::COPY),
H A DMachineInstr.cpp949 const TargetInstrInfo *TII,
957 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1225 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, argument
1258 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, argument
1262 if (!TII->isTriviallyReMaterializable(this, AA) ||
1263 !isSafeToMove(TII, AA, SawStore))
H A DScheduleDAG.cpp38 TII(TM.getInstrInfo()),
59 return &TII->get(Node->getMachineOpcode());
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp307 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
308 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp238 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
434 const TargetInstrInfo *TII) {
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
574 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
433 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument
H A DFunctionLoweringInfo.cpp174 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
176 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
350 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
357 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
360 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
368 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
369 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
390 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
443 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
447 BuildMI(BB, dl, TII->get(CmpOp))
450 BuildMI(BB, dl, TII
482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
[all...]
H A DAArch64ISelDAGToDAG.cpp36 const AArch64InstrInfo *TII; member in class:__anon9639::AArch64DAGToDAGISel
46 TII(static_cast<const AArch64InstrInfo*>(TM.getInstrInfo())),
/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp32 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
227 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
462 if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
502 const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
554 const MCInstrDesc *Desc = &TII->get(Opcode);
561 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
5727 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5730 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5731 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5733 BuildMI(BB, dl, TII->get(PPC::BCC))
5750 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
5822 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5827 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5829 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5832 BuildMI(BB, dl, TII
5878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
[all...]
H A DPPCISelDAGToDAG.cpp227 const TargetInstrInfo &TII = *TM.getInstrInfo(); local
235 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
236 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
238 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
252 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
263 const TargetInstrInfo &TII = *TM.getInstrInfo(); local
271 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
272 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
275 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
276 BuildMI(FirstMBB, MBBI, dl, TII
[all...]
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2770 const X86InstrInfo *TII) {
2781 if (!TII->isLoadFromStackSlot(Def, FI))
2968 const X86InstrInfo *TII = local
2978 MFI, MRI, TII))
12727 const TargetInstrInfo *TII) {
12761 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12767 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12774 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12923 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
12992 MIB = BuildMI(thisMBB, DL, TII
2768 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const X86InstrInfo *TII) argument
12726 EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, const TargetInstrInfo *TII) argument
13196 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
13463 EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII) argument
13500 EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII) argument
13535 EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII, const X86Subtarget* Subtarget) argument
13593 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
13851 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
13928 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
13996 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
14117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
14174 const X86InstrInfo *TII local
14230 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
14365 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
14470 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h823 const TargetInstrInfo *TII,
908 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
913 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
H A DFastISel.h58 const TargetInstrInfo &TII; member in class:llvm::FastISel
H A DLiveIntervalAnalysis.h54 const TargetInstrInfo* TII; member in class:llvm::LiveIntervals
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp53 const HexagonInstrInfo *TII; member in class:__anon9701::HexagonDAGToDAGISel
61 TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
398 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
462 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
539 if (TII->isValidAutoIncImm(LoadedVT, Val))
544 if (TII->isValidAutoIncImm(LoadedVT, Val))
549 if (TII->isValidAutoIncImm(LoadedVT, Val))
554 if (TII->isValidAutoIncImm(LoadedVT, Val))
571 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
646 if (TII
[all...]

Completed in 562 milliseconds

12345678