/external/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.h | 26 explicit AArch64SelectionDAGInfo(const AArch64TargetMachine &TM);
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H A D | AArch64.h | 29 FunctionPass *createAArch64ISelDAG(AArch64TargetMachine &TM,
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeSelectionDAGInfo.h | 25 explicit MBlazeSelectionDAGInfo(const MBlazeTargetMachine &TM);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430SelectionDAGInfo.h | 25 explicit MSP430SelectionDAGInfo(const MSP430TargetMachine &TM);
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H A D | MSP430.h | 40 FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSelectionDAGInfo.h | 25 explicit MipsSelectionDAGInfo(const MipsTargetMachine &TM);
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H A D | Mips16ISelDAGToDAG.h | 23 explicit Mips16DAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {} argument 47 FunctionPass *createMips16ISelDag(MipsTargetMachine &TM);
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H A D | MipsTargetMachine.cpp | 82 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) argument 83 : TargetPassConfig(TM, PM) {} 113 MipsTargetMachine &TM = getMipsTargetMachine(); local 114 addPass(createMipsDelaySlotFillerPass(TM)); 117 if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding()) 118 addPass(createMipsLongBranchPass(TM)); 119 if (TM.getSubtarget<MipsSubtarget>().inMips16Mode()) 120 addPass(createMipsConstantIslandPass(TM));
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H A D | MipsISelDAGToDAG.h | 34 explicit MipsDAGToDAGISel(MipsTargetMachine &TM) argument 35 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {} 89 FunctionPass *createMipsISelDag(MipsTargetMachine &TM);
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H A D | MipsInstrInfo.h | 30 MipsTargetMachine &TM; member in class:llvm::MipsInstrInfo 43 explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc); 45 static const MipsInstrInfo *create(MipsTargetMachine &TM); 107 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM); 108 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCSelectionDAGInfo.h | 25 explicit PPCSelectionDAGInfo(const PPCTargetMachine &TM);
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H A D | PPC.h | 36 FunctionPass *createPPCISelDag(PPCTargetMachine &TM); 37 FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM, 43 ImmutablePass *createPPCTargetTransformInfoPass(const PPCTargetMachine *TM);
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H A D | PPCJITInfo.h | 25 PPCTargetMachine &TM; member in class:llvm::PPCJITInfo 28 PPCJITInfo(PPCTargetMachine &tm, bool tmIs64Bit) : TM(tm) {
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H A D | PPCTargetTransformInfo.cpp | 36 const PPCTargetMachine *TM; member in class:__anon9766::PPCTTI 45 PPCTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) { 49 PPCTTI(const PPCTargetMachine *TM) argument 50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 51 TLI(TM->getTargetLowering()) { 112 llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) { argument 113 return new PPCTTI(TM);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcSelectionDAGInfo.h | 25 explicit SparcSelectionDAGInfo(const SparcTargetMachine &TM);
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/external/llvm/lib/Target/XCore/ |
H A D | XCore.h | 27 FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
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H A D | XCoreSelectionDAGInfo.h | 25 explicit XCoreSelectionDAGInfo(const XCoreTargetMachine &TM);
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/external/llvm/include/llvm/Target/ |
H A D | TargetLoweringObjectFile.h | 52 virtual void Initialize(MCContext &ctx, const TargetMachine &TM); 55 const TargetMachine &TM, 79 const TargetMachine &TM); 86 const TargetMachine &TM) const; 93 const TargetMachine &TM) const { 94 return SectionForGlobal(GV, getKindForGlobal(GV, TM), Mang, TM); 102 Mangler *Mang, const TargetMachine &TM) const = 0; 144 Mangler *Mang, const TargetMachine &TM) const;
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/external/llvm/lib/Target/ARM/ |
H A D | ARM.h | 32 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, 35 FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 49 ImmutablePass *createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUConvertToISA.cpp | 28 TargetMachine &TM; member in class:__anon9767::AMDGPUConvertToISAPass 32 MachineFunctionPass(ID), TM(tm) { } 50 static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo());
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H A D | AMDIL.h | 66 createAMDGPUISelDag(TargetMachine &TM); 68 createAMDGPUPeepholeOpt(TargetMachine &TM); 72 createAMDGPUCFGPreparationPass(TargetMachine &TM); 74 createAMDGPUCFGStructurizerPass(TargetMachine &TM);
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetObjectFile.cpp | 46 X86LinuxTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { argument 47 TargetLoweringObjectFileELF::Initialize(Ctx, TM); 48 InitializeELF(TM.Options.UseInitArray);
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/external/llvm/include/llvm/CodeGen/ |
H A D | TargetLoweringObjectFileImpl.h | 42 const TargetMachine &TM, 52 Mangler *Mang, const TargetMachine &TM) const; 56 Mangler *Mang, const TargetMachine &TM) const; 87 Mangler *Mang, const TargetMachine &TM) const; 91 Mangler *Mang, const TargetMachine &TM) const; 95 Mangler *Mang, const TargetMachine &TM) const; 126 Mangler *Mang, const TargetMachine &TM) const; 130 Mangler *Mang, const TargetMachine &TM) const;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.cpp | 21 &TM) 22 : TargetSelectionDAGInfo(TM) { 20 HexagonSelectionDAGInfo(const HexagonTargetMachine &TM) argument
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/external/llvm/lib/Target/ |
H A D | TargetLoweringObjectFile.cpp | 41 const TargetMachine &TM) { 43 InitMCObjectFileInfo(TM.getTargetTriple(), 44 TM.getRelocationModel(), TM.getCodeModel(), *Ctx); 107 const TargetMachine &TM, 113 /// a global variable. Given an global variable and information from TM, it 118 const TargetMachine &TM){ 122 Reloc::Model ReloModel = TM.getRelocationModel(); 131 if (isSuitableForBSS(GVar, TM.Options.NoZerosInBSS)) 141 if (isSuitableForBSS(GVar, TM 40 Initialize(MCContext &ctx, const TargetMachine &TM) argument 106 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument 117 getKindForGlobal(const GlobalValue *GV, const TargetMachine &TM) argument [all...] |