History log of /external/llvm/lib/Target/ARM/ARM.h
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5 15-Mar-2013 Silviu Baranga <silviu.baranga@arm.com> Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.

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/external/llvm/lib/Target/ARM/ARM.h
54f2187eacaa962fe9b25708c9ea01ec2b19dba3 07-Jan-2013 Jim Grosbach <grosbach@apple.com> ARM: Fix a few copy-paste errors.

s/X86/ARM/

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/external/llvm/lib/Target/ARM/ARM.h
aeef83c6afa1e18d1cf9d359cc678ca0ad556175 07-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

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/external/llvm/lib/Target/ARM/ARM.h
8f50647662560167b88851f92c3c891d2e7c1696 27-Sep-2012 Jush Lu <jush.msn@gmail.com> [arm-fast-isel] Add support for ELF PIC.

This is a preliminary step towards ELF support; currently ARMFastISel hasn't
been used for ELF object files yet.


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/external/llvm/lib/Target/ARM/ARM.h
c1f6f42049696e7357fb4837e1b25dabbaed3fe6 17-Mar-2012 Craig Topper <craig.topper@gmail.com> Reorder includes to match coding standards. Fix an issue or two exposed by that.

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/external/llvm/lib/Target/ARM/ARM.h
9ad012a29c72881623fdfb135f4faa81807ea29b 19-Feb-2012 Jia Liu <proljc@gmail.com> comment fix ARM.h

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/external/llvm/lib/Target/ARM/ARM.h
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

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/external/llvm/lib/Target/ARM/ARM.h
adcb634d85b1372f66dbafe24c026645bc3d447a 29-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Delete NEONMoveFix, now unused.

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/external/llvm/lib/Target/ARM/ARM.h
3511cedf36d0473292b8e8dca0b4eb7576e1064c 29-Sep-2011 Bill Wendling <isanbard@gmail.com> Move to ISelLowering.

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/external/llvm/lib/Target/ARM/ARM.h
0481d29d49cc26a944d0d502360f044cb493a4b5 28-Sep-2011 Bill Wendling <isanbard@gmail.com> This is the start of the new SjLj EH preparation pass, which will replace the
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.


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/external/llvm/lib/Target/ARM/ARM.h
54134708f5debe1631f9ea9b232f78758a2151e4 25-Jul-2011 Evan Cheng <evan.cheng@apple.com> Code clean up.

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/external/llvm/lib/Target/ARM/ARM.h
be74029f44c32efc09274a16cbff588ad10dc5ea 23-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink ARM mc routines into MCTargetDesc.

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/external/llvm/lib/Target/ARM/ARM.h
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


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/external/llvm/lib/Target/ARM/ARM.h
59ee62d2418df8db499eca1ae17f5900dc2dcbba 11-Jul-2011 Evan Cheng <evan.cheng@apple.com> - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.


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/external/llvm/lib/Target/ARM/ARM.h
d7d71a18597e7f3b88055e3f3dde09d8648233ee 22-Jun-2011 Jim Grosbach <grosbach@apple.com> Add missing header.

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/external/llvm/lib/Target/ARM/ARM.h
2fc689888623743502b62e979767dd5c71e692bb 22-Jun-2011 Jim Grosbach <grosbach@apple.com> Move ARMMachObjectWriter to its own file.

Just tidy up a bit. No functional change.


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/external/llvm/lib/Target/ARM/ARM.h
48575f6ea7d5cd21ab29ca370f58fcf9ca31400b 05-Dec-2010 Evan Cheng <evan.cheng@apple.com> Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


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/external/llvm/lib/Target/ARM/ARM.h
baf120fbe8056ef68fc91b16465590fdf2311c27 01-Dec-2010 Jim Grosbach <grosbach@apple.com> Move the ARMAsmPrinter class defintiion into a header file.

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/external/llvm/lib/Target/ARM/ARM.h
30e2cc254be72601b11383dda01f495741ffd56c 14-Nov-2010 Chris Lattner <sabre@nondot.org> rename LowerToMCInst -> LowerARMMachineInstrToMCInst.


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/external/llvm/lib/Target/ARM/ARM.h
1612a619f18cbb328df5b2d8d268dd5e02a4a483 14-Nov-2010 Chris Lattner <sabre@nondot.org> even more simplifications. ARM MCInstLowering is now just
a single function instead of a class. It doesn't need the
complexity that X86 does.


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/external/llvm/lib/Target/ARM/ARM.h
d4d4f4f488d46a9743a0c494b42b22a1b15e0e7d 30-Sep-2010 Jason W Kim <jason.w.kim.2009@gmail.com> I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)

Tested against -r115126



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/external/llvm/lib/Target/ARM/ARM.h
568eeedea72c274abbba1310c18a31eef78e14a4 17-Sep-2010 Jim Grosbach <grosbach@apple.com> Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!



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/external/llvm/lib/Target/ARM/ARM.h
754578b56518d57c28cd439a6dab2b75865e6746 15-Sep-2010 Jim Grosbach <grosbach@apple.com> Factor out basic enums and hleper functions from ARM.h for cleaner sharing
between the compiler back end and the MC libraries.

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/external/llvm/lib/Target/ARM/ARM.h
bd916c54b7989ddbab373c61eb1ed2556ca44d27 14-Sep-2010 Bob Wilson <bob.wilson@apple.com> Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!


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/external/llvm/lib/Target/ARM/ARM.h
5e7044bd0e3921c166d3604d12695e10782913c4 24-Aug-2010 Bill Wendling <isanbard@gmail.com> Add comments for what the condition code symbols mean.

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/external/llvm/lib/Target/ARM/ARM.h
1adc40cac314b0a77b790b094bca146a3a868452 12-Aug-2010 Johnny Chen <johnny.chen@apple.com> Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.


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/external/llvm/lib/Target/ARM/ARM.h
cec36f4c1118dc8388910d4753fe7cbf88d2d793 24-Jul-2010 Anton Korobeynikov <asl@math.spbu.ru> Hook in GlobalMerge pass

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/external/llvm/lib/Target/ARM/ARM.h
dca653951c693edf47437cf0a10d0d0dbb57276d 02-Jul-2010 Evan Cheng <evan.cheng@apple.com> Remove early IT block formation. It's not used.

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/external/llvm/lib/Target/ARM/ARM.h
07f6e805b1e832a2c34a83862cec27736bb471bf 16-Jun-2010 Bob Wilson <bob.wilson@apple.com> Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.


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/external/llvm/lib/Target/ARM/ARM.h
d84712421121744797210a7814aafce8c5377d92 09-Jun-2010 Evan Cheng <evan.cheng@apple.com> Thumb2 IT blocks are fairly expensive. When there are multiple selects using
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.

Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.


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/external/llvm/lib/Target/ARM/ARM.h
de8aa4ed9c8d3654e08eda3973e0500ddc7ac0fd 05-May-2010 Evan Cheng <evan.cheng@apple.com> Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.

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/external/llvm/lib/Target/ARM/ARM.h
4b38debf597a22e2db02aafdaa40264d7770c1ad 07-Apr-2010 Anton Korobeynikov <asl@math.spbu.ru> Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.

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/external/llvm/lib/Target/ARM/ARM.h
1e7b324fe517583eb093854e17f1619324da4582 07-Apr-2010 Anton Korobeynikov <asl@math.spbu.ru> Some initial version of global merger

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/external/llvm/lib/Target/ARM/ARM.h
55fed86353fb39924378dc0e5d29cb273f5e2138 02-Feb-2010 Chris Lattner <sabre@nondot.org> tidy some targets.


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/external/llvm/lib/Target/ARM/ARM.h
e0faa547059c8d10cf34e63ea26a994291116228 02-Feb-2010 Chris Lattner <sabre@nondot.org> remove dead code.


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/external/llvm/lib/Target/ARM/ARM.h
e27d205d5d4d53cceabcd6325533fbdf9c0cee42 02-Dec-2009 Jim Grosbach <grosbach@apple.com> Factor the stack alignment calculations out into a target independent pass.
No functionality change.

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/external/llvm/lib/Target/ARM/ARM.h
a44321776ecd96fa0344335d3027758be3386e45 15-Nov-2009 Jim Grosbach <grosbach@apple.com> Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

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/external/llvm/lib/Target/ARM/ARM.h
b9803a8fa65f043c96612fa9c5aeeee12739db2b 07-Nov-2009 Evan Cheng <evan.cheng@apple.com> - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.


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/external/llvm/lib/Target/ARM/ARM.h
7aaf94bb0dde65e70b417208aaf859f7292a31d1 03-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.

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/external/llvm/lib/Target/ARM/ARM.h
522ce975327e1aeba8317b233cdb54366e2645b5 28-Sep-2009 Bob Wilson <bob.wilson@apple.com> Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.


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/external/llvm/lib/Target/ARM/ARM.h
764ab52dd80310a205c9888bf166d09dab858f90 11-Aug-2009 Jim Grosbach <grosbach@apple.com> Whitespace cleanup. Remove trailing whitespace.

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/external/llvm/lib/Target/ARM/ARM.h
8fb903604e83dfd63659c919042bf2bfed3c940f 08-Aug-2009 Evan Cheng <evan.cheng@apple.com> Code refactoring. No functionality change.

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/external/llvm/lib/Target/ARM/ARM.h
70cd88fb7b5b77f8bbca7417e624d11b6e22a7e7 06-Aug-2009 Bob Wilson <bob.wilson@apple.com> Add a new pre-allocation pass to assign adjacent registers for Neon instructions
that have that constraint. This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.


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/external/llvm/lib/Target/ARM/ARM.h
7f0f2515a01596a2785aca9ee5f630ecc0ab134a 05-Aug-2009 Bob Wilson <bob.wilson@apple.com> Remove a redundant declaration.


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/external/llvm/lib/Target/ARM/ARM.h
0c795d61878156817cedbac51ec2921f2634c1a5 25-Jul-2009 Daniel Dunbar <daniel@zuster.org> Add new helpers for registering targets.
- Less boilerplate == good.


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/external/llvm/lib/Target/ARM/ARM.h
4cb1e13769856716261a4d315f8202bd918502c3 19-Jul-2009 Daniel Dunbar <daniel@zuster.org> Put Target definitions inside Target specific header, and llvm namespace.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
51b198af83cb0080c2709b04c129a3d774c07765 15-Jul-2009 Daniel Dunbar <daniel@zuster.org> Reapply TargetRegistry refactoring commits.

--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
2286f8dc4cec0625f7d7a14e2570926cf8599646 15-Jul-2009 Stuart Hastings <stuart@apple.com> Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
Will revert 75770 in the llvm-gcc trunk.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
4246790aa84a530b0378d917023584c2c7adb4a9 15-Jul-2009 Daniel Dunbar <daniel@zuster.org> Register Target's TargetMachine and AsmPrinter in the new registry.
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
71847813bc419f7a0667468136a07429c6d9f164 14-Jul-2009 David Greene <greened@obbligato.org> Have asm printers use formatted_raw_ostream directly to avoid a
dynamic_cast<>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
c25e7581b9b8088910da31702d4ca21c4734c6d7 11-Jul-2009 Torok Edwin <edwintorok@gmail.com> assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
06e16587ebc81e43b42157fa3afcfd806b59b296 10-Jul-2009 Evan Cheng <evan.cheng@apple.com> Add a thumb2 pass to insert IT blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
ac57e6e498abccb117e0d61c2fa0f733845e50cb 06-Jul-2009 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
cleanup, removed some #includes and moved Object Code Emitter out-of-line.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
5bcc8bd0c60cfe583ee47852950aad9e532c932e 01-Jul-2009 Daniel Dunbar <daniel@zuster.org> Remove unused AsmPrinter OptLevel argument, and propogate.
- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
d49ea77cbc24776142615fecf75f41e191c765bd 26-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Split thumb-related stuff into separate classes.
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
e7d6df73530a98a5cc5f69ddfd17073b464caa57 13-Jun-2009 Evan Cheng <evan.cheng@apple.com> Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
434dd4fd94f5f248492c675e4285e7d67342d4c4 01-Jun-2009 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
a3f99f90338d89354384ca25f53ca4450a1a9d18 30-May-2009 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> First patch in the direction of splitting MachineCodeEmitter in two subclasses:
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
98a366d547772010e94609e4584489b3e5ce0043 30-Apr-2009 Bill Wendling <isanbard@gmail.com> Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b 29-Apr-2009 Bill Wendling <isanbard@gmail.com> Second attempt:

Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
c69d56f1154342a57c9bdd4c17a10333e3520127 28-Apr-2009 Bill Wendling <isanbard@gmail.com> r70270 isn't ready yet. Back this out. Sorry for the noise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
2e9d5f912a9841d3685ba0241abe1131943fed29 28-Apr-2009 Bill Wendling <isanbard@gmail.com> Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
42bf74be1402df7409efbea089310d4c276fde37 25-Mar-2009 Evan Cheng <evan.cheng@apple.com> CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
57f0db833dc30404f1f5d28b23df326e520698ec 24-Feb-2009 Bill Wendling <isanbard@gmail.com> Overhaul my earlier submission due to feedback. It's a large patch, but most of
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
d68a07650cdb2e18f18f362ba533459aa10e01b6 05-Jan-2009 Dan Gohman <gohman@apple.com> Tidy up #includes, deleting a bunch of unnecessary #includes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
309c80adb5ece9c2bcc5fe871a440f9d91e12ef8 08-Oct-2008 Jim Grosbach <grosbach@apple.com> Comment to be explicit that the enumeration values for CondCodes matter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
cb3718832375a581c5ea23f15918f3ea447a446c 21-Aug-2008 Owen Anderson <resistor@mac.com> Use raw_ostream throughout the AsmPrinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
148b6a419fbb20e2224a1b92c499d51513b9bc27 05-Jul-2007 Evan Cheng <evan.cheng@apple.com> Initial ARM JIT support by Raul Fernandes Herbster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
a8e2989ece6dc46df59b0768184028257f913843 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> ARM backend contribution from Apple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
e931a37a4eb3e46d73ab0379dd84173dca1214f2 02-Nov-2006 Rafael Espindola <rafael.espindola@gmail.com> move ARMCondCodeToString to ARMAsmPrinter.cpp
remove unused variables from lowerCall


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
71f3b94fa846114a2ce45645ef262e230737e65e 19-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> Implement a MachineFunctionPass to fix the mul instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
3ad5e5cf998841681e9d11e08eb82a94ddffd1f8 13-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add shifts to addressing mode 1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
5f450d2948ac5bd83a31fbfff89e17b0e2536a80 02-Sep-2006 Rafael Espindola <rafael.espindola@gmail.com> add more condition codes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
cdda88cd1216c146d9ea095561467a9c83f65908 24-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> add the "eq" condition code
implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
6f602de3b68cc63d12554ad6ae3c98a4c436c32d 24-Aug-2006 Rafael Espindola <rafael.espindola@gmail.com> create a generic bcond instruction that has a conditional code argument


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h
7bc59bc3952ad7842b1e079753deb32217a768a3 15-May-2006 Rafael Espindola <rafael.espindola@gmail.com> added a skeleton of the ARM backend


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARM.h