ARM.h revision a44321776ecd96fa0344335d3027758be3386e45 
1//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the entry points for global functions defined in the LLVM
11// ARM back-end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef TARGET_ARM_H
16#define TARGET_ARM_H
17
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Target/TargetMachine.h"
20#include <cassert>
21
22namespace llvm {
23
24class ARMBaseTargetMachine;
25class FunctionPass;
26class MachineCodeEmitter;
27class JITCodeEmitter;
28class ObjectCodeEmitter;
29class formatted_raw_ostream;
30
31// Enums corresponding to ARM condition codes
32namespace ARMCC {
33  // The CondCodes constants map directly to the 4-bit encoding of the
34  // condition field for predicated instructions.
35  enum CondCodes {
36    EQ,
37    NE,
38    HS,
39    LO,
40    MI,
41    PL,
42    VS,
43    VC,
44    HI,
45    LS,
46    GE,
47    LT,
48    GT,
49    LE,
50    AL
51  };
52
53  inline static CondCodes getOppositeCondition(CondCodes CC){
54    switch (CC) {
55    default: llvm_unreachable("Unknown condition code");
56    case EQ: return NE;
57    case NE: return EQ;
58    case HS: return LO;
59    case LO: return HS;
60    case MI: return PL;
61    case PL: return MI;
62    case VS: return VC;
63    case VC: return VS;
64    case HI: return LS;
65    case LS: return HI;
66    case GE: return LT;
67    case LT: return GE;
68    case GT: return LE;
69    case LE: return GT;
70    }
71  }
72}
73
74inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
75  switch (CC) {
76  default: llvm_unreachable("Unknown condition code");
77  case ARMCC::EQ:  return "eq";
78  case ARMCC::NE:  return "ne";
79  case ARMCC::HS:  return "hs";
80  case ARMCC::LO:  return "lo";
81  case ARMCC::MI:  return "mi";
82  case ARMCC::PL:  return "pl";
83  case ARMCC::VS:  return "vs";
84  case ARMCC::VC:  return "vc";
85  case ARMCC::HI:  return "hi";
86  case ARMCC::LS:  return "ls";
87  case ARMCC::GE:  return "ge";
88  case ARMCC::LT:  return "lt";
89  case ARMCC::GT:  return "gt";
90  case ARMCC::LE:  return "le";
91  case ARMCC::AL:  return "al";
92  }
93}
94
95FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
96                               CodeGenOpt::Level OptLevel);
97
98FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
99                                       MachineCodeEmitter &MCE);
100FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
101                                          JITCodeEmitter &JCE);
102FunctionPass *createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
103                                             ObjectCodeEmitter &OCE);
104
105FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
106FunctionPass *createARMExpandPseudoPass();
107FunctionPass *createARMConstantIslandPass();
108FunctionPass *createNEONPreAllocPass();
109FunctionPass *createNEONMoveFixPass();
110FunctionPass *createThumb2ITBlockPass();
111FunctionPass *createThumb2SizeReductionPass();
112FunctionPass *createARMMaxStackAlignmentCalculatorPass();
113
114extern Target TheARMTarget, TheThumbTarget;
115
116} // end namespace llvm;
117
118// Defines symbolic names for ARM registers.  This defines a mapping from
119// register name to register number.
120//
121#include "ARMGenRegisterNames.inc"
122
123// Defines symbolic names for the ARM instructions.
124//
125#include "ARMGenInstrNames.inc"
126
127
128#endif
129