ARM.h revision 3ad5e5cf998841681e9d11e08eb82a94ddffd1f8 
1//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the entry points for global functions defined in the LLVM
12// ARM back-end.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef TARGET_ARM_H
17#define TARGET_ARM_H
18
19#include <iosfwd>
20#include <cassert>
21
22namespace llvm {
23  // Enums corresponding to ARM condition codes
24  namespace ARMCC {
25    enum CondCodes {
26      EQ,
27      NE,
28      CS,
29      CC,
30      MI,
31      PL,
32      VS,
33      VC,
34      HI,
35      LS,
36      GE,
37      LT,
38      GT,
39      LE,
40      AL
41    };
42  }
43
44  namespace ARMShift {
45    enum ShiftTypes {
46      LSL,
47      LSR,
48      ASR,
49      ROR,
50      RRX
51    };
52  }
53
54  static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
55    switch (CC) {
56    default: assert(0 && "Unknown condition code");
57    case ARMCC::EQ:  return "eq";
58    case ARMCC::NE:  return "ne";
59    case ARMCC::CS:  return "cs";
60    case ARMCC::CC:  return "cc";
61    case ARMCC::MI:  return "mi";
62    case ARMCC::PL:  return "pl";
63    case ARMCC::VS:  return "vs";
64    case ARMCC::VC:  return "vc";
65    case ARMCC::HI:  return "hi";
66    case ARMCC::LS:  return "ls";
67    case ARMCC::GE:  return "ge";
68    case ARMCC::LT:  return "lt";
69    case ARMCC::GT:  return "gt";
70    case ARMCC::LE:  return "le";
71    case ARMCC::AL:  return "al";
72    }
73  }
74
75  class FunctionPass;
76  class TargetMachine;
77
78  FunctionPass *createARMISelDag(TargetMachine &TM);
79  FunctionPass *createARMCodePrinterPass(std::ostream &OS, TargetMachine &TM);
80} // end namespace llvm;
81
82// Defines symbolic names for ARM registers.  This defines a mapping from
83// register name to register number.
84//
85#include "ARMGenRegisterNames.inc"
86
87// Defines symbolic names for the ARM instructions.
88//
89#include "ARMGenInstrNames.inc"
90
91
92#endif
93