/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.h | 28 NVPTXTargetMachine &TM; member in class:llvm::NVPTXInstrInfo 31 explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
|
H A D | NVPTXTargetMachine.cpp | 104 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM) argument 105 : TargetPassConfig(TM, PM) {}
|
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.h | 26 const X86TargetMachine &TM; member in class:llvm::X86FrameLowering 33 TM(tm), STI(sti) {
|
H A D | X86PadShortFunction.cpp | 52 , Threshold(4), TM(0), TII(0) {} 80 const TargetMachine *TM; member in struct:__anon9842::PadShortFunc 102 TM = &MF.getTarget(); 103 TII = TM->getInstrInfo(); 193 CyclesToEnd += TII->getInstrLatency(TM->getInstrItineraryData(), MI);
|
H A D | X86JITInfo.h | 26 X86TargetMachine &TM; member in class:llvm::X86JITInfo
|
H A D | X86SelectionDAGInfo.h | 33 explicit X86SelectionDAGInfo(const X86TargetMachine &TM);
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreTargetObjectFile.cpp | 19 void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ argument 20 TargetLoweringObjectFileELF::Initialize(Ctx, TM);
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 104 const ARMTargetMachine *TM = local 106 if (TM->getRelocationModel() != Reloc::PIC_) 115 unsigned Align = TM->getDataLayout()->getPrefTypeAlignment(GV->getType()); 122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? 124 const TargetInstrInfo &TII = *TM->getInstrInfo();
|
H A D | ARMAsmPrinter.h | 47 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 48 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL), InConstantPool(false) { 49 Subtarget = &TM.getSubtarget<ARMSubtarget>();
|
H A D | ARMSelectionDAGInfo.h | 44 explicit ARMSelectionDAGInfo(const TargetMachine &TM);
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 41 HexagonCFGOptimizer(HexagonTargetMachine& TM) : MachineFunctionPass(ID), argument 42 QTM(TM), 43 QST(*TM.getSubtargetImpl()) {} 234 FunctionPass *llvm::createHexagonCFGOptimizer(HexagonTargetMachine &TM) { argument 235 return new HexagonCFGOptimizer(TM);
|
/external/llvm/lib/Target/Sparc/ |
H A D | FPMover.cpp | 35 TargetMachine &TM; member in struct:__anon9790::FPMover 39 : MachineFunctionPass(ID), TM(tm) { } 105 const TargetInstrInfo *TII = TM.getInstrInfo(); 120 MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) 133 if (TM.getSubtarget<SparcSubtarget>().isV9())
|
H A D | SparcTargetMachine.cpp | 46 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) argument 47 : TargetPassConfig(TM, PM) {}
|
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 49 /// TM - Keep a reference to MBlazeTargetMachine. 50 MBlazeTargetMachine &TM; member in class:__anon9715::MBlazeDAGToDAGISel 59 TM(tm), Subtarget(tm.getSubtarget<MBlazeSubtarget>()) {} 72 return static_cast<const MBlazeTargetMachine &>(TM); 172 Disp = CurDAG->getTargetConstant(0, TM.getTargetLowering()->getPointerTy()); 225 if (TM.getRelocationModel() == Reloc::PIC_) { 275 FunctionPass *llvm::createMBlazeISelDag(MBlazeTargetMachine &TM) { argument 276 return new MBlazeDAGToDAGISel(TM);
|
H A D | MBlazeAsmPrinter.cpp | 52 explicit MBlazeAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 53 : AsmPrinter(TM, Streamer) { 54 Subtarget = &TM.getSubtarget<MBlazeSubtarget>(); 126 const TargetFrameLowering *TFI = TM.getFrameLowering(); 127 const TargetRegisterInfo &RI = *TM.getRegisterInfo(); 158 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
|
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInst.cpp | 22 unsigned HexagonMCInst::getUnits(const HexagonTargetMachine* TM) const { 23 const HexagonInstrInfo* QII = TM->getInstrInfo(); 24 const InstrItineraryData* II = TM->getInstrItineraryData();
|
H A D | HexagonMCInst.h | 45 unsigned getUnits(const HexagonTargetMachine* TM) const;
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 68 PPCTargetMachine &TM; member in class:llvm::PPCInstrInfo 82 explicit PPCInstrInfo(PPCTargetMachine &TM); 91 CreateTargetHazardRecognizer(const TargetMachine *TM,
|
H A D | PPCSubtarget.cpp | 111 const TargetMachine &TM) const { 113 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
|
H A D | PPCCodeEmitter.cpp | 31 TargetMachine &TM; member in class:__anon9759::PPCCodeEmitter 48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {} 89 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, argument 91 return new PPCCodeEmitter(TM, JCE); 130 assert(TM.getRelocationModel() == Reloc::PIC_); 156 if (TM.getRelocationModel() == Reloc::PIC_) {
|
/external/llvm/include/llvm/CodeGen/ |
H A D | Passes.h | 65 TargetMachine *TM; member in class:llvm::TargetPassConfig 88 return *static_cast<TMC*>(TM); 92 return TM->getTargetLowering(); 98 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.h | 22 explicit MipsSETargetLowering(MipsTargetMachine &TM);
|
/external/llvm/lib/Target/R600/ |
H A D | AMDGPURegisterInfo.cpp | 23 TM(tm),
|
H A D | AMDGPURegisterInfo.h | 32 TargetMachine &TM; member in struct:llvm::AMDGPURegisterInfo
|
/external/valgrind/main/exp-bbv/tests/amd64-linux/ |
H A D | ll.stdout.exp | 15 [2CTwo 3200MHz Intel(R) Xeon(TM) Processors, 2048M RAM, 6934.38 Bogomips Total
|