1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares codegen opcodes and related utilities. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_ISDOPCODES_H 15#define LLVM_CODEGEN_ISDOPCODES_H 16 17namespace llvm { 18 19/// ISD namespace - This namespace contains an enum which represents all of the 20/// SelectionDAG node types and value types. 21/// 22namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 76 /// first (possible) on-stack argument. This is needed for correct stack 77 /// adjustment during unwind. 78 FRAME_TO_ARGS_OFFSET, 79 80 /// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the 81 /// address of the exception block on entry to an landing pad block. 82 EXCEPTIONADDR, 83 84 /// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the 85 /// address of the Language Specific Data Area for the enclosing function. 86 LSDAADDR, 87 88 /// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node 89 /// represents the selection index of the exception thrown. 90 EHSELECTION, 91 92 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 93 /// 'eh_return' gcc dwarf builtin, which is used to return from 94 /// exception. The general meaning is: adjust stack by OFFSET and pass 95 /// execution to HANDLER. Many platform-related details also :) 96 EH_RETURN, 97 98 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 99 /// This corresponds to the eh.sjlj.setjmp intrinsic. 100 /// It takes an input chain and a pointer to the jump buffer as inputs 101 /// and returns an outchain. 102 EH_SJLJ_SETJMP, 103 104 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 105 /// This corresponds to the eh.sjlj.longjmp intrinsic. 106 /// It takes an input chain and a pointer to the jump buffer as inputs 107 /// and returns an outchain. 108 EH_SJLJ_LONGJMP, 109 110 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 111 /// simplification, or lowering of the constant. They are used for constants 112 /// which are known to fit in the immediate fields of their users, or for 113 /// carrying magic numbers which are not values which need to be 114 /// materialized in registers. 115 TargetConstant, 116 TargetConstantFP, 117 118 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 119 /// anything else with this node, and this is valid in the target-specific 120 /// dag, turning into a GlobalAddress operand. 121 TargetGlobalAddress, 122 TargetGlobalTLSAddress, 123 TargetFrameIndex, 124 TargetJumpTable, 125 TargetConstantPool, 126 TargetExternalSymbol, 127 TargetBlockAddress, 128 129 /// TargetIndex - Like a constant pool entry, but with completely 130 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 131 /// 64-bit index. Targets can use this however they like. 132 TargetIndex, 133 134 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 135 /// This node represents a target intrinsic function with no side effects. 136 /// The first operand is the ID number of the intrinsic from the 137 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 138 /// node returns the result of the intrinsic. 139 INTRINSIC_WO_CHAIN, 140 141 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 142 /// This node represents a target intrinsic function with side effects that 143 /// returns a result. The first operand is a chain pointer. The second is 144 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 145 /// operands to the intrinsic follow. The node has two results, the result 146 /// of the intrinsic and an output chain. 147 INTRINSIC_W_CHAIN, 148 149 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 150 /// This node represents a target intrinsic function with side effects that 151 /// does not return a result. The first operand is a chain pointer. The 152 /// second is the ID number of the intrinsic from the llvm::Intrinsic 153 /// namespace. The operands to the intrinsic follow. 154 INTRINSIC_VOID, 155 156 /// CopyToReg - This node has three operands: a chain, a register number to 157 /// set to this value, and a value. 158 CopyToReg, 159 160 /// CopyFromReg - This node indicates that the input value is a virtual or 161 /// physical register that is defined outside of the scope of this 162 /// SelectionDAG. The register is available from the RegisterSDNode object. 163 CopyFromReg, 164 165 /// UNDEF - An undefined node. 166 UNDEF, 167 168 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 169 /// a Constant, which is required to be operand #1) half of the integer or 170 /// float value specified as operand #0. This is only for use before 171 /// legalization, for values that will be broken into multiple registers. 172 EXTRACT_ELEMENT, 173 174 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 175 /// Given two values of the same integer value type, this produces a value 176 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 177 /// legalization. 178 BUILD_PAIR, 179 180 /// MERGE_VALUES - This node takes multiple discrete operands and returns 181 /// them all as its individual results. This nodes has exactly the same 182 /// number of inputs and outputs. This node is useful for some pieces of the 183 /// code generator that want to think about a single node with multiple 184 /// results, not multiple nodes. 185 MERGE_VALUES, 186 187 /// Simple integer binary arithmetic operators. 188 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 189 190 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 191 /// a signed/unsigned value of type i[2*N], and return the full value as 192 /// two results, each of type iN. 193 SMUL_LOHI, UMUL_LOHI, 194 195 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 196 /// remainder result. 197 SDIVREM, UDIVREM, 198 199 /// CARRY_FALSE - This node is used when folding other nodes, 200 /// like ADDC/SUBC, which indicate the carry result is always false. 201 CARRY_FALSE, 202 203 /// Carry-setting nodes for multiple precision addition and subtraction. 204 /// These nodes take two operands of the same value type, and produce two 205 /// results. The first result is the normal add or sub result, the second 206 /// result is the carry flag result. 207 ADDC, SUBC, 208 209 /// Carry-using nodes for multiple precision addition and subtraction. These 210 /// nodes take three operands: The first two are the normal lhs and rhs to 211 /// the add or sub, and the third is the input carry flag. These nodes 212 /// produce two results; the normal result of the add or sub, and the output 213 /// carry flag. These nodes both read and write a carry flag to allow them 214 /// to them to be chained together for add and sub of arbitrarily large 215 /// values. 216 ADDE, SUBE, 217 218 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 219 /// These nodes take two operands: the normal LHS and RHS to the add. They 220 /// produce two results: the normal result of the add, and a boolean that 221 /// indicates if an overflow occurred (*not* a flag, because it may be store 222 /// to memory, etc.). If the type of the boolean is not i1 then the high 223 /// bits conform to getBooleanContents. 224 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 225 SADDO, UADDO, 226 227 /// Same for subtraction. 228 SSUBO, USUBO, 229 230 /// Same for multiplication. 231 SMULO, UMULO, 232 233 /// Simple binary floating point operators. 234 FADD, FSUB, FMUL, FMA, FDIV, FREM, 235 236 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 237 /// DAG node does not require that X and Y have the same type, just that the 238 /// are both floating point. X and the result must have the same type. 239 /// FCOPYSIGN(f32, f64) is allowed. 240 FCOPYSIGN, 241 242 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 243 /// value as an integer 0/1 value. 244 FGETSIGN, 245 246 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 247 /// specified, possibly variable, elements. The number of elements is 248 /// required to be a power of two. The types of the operands must all be 249 /// the same and must match the vector element type, except that integer 250 /// types are allowed to be larger than the element type, in which case 251 /// the operands are implicitly truncated. 252 BUILD_VECTOR, 253 254 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 255 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 256 /// element type then VAL is truncated before replacement. 257 INSERT_VECTOR_ELT, 258 259 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 260 /// identified by the (potentially variable) element number IDX. If the 261 /// return type is an integer type larger than the element type of the 262 /// vector, the result is extended to the width of the return type. 263 EXTRACT_VECTOR_ELT, 264 265 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 266 /// vector type with the same length and element type, this produces a 267 /// concatenated vector result value, with length equal to the sum of the 268 /// lengths of the input vectors. 269 CONCAT_VECTORS, 270 271 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 272 /// with VECTOR2 inserted into VECTOR1 at the (potentially 273 /// variable) element number IDX, which must be a multiple of the 274 /// VECTOR2 vector length. The elements of VECTOR1 starting at 275 /// IDX are overwritten with VECTOR2. Elements IDX through 276 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 277 INSERT_SUBVECTOR, 278 279 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 280 /// vector value) starting with the element number IDX, which must be a 281 /// constant multiple of the result vector length. 282 EXTRACT_SUBVECTOR, 283 284 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 285 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 286 /// values that indicate which value (or undef) each result element will 287 /// get. These constant ints are accessible through the 288 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 289 /// 'vperm' instruction, except that the indices must be constants and are 290 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 291 VECTOR_SHUFFLE, 292 293 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 294 /// scalar value into element 0 of the resultant vector type. The top 295 /// elements 1 to N-1 of the N-element vector are undefined. The type 296 /// of the operand must match the vector element type, except when they 297 /// are integer types. In this case the operand is allowed to be wider 298 /// than the vector element type, and is implicitly truncated to it. 299 SCALAR_TO_VECTOR, 300 301 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 302 /// producing an unsigned/signed value of type i[2*N], then return the top 303 /// part. 304 MULHU, MULHS, 305 306 /// Bitwise operators - logical and, logical or, logical xor. 307 AND, OR, XOR, 308 309 /// Shift and rotation operations. After legalization, the type of the 310 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 311 /// the shift amount can be any type, but care must be taken to ensure it is 312 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 313 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 314 /// to represent the shift amount. 315 /// When the 1st operand is a vector, the shift amount must be in the same 316 /// type. (TLI.getShiftAmountTy() will return the same type when the input 317 /// type is a vector.) 318 SHL, SRA, SRL, ROTL, ROTR, 319 320 /// Byte Swap and Counting operators. 321 BSWAP, CTTZ, CTLZ, CTPOP, 322 323 /// Bit counting operators with an undefined result for zero inputs. 324 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 325 326 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 327 /// i1 then the high bits must conform to getBooleanContents. 328 SELECT, 329 330 /// Select with a vector condition (op #0) and two vector operands (ops #1 331 /// and #2), returning a vector result. All vectors have the same length. 332 /// Much like the scalar select and setcc, each bit in the condition selects 333 /// whether the corresponding result element is taken from op #1 or op #2. 334 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 335 /// change the condition type in order to match the VSELECT node using a 336 /// pattern. The condition follows the BooleanContent format of the target. 337 VSELECT, 338 339 /// Select with condition operator - This selects between a true value and 340 /// a false value (ops #2 and #3) based on the boolean result of comparing 341 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 342 /// condition code in op #4, a CondCodeSDNode. 343 SELECT_CC, 344 345 /// SetCC operator - This evaluates to a true value iff the condition is 346 /// true. If the result value type is not i1 then the high bits conform 347 /// to getBooleanContents. The operands to this are the left and right 348 /// operands to compare (ops #0, and #1) and the condition code to compare 349 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 350 /// then the result type must also be a vector type. 351 SETCC, 352 353 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 354 /// integer shift operations, just like ADD/SUB_PARTS. The operation 355 /// ordering is: 356 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 357 SHL_PARTS, SRA_PARTS, SRL_PARTS, 358 359 /// Conversion operators. These are all single input single output 360 /// operations. For all of these, the result type must be strictly 361 /// wider or narrower (depending on the operation) than the source 362 /// type. 363 364 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 365 /// into new bits. 366 SIGN_EXTEND, 367 368 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 369 ZERO_EXTEND, 370 371 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 372 ANY_EXTEND, 373 374 /// TRUNCATE - Completely drop the high bits. 375 TRUNCATE, 376 377 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 378 /// depends on the first letter) to floating point. 379 SINT_TO_FP, 380 UINT_TO_FP, 381 382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 383 /// sign extend a small value in a large integer register (e.g. sign 384 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 385 /// with the 7th bit). The size of the smaller type is indicated by the 1th 386 /// operand, a ValueType node. 387 SIGN_EXTEND_INREG, 388 389 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 390 /// integer. 391 FP_TO_SINT, 392 FP_TO_UINT, 393 394 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 395 /// down to the precision of the destination VT. TRUNC is a flag, which is 396 /// always an integer that is zero or one. If TRUNC is 0, this is a 397 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 398 /// value of Y. 399 /// 400 /// The TRUNC = 1 case is used in cases where we know that the value will 401 /// not be modified by the node, because Y is not using any of the extra 402 /// precision of source type. This allows certain transformations like 403 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 404 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 405 FP_ROUND, 406 407 /// FLT_ROUNDS_ - Returns current rounding mode: 408 /// -1 Undefined 409 /// 0 Round to 0 410 /// 1 Round to nearest 411 /// 2 Round to +inf 412 /// 3 Round to -inf 413 FLT_ROUNDS_, 414 415 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 416 /// rounds it to a floating point value. It then promotes it and returns it 417 /// in a register of the same size. This operation effectively just 418 /// discards excess precision. The type to round down to is specified by 419 /// the VT operand, a VTSDNode. 420 FP_ROUND_INREG, 421 422 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 423 FP_EXTEND, 424 425 /// BITCAST - This operator converts between integer, vector and FP 426 /// values, as if the value was stored to memory with one type and loaded 427 /// from the same address with the other type (or equivalently for vector 428 /// format conversions, etc). The source and result are required to have 429 /// the same bit size (e.g. f32 <-> i32). This can also be used for 430 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 431 /// getNode(). 432 BITCAST, 433 434 /// CONVERT_RNDSAT - This operator is used to support various conversions 435 /// between various types (float, signed, unsigned and vectors of those 436 /// types) with rounding and saturation. NOTE: Avoid using this operator as 437 /// most target don't support it and the operator might be removed in the 438 /// future. It takes the following arguments: 439 /// 0) value 440 /// 1) dest type (type to convert to) 441 /// 2) src type (type to convert from) 442 /// 3) rounding imm 443 /// 4) saturation imm 444 /// 5) ISD::CvtCode indicating the type of conversion to do 445 CONVERT_RNDSAT, 446 447 /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform 448 /// promotions and truncation for half-precision (16 bit) floating 449 /// numbers. We need special nodes since FP16 is a storage-only type with 450 /// special semantics of operations. 451 FP16_TO_FP32, FP32_TO_FP16, 452 453 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 454 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 455 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary 456 /// floating point operations. These are inspired by libm. 457 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 458 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 459 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, 460 461 /// FSINCOS - Compute both fsin and fcos as a single operation. 462 FSINCOS, 463 464 /// LOAD and STORE have token chains as their first operand, then the same 465 /// operands as an LLVM load/store instruction, then an offset node that 466 /// is added / subtracted from the base pointer to form the address (for 467 /// indexed memory ops). 468 LOAD, STORE, 469 470 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 471 /// to a specified boundary. This node always has two return values: a new 472 /// stack pointer value and a chain. The first operand is the token chain, 473 /// the second is the number of bytes to allocate, and the third is the 474 /// alignment boundary. The size is guaranteed to be a multiple of the 475 /// stack alignment, and the alignment is guaranteed to be bigger than the 476 /// stack alignment (if required) or 0 to get standard stack alignment. 477 DYNAMIC_STACKALLOC, 478 479 /// Control flow instructions. These all have token chains. 480 481 /// BR - Unconditional branch. The first operand is the chain 482 /// operand, the second is the MBB to branch to. 483 BR, 484 485 /// BRIND - Indirect branch. The first operand is the chain, the second 486 /// is the value to branch to, which must be of the same type as the 487 /// target's pointer type. 488 BRIND, 489 490 /// BR_JT - Jumptable branch. The first operand is the chain, the second 491 /// is the jumptable index, the last one is the jumptable entry index. 492 BR_JT, 493 494 /// BRCOND - Conditional branch. The first operand is the chain, the 495 /// second is the condition, the third is the block to branch to if the 496 /// condition is true. If the type of the condition is not i1, then the 497 /// high bits must conform to getBooleanContents. 498 BRCOND, 499 500 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 501 /// that the condition is represented as condition code, and two nodes to 502 /// compare, rather than as a combined SetCC node. The operands in order 503 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 504 BR_CC, 505 506 /// INLINEASM - Represents an inline asm block. This node always has two 507 /// return values: a chain and a flag result. The inputs are as follows: 508 /// Operand #0 : Input chain. 509 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 510 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 511 /// Operand #3 : HasSideEffect, IsAlignStack bits. 512 /// After this, it is followed by a list of operands with this format: 513 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 514 /// of operands that follow, etc. See InlineAsm.h. 515 /// ... however many operands ... 516 /// Operand #last: Optional, an incoming flag. 517 /// 518 /// The variable width operands are required to represent target addressing 519 /// modes as a single "operand", even though they may have multiple 520 /// SDOperands. 521 INLINEASM, 522 523 /// EH_LABEL - Represents a label in mid basic block used to track 524 /// locations needed for debug and exception handling tables. These nodes 525 /// take a chain as input and return a chain. 526 EH_LABEL, 527 528 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 529 /// value, the same type as the pointer type for the system, and an output 530 /// chain. 531 STACKSAVE, 532 533 /// STACKRESTORE has two operands, an input chain and a pointer to restore 534 /// to it returns an output chain. 535 STACKRESTORE, 536 537 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 538 /// of a call sequence, and carry arbitrary information that target might 539 /// want to know. The first operand is a chain, the rest are specified by 540 /// the target and not touched by the DAG optimizers. 541 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 542 CALLSEQ_START, // Beginning of a call sequence 543 CALLSEQ_END, // End of a call sequence 544 545 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 546 /// and the alignment. It returns a pair of values: the vaarg value and a 547 /// new chain. 548 VAARG, 549 550 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 551 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 552 /// source. 553 VACOPY, 554 555 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 556 /// pointer, and a SRCVALUE. 557 VAEND, VASTART, 558 559 /// SRCVALUE - This is a node type that holds a Value* that is used to 560 /// make reference to a value in the LLVM IR. 561 SRCVALUE, 562 563 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 564 /// reference metadata in the IR. 565 MDNODE_SDNODE, 566 567 /// PCMARKER - This corresponds to the pcmarker intrinsic. 568 PCMARKER, 569 570 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 571 /// The only operand is a chain and a value and a chain are produced. The 572 /// value is the contents of the architecture specific cycle counter like 573 /// register (or other high accuracy low latency clock source) 574 READCYCLECOUNTER, 575 576 /// HANDLENODE node - Used as a handle for various purposes. 577 HANDLENODE, 578 579 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 580 /// takes as input a token chain, the pointer to the trampoline, the pointer 581 /// to the nested function, the pointer to pass for the 'nest' parameter, a 582 /// SRCVALUE for the trampoline and another for the nested function 583 /// (allowing targets to access the original Function*). 584 /// It produces a token chain as output. 585 INIT_TRAMPOLINE, 586 587 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 588 /// It takes a pointer to the trampoline and produces a (possibly) new 589 /// pointer to the same trampoline with platform-specific adjustments 590 /// applied. The pointer it returns points to an executable block of code. 591 ADJUST_TRAMPOLINE, 592 593 /// TRAP - Trapping instruction 594 TRAP, 595 596 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 597 DEBUGTRAP, 598 599 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 600 /// is the chain. The other operands are the address to prefetch, 601 /// read / write specifier, locality specifier and instruction / data cache 602 /// specifier. 603 PREFETCH, 604 605 /// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, 606 /// store-store, device) 607 /// This corresponds to the memory.barrier intrinsic. 608 /// it takes an input chain, 4 operands to specify the type of barrier, an 609 /// operand specifying if the barrier applies to device and uncached memory 610 /// and produces an output chain. 611 MEMBARRIER, 612 613 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 614 /// This corresponds to the fence instruction. It takes an input chain, and 615 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 616 ATOMIC_FENCE, 617 618 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 619 /// This corresponds to "load atomic" instruction. 620 ATOMIC_LOAD, 621 622 /// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) 623 /// This corresponds to "store atomic" instruction. 624 ATOMIC_STORE, 625 626 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 627 /// This corresponds to the cmpxchg instruction. 628 ATOMIC_CMP_SWAP, 629 630 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 631 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 632 /// These correspond to the atomicrmw instruction. 633 ATOMIC_SWAP, 634 ATOMIC_LOAD_ADD, 635 ATOMIC_LOAD_SUB, 636 ATOMIC_LOAD_AND, 637 ATOMIC_LOAD_OR, 638 ATOMIC_LOAD_XOR, 639 ATOMIC_LOAD_NAND, 640 ATOMIC_LOAD_MIN, 641 ATOMIC_LOAD_MAX, 642 ATOMIC_LOAD_UMIN, 643 ATOMIC_LOAD_UMAX, 644 645 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 646 /// is the chain and the second operand is the alloca pointer. 647 LIFETIME_START, LIFETIME_END, 648 649 /// BUILTIN_OP_END - This must be the last enum value in this list. 650 /// The target-specific pre-isel opcode values start here. 651 BUILTIN_OP_END 652 }; 653 654 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 655 /// which do not reference a specific memory location should be less than 656 /// this value. Those that do must not be less than this value, and can 657 /// be used with SelectionDAG::getMemIntrinsicNode. 658 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150; 659 660 //===--------------------------------------------------------------------===// 661 /// MemIndexedMode enum - This enum defines the load / store indexed 662 /// addressing modes. 663 /// 664 /// UNINDEXED "Normal" load / store. The effective address is already 665 /// computed and is available in the base pointer. The offset 666 /// operand is always undefined. In addition to producing a 667 /// chain, an unindexed load produces one value (result of the 668 /// load); an unindexed store does not produce a value. 669 /// 670 /// PRE_INC Similar to the unindexed mode where the effective address is 671 /// PRE_DEC the value of the base pointer add / subtract the offset. 672 /// It considers the computation as being folded into the load / 673 /// store operation (i.e. the load / store does the address 674 /// computation as well as performing the memory transaction). 675 /// The base operand is always undefined. In addition to 676 /// producing a chain, pre-indexed load produces two values 677 /// (result of the load and the result of the address 678 /// computation); a pre-indexed store produces one value (result 679 /// of the address computation). 680 /// 681 /// POST_INC The effective address is the value of the base pointer. The 682 /// POST_DEC value of the offset operand is then added to / subtracted 683 /// from the base after memory transaction. In addition to 684 /// producing a chain, post-indexed load produces two values 685 /// (the result of the load and the result of the base +/- offset 686 /// computation); a post-indexed store produces one value (the 687 /// the result of the base +/- offset computation). 688 enum MemIndexedMode { 689 UNINDEXED = 0, 690 PRE_INC, 691 PRE_DEC, 692 POST_INC, 693 POST_DEC, 694 LAST_INDEXED_MODE 695 }; 696 697 //===--------------------------------------------------------------------===// 698 /// LoadExtType enum - This enum defines the three variants of LOADEXT 699 /// (load with extension). 700 /// 701 /// SEXTLOAD loads the integer operand and sign extends it to a larger 702 /// integer result type. 703 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 704 /// integer result type. 705 /// EXTLOAD is used for two things: floating point extending loads and 706 /// integer extending loads [the top bits are undefined]. 707 enum LoadExtType { 708 NON_EXTLOAD = 0, 709 EXTLOAD, 710 SEXTLOAD, 711 ZEXTLOAD, 712 LAST_LOADEXT_TYPE 713 }; 714 715 //===--------------------------------------------------------------------===// 716 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 717 /// below work out, when considering SETFALSE (something that never exists 718 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 719 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 720 /// to. If the "N" column is 1, the result of the comparison is undefined if 721 /// the input is a NAN. 722 /// 723 /// All of these (except for the 'always folded ops') should be handled for 724 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 725 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 726 /// 727 /// Note that these are laid out in a specific order to allow bit-twiddling 728 /// to transform conditions. 729 enum CondCode { 730 // Opcode N U L G E Intuitive operation 731 SETFALSE, // 0 0 0 0 Always false (always folded) 732 SETOEQ, // 0 0 0 1 True if ordered and equal 733 SETOGT, // 0 0 1 0 True if ordered and greater than 734 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 735 SETOLT, // 0 1 0 0 True if ordered and less than 736 SETOLE, // 0 1 0 1 True if ordered and less than or equal 737 SETONE, // 0 1 1 0 True if ordered and operands are unequal 738 SETO, // 0 1 1 1 True if ordered (no nans) 739 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 740 SETUEQ, // 1 0 0 1 True if unordered or equal 741 SETUGT, // 1 0 1 0 True if unordered or greater than 742 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 743 SETULT, // 1 1 0 0 True if unordered or less than 744 SETULE, // 1 1 0 1 True if unordered, less than, or equal 745 SETUNE, // 1 1 1 0 True if unordered or not equal 746 SETTRUE, // 1 1 1 1 Always true (always folded) 747 // Don't care operations: undefined if the input is a nan. 748 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 749 SETEQ, // 1 X 0 0 1 True if equal 750 SETGT, // 1 X 0 1 0 True if greater than 751 SETGE, // 1 X 0 1 1 True if greater than or equal 752 SETLT, // 1 X 1 0 0 True if less than 753 SETLE, // 1 X 1 0 1 True if less than or equal 754 SETNE, // 1 X 1 1 0 True if not equal 755 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 756 757 SETCC_INVALID // Marker value. 758 }; 759 760 /// isSignedIntSetCC - Return true if this is a setcc instruction that 761 /// performs a signed comparison when used with integer operands. 762 inline bool isSignedIntSetCC(CondCode Code) { 763 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 764 } 765 766 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 767 /// performs an unsigned comparison when used with integer operands. 768 inline bool isUnsignedIntSetCC(CondCode Code) { 769 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 770 } 771 772 /// isTrueWhenEqual - Return true if the specified condition returns true if 773 /// the two operands to the condition are equal. Note that if one of the two 774 /// operands is a NaN, this value is meaningless. 775 inline bool isTrueWhenEqual(CondCode Cond) { 776 return ((int)Cond & 1) != 0; 777 } 778 779 /// getUnorderedFlavor - This function returns 0 if the condition is always 780 /// false if an operand is a NaN, 1 if the condition is always true if the 781 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 782 /// NaN. 783 inline unsigned getUnorderedFlavor(CondCode Cond) { 784 return ((int)Cond >> 3) & 3; 785 } 786 787 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 788 /// 'op' is a valid SetCC operation. 789 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 790 791 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 792 /// when given the operation for (X op Y). 793 CondCode getSetCCSwappedOperands(CondCode Operation); 794 795 /// getSetCCOrOperation - Return the result of a logical OR between different 796 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 797 /// function returns SETCC_INVALID if it is not possible to represent the 798 /// resultant comparison. 799 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 800 801 /// getSetCCAndOperation - Return the result of a logical AND between 802 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 803 /// function returns SETCC_INVALID if it is not possible to represent the 804 /// resultant comparison. 805 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 806 807 //===--------------------------------------------------------------------===// 808 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 809 /// supports. 810 enum CvtCode { 811 CVT_FF, /// Float from Float 812 CVT_FS, /// Float from Signed 813 CVT_FU, /// Float from Unsigned 814 CVT_SF, /// Signed from Float 815 CVT_UF, /// Unsigned from Float 816 CVT_SS, /// Signed from Signed 817 CVT_SU, /// Signed from Unsigned 818 CVT_US, /// Unsigned from Signed 819 CVT_UU, /// Unsigned from Unsigned 820 CVT_INVALID /// Marker - Invalid opcode 821 }; 822 823} // end llvm::ISD namespace 824 825} // end llvm namespace 826 827#endif 828