1518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===// 2518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// 3518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// The LLVM Compiler Infrastructure 4518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// 5518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// This file is distributed under the University of Illinois Open Source 6518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// License. See LICENSE.TXT for details. 7518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// 8518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner//===----------------------------------------------------------------------===// 9518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// 10518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// This file defines the target independent instruction opcodes. 11518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner// 12518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner//===----------------------------------------------------------------------===// 13518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner 14518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner#ifndef LLVM_TARGET_TARGETOPCODES_H 15518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner#define LLVM_TARGET_TARGETOPCODES_H 16518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner 17518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattnernamespace llvm { 1865766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 192516d0d7b1062f512bd57d142c966b3ae18ada7cDan Gohman/// Invariant opcodes: All instruction sets have these as their low opcodes. 2065766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen/// 2165766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen/// Every instruction defined here must also appear in Target.td and the order 2265766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen/// must be the same as in CodeGenTarget.cpp. 2365766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen/// 24518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattnernamespace TargetOpcode { 2565766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen enum { 26518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner PHI = 0, 27518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner INLINEASM = 1, 287431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling PROLOG_LABEL = 2, 29518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner EH_LABEL = 3, 30518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner GC_LABEL = 4, 3165766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 32518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// KILL - This instruction is a noop that is used only to adjust the 33518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// liveness of registers. This can be useful when dealing with 34518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// sub-registers. 35518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner KILL = 5, 3665766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 37518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// EXTRACT_SUBREG - This instruction takes two operands: a register 38518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// that has subregisters, and a subregister index. It returns the 39518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// extracted subregister value. This is commonly used to implement 40518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// truncation operations on target architectures which support it. 41518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner EXTRACT_SUBREG = 6, 4265766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 43d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// INSERT_SUBREG - This instruction takes three operands: a register that 44d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// has subregisters, a register providing an insert value, and a 45d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// subregister index. It returns the value of the first register with the 46d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// value of the second register inserted. The first register is often 47d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// defined by an IMPLICIT_DEF, because it is commonly used to implement 48518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// anyext operations on target architectures which support it. 49518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner INSERT_SUBREG = 7, 5065766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 51518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 52518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner IMPLICIT_DEF = 8, 5365766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 54d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that 55d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// the first operand is an immediate integer constant. This constant is 56d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// often zero, because it is commonly used to assert that the instruction 57d8ab9b415de10320315644a72ce6c5d3b8f6bc9bBill Wendling /// defining the register implicitly clears the high bits. 58518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner SUBREG_TO_REG = 9, 5965766ce7df779ac0e7f6ee0171562b56769ae1ddJakob Stoklund Olesen 60518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 61518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// register-to-register copy into a specific register class. This is only 62518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// used between instruction selection and MachineInstr creation, before 63518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// virtual registers have been created for all the instructions, and it's 64518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner /// only needed in cases where the register classes implied by the 65744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen /// instructions are insufficient. It is emitted as a COPY MachineInstr. 66518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner COPY_TO_REGCLASS = 10, 67b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng 682516d0d7b1062f512bd57d142c966b3ae18ada7cDan Gohman /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 69b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng DBG_VALUE = 11, 70b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng 71b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// REG_SEQUENCE - This variadic instruction is used to form a register that 72b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// represent a consecutive sequence of sub-registers. It's used as register 73b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// coalescing / allocation aid and must be eliminated before code emission. 741300f3019e5d590231bbc3d907626708515d3212Owen Anderson // In SDNode form, the first operand encodes the register class created by 751300f3019e5d590231bbc3d907626708515d3212Owen Anderson // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 761300f3019e5d590231bbc3d907626708515d3212Owen Anderson // pair. Once it has been lowered to a MachineInstr, the regclass operand 771300f3019e5d590231bbc3d907626708515d3212Owen Anderson // is no longer present. 78b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 79b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// After register coalescing references of v1024 should be replace with 80b55c8bed9d0f3eaa454a657746d8ec11aae9dea3Evan Cheng /// v1027:3, v1025 with v1027:4, etc. 81a4e1ba53ddedd08669886b2849926bb33facc198Jakob Stoklund Olesen REG_SEQUENCE = 12, 82a4e1ba53ddedd08669886b2849926bb33facc198Jakob Stoklund Olesen 83a4e1ba53ddedd08669886b2849926bb33facc198Jakob Stoklund Olesen /// COPY - Target-independent register copy. This instruction can also be 84a4e1ba53ddedd08669886b2849926bb33facc198Jakob Stoklund Olesen /// used to copy between subregisters of virtual registers. 857c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng COPY = 13, 867c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 877c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// BUNDLE - This instruction represents an instruction bundle. Instructions 887c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// which immediately follow a BUNDLE instruction which are marked with 897c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// 'InsideBundle' flag are inside the bundle. 90c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem BUNDLE = 14, 91c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem 92c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem /// Lifetime markers. 93c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem LIFETIME_START = 15, 94c05d30601ced172b55be81bb529df6be91d6ae15Nadav Rotem LIFETIME_END = 16 95518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner }; 96518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner} // end namespace TargetOpcode 97518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner} // end namespace llvm 98518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner 99518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner#endif 100