1//===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64.h"
15#include "AArch64FrameLowering.h"
16#include "AArch64MachineFunctionInfo.h"
17#include "AArch64InstrInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/RegisterScavenging.h"
25#include "llvm/IR/Function.h"
26#include "llvm/MC/MachineLocation.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29
30using namespace llvm;
31
32void AArch64FrameLowering::splitSPAdjustments(uint64_t Total,
33                                              uint64_t &Initial,
34                                              uint64_t &Residual) const {
35  // 0x1f0 here is a pessimistic (i.e. realistic) boundary: x-register LDP
36  // instructions have a 7-bit signed immediate scaled by 8, giving a reach of
37  // 0x1f8, but stack adjustment should always be a multiple of 16.
38  if (Total <= 0x1f0) {
39    Initial = Total;
40    Residual = 0;
41  } else {
42    Initial = 0x1f0;
43    Residual = Total - Initial;
44  }
45}
46
47void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
48  AArch64MachineFunctionInfo *FuncInfo =
49    MF.getInfo<AArch64MachineFunctionInfo>();
50  MachineBasicBlock &MBB = MF.front();
51  MachineBasicBlock::iterator MBBI = MBB.begin();
52  MachineFrameInfo *MFI = MF.getFrameInfo();
53  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
54  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
55
56  MachineModuleInfo &MMI = MF.getMMI();
57  std::vector<MachineMove> &Moves = MMI.getFrameMoves();
58  bool NeedsFrameMoves = MMI.hasDebugInfo()
59    || MF.getFunction()->needsUnwindTableEntry();
60
61  uint64_t NumInitialBytes, NumResidualBytes;
62
63  // Currently we expect the stack to be laid out by
64  //     sub sp, sp, #initial
65  //     stp x29, x30, [sp, #offset]
66  //     ...
67  //     str xxx, [sp, #offset]
68  //     sub sp, sp, #rest (possibly via extra instructions).
69  if (MFI->getCalleeSavedInfo().size()) {
70    // If there are callee-saved registers, we want to store them efficiently as
71    // a block, and virtual base assignment happens too early to do it for us so
72    // we adjust the stack in two phases: first just for callee-saved fiddling,
73    // then to allocate the rest of the frame.
74    splitSPAdjustments(MFI->getStackSize(), NumInitialBytes, NumResidualBytes);
75  } else {
76    // If there aren't any callee-saved registers, two-phase adjustment is
77    // inefficient. It's more efficient to adjust with NumInitialBytes too
78    // because when we're in a "callee pops argument space" situation, that pop
79    // must be tacked onto Initial for correctness.
80    NumInitialBytes = MFI->getStackSize();
81    NumResidualBytes = 0;
82  }
83
84  // Tell everyone else how much adjustment we're expecting them to use. In
85  // particular if an adjustment is required for a tail call the epilogue could
86  // have a different view of things.
87  FuncInfo->setInitialStackAdjust(NumInitialBytes);
88
89  emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
90               MachineInstr::FrameSetup);
91
92  if (NeedsFrameMoves && NumInitialBytes) {
93    // We emit this update even if the CFA is set from a frame pointer later so
94    // that the CFA is valid in the interim.
95    MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
96    BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
97      .addSym(SPLabel);
98
99    MachineLocation Dst(MachineLocation::VirtualFP);
100    MachineLocation Src(AArch64::XSP, NumInitialBytes);
101    Moves.push_back(MachineMove(SPLabel, Dst, Src));
102  }
103
104  // Otherwise we need to set the frame pointer and/or add a second stack
105  // adjustment.
106
107  bool FPNeedsSetting = hasFP(MF);
108  for (; MBBI != MBB.end(); ++MBBI) {
109    // Note that this search makes strong assumptions about the operation used
110    // to store the frame-pointer: it must be "STP x29, x30, ...". This could
111    // change in future, but until then there's no point in implementing
112    // untestable more generic cases.
113    if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
114                       && MBBI->getOperand(0).getReg() == AArch64::X29) {
115      int64_t X29FrameIdx = MBBI->getOperand(2).getIndex();
116      FuncInfo->setFramePointerOffset(MFI->getObjectOffset(X29FrameIdx));
117
118      ++MBBI;
119      emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
120                    AArch64::X29,
121                    NumInitialBytes + MFI->getObjectOffset(X29FrameIdx),
122                    MachineInstr::FrameSetup);
123
124      // The offset adjustment used when emitting debugging locations relative
125      // to whatever frame base is set. AArch64 uses the default frame base (FP
126      // or SP) and this adjusts the calculations to be correct.
127      MFI->setOffsetAdjustment(- MFI->getObjectOffset(X29FrameIdx)
128                               - MFI->getStackSize());
129
130      if (NeedsFrameMoves) {
131        MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
132        BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
133          .addSym(FPLabel);
134        MachineLocation Dst(MachineLocation::VirtualFP);
135        MachineLocation Src(AArch64::X29, -MFI->getObjectOffset(X29FrameIdx));
136        Moves.push_back(MachineMove(FPLabel, Dst, Src));
137      }
138
139      FPNeedsSetting = false;
140    }
141
142    if (!MBBI->getFlag(MachineInstr::FrameSetup))
143      break;
144  }
145
146  assert(!FPNeedsSetting && "Frame pointer couldn't be set");
147
148  emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
149               MachineInstr::FrameSetup);
150
151  // Now we emit the rest of the frame setup information, if necessary: we've
152  // already noted the FP and initial SP moves so we're left with the prologue's
153  // final SP update and callee-saved register locations.
154  if (!NeedsFrameMoves)
155    return;
156
157  // Reuse the label if appropriate, so create it in this outer scope.
158  MCSymbol *CSLabel = 0;
159
160  // The rest of the stack adjustment
161  if (!hasFP(MF) && NumResidualBytes) {
162    CSLabel = MMI.getContext().CreateTempSymbol();
163    BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
164      .addSym(CSLabel);
165
166    MachineLocation Dst(MachineLocation::VirtualFP);
167    MachineLocation Src(AArch64::XSP, NumResidualBytes + NumInitialBytes);
168    Moves.push_back(MachineMove(CSLabel, Dst, Src));
169  }
170
171  // And any callee-saved registers (it's fine to leave them to the end here,
172  // because the old values are still valid at this point.
173  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
174  if (CSI.size()) {
175    if (!CSLabel) {
176      CSLabel = MMI.getContext().CreateTempSymbol();
177      BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
178        .addSym(CSLabel);
179    }
180
181    for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
182           E = CSI.end(); I != E; ++I) {
183      MachineLocation Dst(MachineLocation::VirtualFP,
184                          MFI->getObjectOffset(I->getFrameIdx()));
185      MachineLocation Src(I->getReg());
186      Moves.push_back(MachineMove(CSLabel, Dst, Src));
187    }
188  }
189}
190
191void
192AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
193                                   MachineBasicBlock &MBB) const {
194  AArch64MachineFunctionInfo *FuncInfo =
195    MF.getInfo<AArch64MachineFunctionInfo>();
196
197  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
198  DebugLoc DL = MBBI->getDebugLoc();
199  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
200  MachineFrameInfo &MFI = *MF.getFrameInfo();
201  unsigned RetOpcode = MBBI->getOpcode();
202
203  // Initial and residual are named for consitency with the prologue. Note that
204  // in the epilogue, the residual adjustment is executed first.
205  uint64_t NumInitialBytes = FuncInfo->getInitialStackAdjust();
206  uint64_t NumResidualBytes = MFI.getStackSize() - NumInitialBytes;
207  uint64_t ArgumentPopSize = 0;
208  if (RetOpcode == AArch64::TC_RETURNdi ||
209      RetOpcode == AArch64::TC_RETURNxi) {
210    MachineOperand &JumpTarget = MBBI->getOperand(0);
211    MachineOperand &StackAdjust = MBBI->getOperand(1);
212
213    MachineInstrBuilder MIB;
214    if (RetOpcode == AArch64::TC_RETURNdi) {
215      MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
216      if (JumpTarget.isGlobal()) {
217        MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
218                             JumpTarget.getTargetFlags());
219      } else {
220        assert(JumpTarget.isSymbol() && "unexpected tail call destination");
221        MIB.addExternalSymbol(JumpTarget.getSymbolName(),
222                              JumpTarget.getTargetFlags());
223      }
224    } else {
225      assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
226             && "Unexpected tail call");
227
228      MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
229      MIB.addReg(JumpTarget.getReg(), RegState::Kill);
230    }
231
232    // Add the extra operands onto the new tail call instruction even though
233    // they're not used directly (so that liveness is tracked properly etc).
234    for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
235        MIB->addOperand(MBBI->getOperand(i));
236
237
238    // Delete the pseudo instruction TC_RETURN.
239    MachineInstr *NewMI = prior(MBBI);
240    MBB.erase(MBBI);
241    MBBI = NewMI;
242
243    // For a tail-call in a callee-pops-arguments environment, some or all of
244    // the stack may actually be in use for the call's arguments, this is
245    // calculated during LowerCall and consumed here...
246    ArgumentPopSize = StackAdjust.getImm();
247  } else {
248    // ... otherwise the amount to pop is *all* of the argument space,
249    // conveniently stored in the MachineFunctionInfo by
250    // LowerFormalArguments. This will, of course, be zero for the C calling
251    // convention.
252    ArgumentPopSize = FuncInfo->getArgumentStackToRestore();
253  }
254
255  assert(NumInitialBytes % 16 == 0 && NumResidualBytes % 16 == 0
256         && "refusing to adjust stack by misaligned amt");
257
258  // We may need to address callee-saved registers differently, so find out the
259  // bound on the frame indices.
260  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
261  int MinCSFI = 0;
262  int MaxCSFI = -1;
263
264  if (CSI.size()) {
265    MinCSFI = CSI[0].getFrameIdx();
266    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
267  }
268
269  // The "residual" stack update comes first from this direction and guarantees
270  // that SP is NumInitialBytes below its value on function entry, either by a
271  // direct update or restoring it from the frame pointer.
272  if (NumInitialBytes + ArgumentPopSize != 0) {
273    emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
274                 NumInitialBytes + ArgumentPopSize);
275    --MBBI;
276  }
277
278
279  // MBBI now points to the instruction just past the last callee-saved
280  // restoration (either RET/B if NumInitialBytes == 0, or the "ADD sp, sp"
281  // otherwise).
282
283  // Now we need to find out where to put the bulk of the stack adjustment
284  MachineBasicBlock::iterator FirstEpilogue = MBBI;
285  while (MBBI != MBB.begin()) {
286    --MBBI;
287
288    unsigned FrameOp;
289    for (FrameOp = 0; FrameOp < MBBI->getNumOperands(); ++FrameOp) {
290      if (MBBI->getOperand(FrameOp).isFI())
291        break;
292    }
293
294    // If this instruction doesn't have a frame index we've reached the end of
295    // the callee-save restoration.
296    if (FrameOp == MBBI->getNumOperands())
297      break;
298
299    // Likewise if it *is* a local reference, but not to a callee-saved object.
300    int FrameIdx = MBBI->getOperand(FrameOp).getIndex();
301    if (FrameIdx < MinCSFI || FrameIdx > MaxCSFI)
302      break;
303
304    FirstEpilogue = MBBI;
305  }
306
307  if (MF.getFrameInfo()->hasVarSizedObjects()) {
308    int64_t StaticFrameBase;
309    StaticFrameBase = -(NumInitialBytes + FuncInfo->getFramePointerOffset());
310    emitRegUpdate(MBB, FirstEpilogue, DL, TII,
311                  AArch64::XSP, AArch64::X29, AArch64::NoRegister,
312                  StaticFrameBase);
313  } else {
314    emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
315  }
316}
317
318int64_t
319AArch64FrameLowering::resolveFrameIndexReference(MachineFunction &MF,
320                                                 int FrameIndex,
321                                                 unsigned &FrameReg,
322                                                 int SPAdj,
323                                                 bool IsCalleeSaveOp) const {
324  AArch64MachineFunctionInfo *FuncInfo =
325    MF.getInfo<AArch64MachineFunctionInfo>();
326  MachineFrameInfo *MFI = MF.getFrameInfo();
327
328  int64_t TopOfFrameOffset = MFI->getObjectOffset(FrameIndex);
329
330  assert(!(IsCalleeSaveOp && FuncInfo->getInitialStackAdjust() == 0)
331         && "callee-saved register in unexpected place");
332
333  // If the frame for this function is particularly large, we adjust the stack
334  // in two phases which means the callee-save related operations see a
335  // different (intermediate) stack size.
336  int64_t FrameRegPos;
337  if (IsCalleeSaveOp) {
338    FrameReg = AArch64::XSP;
339    FrameRegPos = -static_cast<int64_t>(FuncInfo->getInitialStackAdjust());
340  } else if (useFPForAddressing(MF)) {
341    // Have to use the frame pointer since we have no idea where SP is.
342    FrameReg = AArch64::X29;
343    FrameRegPos = FuncInfo->getFramePointerOffset();
344  } else {
345    FrameReg = AArch64::XSP;
346    FrameRegPos = -static_cast<int64_t>(MFI->getStackSize()) + SPAdj;
347  }
348
349  return TopOfFrameOffset - FrameRegPos;
350}
351
352void
353AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
354                                                       RegScavenger *RS) const {
355  const AArch64RegisterInfo *RegInfo =
356    static_cast<const AArch64RegisterInfo *>(MF.getTarget().getRegisterInfo());
357  MachineFrameInfo *MFI = MF.getFrameInfo();
358  const AArch64InstrInfo &TII =
359    *static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
360
361  if (hasFP(MF)) {
362    MF.getRegInfo().setPhysRegUsed(AArch64::X29);
363    MF.getRegInfo().setPhysRegUsed(AArch64::X30);
364  }
365
366  // If addressing of local variables is going to be more complicated than
367  // shoving a base register and an offset into the instruction then we may well
368  // need to scavenge registers. We should either specifically add an
369  // callee-save register for this purpose or allocate an extra spill slot.
370
371  bool BigStack =
372    (RS && MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF))
373    || MFI->hasVarSizedObjects() // Access will be from X29: messes things up
374    || (MFI->adjustsStack() && !hasReservedCallFrame(MF));
375
376  if (!BigStack)
377    return;
378
379  // We certainly need some slack space for the scavenger, preferably an extra
380  // register.
381  const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
382  uint16_t ExtraReg = AArch64::NoRegister;
383
384  for (unsigned i = 0; CSRegs[i]; ++i) {
385    if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
386        !MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
387      ExtraReg = CSRegs[i];
388      break;
389    }
390  }
391
392  if (ExtraReg != 0) {
393    MF.getRegInfo().setPhysRegUsed(ExtraReg);
394  } else {
395    // Create a stack slot for scavenging purposes. PrologEpilogInserter
396    // helpfully places it near either SP or FP for us to avoid
397    // infinitely-regression during scavenging.
398    const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
399    RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
400                                                       RC->getAlignment(),
401                                                       false));
402  }
403}
404
405bool AArch64FrameLowering::determinePrologueDeath(MachineBasicBlock &MBB,
406                                                  unsigned Reg) const {
407  // If @llvm.returnaddress is called then it will refer to X30 by some means;
408  // the prologue store does not kill the register.
409  if (Reg == AArch64::X30) {
410    if (MBB.getParent()->getFrameInfo()->isReturnAddressTaken()
411        && MBB.getParent()->getRegInfo().isLiveIn(Reg))
412    return false;
413  }
414
415  // In all other cases, physical registers are dead after they've been saved
416  // but live at the beginning of the prologue block.
417  MBB.addLiveIn(Reg);
418  return true;
419}
420
421void
422AArch64FrameLowering::emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB,
423                                      MachineBasicBlock::iterator MBBI,
424                                      const std::vector<CalleeSavedInfo> &CSI,
425                                      const TargetRegisterInfo *TRI,
426                                      LoadStoreMethod PossClasses[],
427                                      unsigned NumClasses) const {
428  DebugLoc DL = MBB.findDebugLoc(MBBI);
429  MachineFunction &MF = *MBB.getParent();
430  MachineFrameInfo &MFI = *MF.getFrameInfo();
431  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
432
433  // A certain amount of implicit contract is present here. The actual stack
434  // offsets haven't been allocated officially yet, so for strictly correct code
435  // we rely on the fact that the elements of CSI are allocated in order
436  // starting at SP, purely as dictated by size and alignment. In practice since
437  // this function handles the only accesses to those slots it's not quite so
438  // important.
439  //
440  // We have also ordered the Callee-saved register list in AArch64CallingConv
441  // so that the above scheme puts registers in order: in particular we want
442  // &X30 to be &X29+8 for an ABI-correct frame record (PCS 5.2.2)
443  for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
444    unsigned Reg = CSI[i].getReg();
445
446    // First we need to find out which register class the register belongs to so
447    // that we can use the correct load/store instrucitons.
448    unsigned ClassIdx;
449    for (ClassIdx = 0; ClassIdx < NumClasses; ++ClassIdx) {
450      if (PossClasses[ClassIdx].RegClass->contains(Reg))
451        break;
452    }
453    assert(ClassIdx != NumClasses
454           && "Asked to store register in unexpected class");
455    const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
456
457    // Now we need to decide whether it's possible to emit a paired instruction:
458    // for this we want the next register to be in the same class.
459    MachineInstrBuilder NewMI;
460    bool Pair = false;
461    if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) {
462      Pair = true;
463      unsigned StLow = 0, StHigh = 0;
464      if (isPrologue) {
465        // Most of these registers will be live-in to the MBB and killed by our
466        // store, though there are exceptions (see determinePrologueDeath).
467        StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
468        StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
469      } else {
470        StLow = RegState::Define;
471        StHigh = RegState::Define;
472      }
473
474      NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].PairOpcode))
475                .addReg(CSI[i+1].getReg(), StLow)
476                .addReg(CSI[i].getReg(), StHigh);
477
478      // If it's a paired op, we've consumed two registers
479      ++i;
480    } else {
481      unsigned State;
482      if (isPrologue) {
483        State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
484      } else {
485        State = RegState::Define;
486      }
487
488      NewMI = BuildMI(MBB, MBBI, DL,
489                      TII.get(PossClasses[ClassIdx].SingleOpcode))
490                .addReg(CSI[i].getReg(), State);
491    }
492
493    // Note that the FrameIdx refers to the second register in a pair: it will
494    // be allocated the smaller numeric address and so is the one an LDP/STP
495    // address must use.
496    int FrameIdx = CSI[i].getFrameIdx();
497    MachineMemOperand::MemOperandFlags Flags;
498    Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
499    MachineMemOperand *MMO =
500      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
501                             Flags,
502                             Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
503                             MFI.getObjectAlignment(FrameIdx));
504
505    NewMI.addFrameIndex(FrameIdx)
506      .addImm(0)                  // address-register offset
507      .addMemOperand(MMO);
508
509    if (isPrologue)
510      NewMI.setMIFlags(MachineInstr::FrameSetup);
511
512    // For aesthetic reasons, during an epilogue we want to emit complementary
513    // operations to the prologue, but in the opposite order. So we still
514    // iterate through the CalleeSavedInfo list in order, but we put the
515    // instructions successively earlier in the MBB.
516    if (!isPrologue)
517      --MBBI;
518  }
519}
520
521bool
522AArch64FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
523                                        MachineBasicBlock::iterator MBBI,
524                                        const std::vector<CalleeSavedInfo> &CSI,
525                                        const TargetRegisterInfo *TRI) const {
526  if (CSI.empty())
527    return false;
528
529  static LoadStoreMethod PossibleClasses[] = {
530    {&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
531    {&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
532  };
533  unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
534
535  emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI,
536                  PossibleClasses, NumClasses);
537
538  return true;
539}
540
541bool
542AArch64FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
543                                        MachineBasicBlock::iterator MBBI,
544                                        const std::vector<CalleeSavedInfo> &CSI,
545                                        const TargetRegisterInfo *TRI) const {
546
547  if (CSI.empty())
548    return false;
549
550  static LoadStoreMethod PossibleClasses[] = {
551    {&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
552    {&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
553  };
554  unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
555
556  emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI,
557                  PossibleClasses, NumClasses);
558
559  return true;
560}
561
562bool
563AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
564  const MachineFrameInfo *MFI = MF.getFrameInfo();
565  const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
566
567  // This is a decision of ABI compliance. The AArch64 PCS gives various options
568  // for conformance, and even at the most stringent level more or less permits
569  // elimination for leaf functions because there's no loss of functionality
570  // (for debugging etc)..
571  if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->hasCalls())
572    return true;
573
574  // The following are hard-limits: incorrect code will be generated if we try
575  // to omit the frame.
576  return (RI->needsStackRealignment(MF) ||
577          MFI->hasVarSizedObjects() ||
578          MFI->isFrameAddressTaken());
579}
580
581bool
582AArch64FrameLowering::useFPForAddressing(const MachineFunction &MF) const {
583  return MF.getFrameInfo()->hasVarSizedObjects();
584}
585
586bool
587AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
588  const MachineFrameInfo *MFI = MF.getFrameInfo();
589
590  // Of the various reasons for having a frame pointer, it's actually only
591  // variable-sized objects that prevent reservation of a call frame.
592  return !(hasFP(MF) && MFI->hasVarSizedObjects());
593}
594
595void
596AArch64FrameLowering::eliminateCallFramePseudoInstr(
597                                MachineFunction &MF,
598                                MachineBasicBlock &MBB,
599                                MachineBasicBlock::iterator MI) const {
600  const AArch64InstrInfo &TII =
601    *static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
602  DebugLoc dl = MI->getDebugLoc();
603  int Opcode = MI->getOpcode();
604  bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
605  uint64_t CalleePopAmount = IsDestroy ? MI->getOperand(1).getImm() : 0;
606
607  if (!hasReservedCallFrame(MF)) {
608    unsigned Align = getStackAlignment();
609
610    int64_t Amount = MI->getOperand(0).getImm();
611    Amount = RoundUpToAlignment(Amount, Align);
612    if (!IsDestroy) Amount = -Amount;
613
614    // N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
615    // doesn't have to pop anything), then the first operand will be zero too so
616    // this adjustment is a no-op.
617    if (CalleePopAmount == 0) {
618      // FIXME: in-function stack adjustment for calls is limited to 12-bits
619      // because there's no guaranteed temporary register available. Mostly call
620      // frames will be allocated at the start of a function so this is OK, but
621      // it is a limitation that needs dealing with.
622      assert(Amount > -0xfff && Amount < 0xfff && "call frame too large");
623      emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
624    }
625  } else if (CalleePopAmount != 0) {
626    // If the calling convention demands that the callee pops arguments from the
627    // stack, we want to add it back if we have a reserved call frame.
628    assert(CalleePopAmount < 0xfff && "call frame too large");
629    emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
630  }
631
632  MBB.erase(MI);
633}
634