1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/Target/TargetInstrInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "ARMGenInstrInfo.inc"
25
26namespace llvm {
27  class ARMSubtarget;
28  class ARMBaseRegisterInfo;
29
30class ARMBaseInstrInfo : public ARMGenInstrInfo {
31  const ARMSubtarget &Subtarget;
32
33protected:
34  // Can be only subclassed.
35  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37public:
38  // Return whether the target has an explicit NOP encoding.
39  bool hasNOP() const;
40
41  // Return the non-pre/post incrementing version of 'Opc'. Return 0
42  // if there is not such an opcode.
43  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
44
45  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46                                              MachineBasicBlock::iterator &MBBI,
47                                              LiveVariables *LV) const;
48
49  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
50  const ARMSubtarget &getSubtarget() const { return Subtarget; }
51
52  ScheduleHazardRecognizer *
53  CreateTargetHazardRecognizer(const TargetMachine *TM,
54                               const ScheduleDAG *DAG) const;
55
56  ScheduleHazardRecognizer *
57  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58                                     const ScheduleDAG *DAG) const;
59
60  // Branch analysis.
61  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62                             MachineBasicBlock *&FBB,
63                             SmallVectorImpl<MachineOperand> &Cond,
64                             bool AllowModify = false) const;
65  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67                                MachineBasicBlock *FBB,
68                                const SmallVectorImpl<MachineOperand> &Cond,
69                                DebugLoc DL) const;
70
71  virtual
72  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
73
74  // Predication support.
75  bool isPredicated(const MachineInstr *MI) const;
76
77  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78    int PIdx = MI->findFirstPredOperandIdx();
79    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80                      : ARMCC::AL;
81  }
82
83  virtual
84  bool PredicateInstruction(MachineInstr *MI,
85                            const SmallVectorImpl<MachineOperand> &Pred) const;
86
87  virtual
88  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89                         const SmallVectorImpl<MachineOperand> &Pred2) const;
90
91  virtual bool DefinesPredicate(MachineInstr *MI,
92                                std::vector<MachineOperand> &Pred) const;
93
94  virtual bool isPredicable(MachineInstr *MI) const;
95
96  /// GetInstSize - Returns the size of the specified MachineInstr.
97  ///
98  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
99
100  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101                                       int &FrameIndex) const;
102  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103                                      int &FrameIndex) const;
104  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105                                             int &FrameIndex) const;
106  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107                                            int &FrameIndex) const;
108
109  virtual void copyPhysReg(MachineBasicBlock &MBB,
110                           MachineBasicBlock::iterator I, DebugLoc DL,
111                           unsigned DestReg, unsigned SrcReg,
112                           bool KillSrc) const;
113
114  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115                                   MachineBasicBlock::iterator MBBI,
116                                   unsigned SrcReg, bool isKill, int FrameIndex,
117                                   const TargetRegisterClass *RC,
118                                   const TargetRegisterInfo *TRI) const;
119
120  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121                                    MachineBasicBlock::iterator MBBI,
122                                    unsigned DestReg, int FrameIndex,
123                                    const TargetRegisterClass *RC,
124                                    const TargetRegisterInfo *TRI) const;
125
126  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
127
128  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
129                                                 int FrameIx,
130                                                 uint64_t Offset,
131                                                 const MDNode *MDPtr,
132                                                 DebugLoc DL) const;
133
134  virtual void reMaterialize(MachineBasicBlock &MBB,
135                             MachineBasicBlock::iterator MI,
136                             unsigned DestReg, unsigned SubIdx,
137                             const MachineInstr *Orig,
138                             const TargetRegisterInfo &TRI) const;
139
140  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
141
142  MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
143
144  virtual bool produceSameValue(const MachineInstr *MI0,
145                                const MachineInstr *MI1,
146                                const MachineRegisterInfo *MRI) const;
147
148  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
149  /// determine if two loads are loading from the same base address. It should
150  /// only return true if the base pointers are the same and the only
151  /// differences between the two addresses is the offset. It also returns the
152  /// offsets by reference.
153  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
154                                       int64_t &Offset1, int64_t &Offset2)const;
155
156  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
157  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
158  /// should be scheduled togther. On some targets if two loads are loading from
159  /// addresses in the same cache line, it's better if they are scheduled
160  /// together. This function takes two integers that represent the load offsets
161  /// from the common base address. It returns true if it decides it's desirable
162  /// to schedule the two loads together. "NumLoads" is the number of loads that
163  /// have already been scheduled after Load1.
164  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
165                                       int64_t Offset1, int64_t Offset2,
166                                       unsigned NumLoads) const;
167
168  virtual bool isSchedulingBoundary(const MachineInstr *MI,
169                                    const MachineBasicBlock *MBB,
170                                    const MachineFunction &MF) const;
171
172  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
173                                   unsigned NumCycles, unsigned ExtraPredCycles,
174                                   const BranchProbability &Probability) const;
175
176  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
177                                   unsigned NumT, unsigned ExtraT,
178                                   MachineBasicBlock &FMBB,
179                                   unsigned NumF, unsigned ExtraF,
180                                   const BranchProbability &Probability) const;
181
182  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
183                                         unsigned NumCycles,
184                                         const BranchProbability
185                                         &Probability) const {
186    return NumCycles == 1;
187  }
188
189  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
190                                         MachineBasicBlock &FMBB) const;
191
192  /// analyzeCompare - For a comparison instruction, return the source registers
193  /// in SrcReg and SrcReg2 if having two register operands, and the value it
194  /// compares against in CmpValue. Return true if the comparison instruction
195  /// can be analyzed.
196  virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
197                              unsigned &SrcReg2, int &CmpMask,
198                              int &CmpValue) const;
199
200  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
201  /// that we can remove a "comparison with zero"; Remove a redundant CMP
202  /// instruction if the flags can be updated in the same way by an earlier
203  /// instruction such as SUB.
204  virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
205                                    unsigned SrcReg2, int CmpMask, int CmpValue,
206                                    const MachineRegisterInfo *MRI) const;
207
208  virtual bool analyzeSelect(const MachineInstr *MI,
209                             SmallVectorImpl<MachineOperand> &Cond,
210                             unsigned &TrueOp, unsigned &FalseOp,
211                             bool &Optimizable) const;
212
213  virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
214
215  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
216  /// instruction, try to fold the immediate into the use instruction.
217  virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
218                             unsigned Reg, MachineRegisterInfo *MRI) const;
219
220  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
221                                  const MachineInstr *MI) const;
222
223  virtual
224  int getOperandLatency(const InstrItineraryData *ItinData,
225                        const MachineInstr *DefMI, unsigned DefIdx,
226                        const MachineInstr *UseMI, unsigned UseIdx) const;
227  virtual
228  int getOperandLatency(const InstrItineraryData *ItinData,
229                        SDNode *DefNode, unsigned DefIdx,
230                        SDNode *UseNode, unsigned UseIdx) const;
231
232  /// VFP/NEON execution domains.
233  std::pair<uint16_t, uint16_t>
234  getExecutionDomain(const MachineInstr *MI) const;
235  void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
236
237  unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
238                                        const TargetRegisterInfo*) const;
239  void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
240                                 const TargetRegisterInfo *TRI) const;
241  /// Get the number of addresses by LDM or VLDM or zero for unknown.
242  unsigned getNumLDMAddresses(const MachineInstr *MI) const;
243
244private:
245  unsigned getInstBundleLength(const MachineInstr *MI) const;
246
247  int getVLDMDefCycle(const InstrItineraryData *ItinData,
248                      const MCInstrDesc &DefMCID,
249                      unsigned DefClass,
250                      unsigned DefIdx, unsigned DefAlign) const;
251  int getLDMDefCycle(const InstrItineraryData *ItinData,
252                     const MCInstrDesc &DefMCID,
253                     unsigned DefClass,
254                     unsigned DefIdx, unsigned DefAlign) const;
255  int getVSTMUseCycle(const InstrItineraryData *ItinData,
256                      const MCInstrDesc &UseMCID,
257                      unsigned UseClass,
258                      unsigned UseIdx, unsigned UseAlign) const;
259  int getSTMUseCycle(const InstrItineraryData *ItinData,
260                     const MCInstrDesc &UseMCID,
261                     unsigned UseClass,
262                     unsigned UseIdx, unsigned UseAlign) const;
263  int getOperandLatency(const InstrItineraryData *ItinData,
264                        const MCInstrDesc &DefMCID,
265                        unsigned DefIdx, unsigned DefAlign,
266                        const MCInstrDesc &UseMCID,
267                        unsigned UseIdx, unsigned UseAlign) const;
268
269  unsigned getInstrLatency(const InstrItineraryData *ItinData,
270                           const MachineInstr *MI,
271                           unsigned *PredCost = 0) const;
272
273  int getInstrLatency(const InstrItineraryData *ItinData,
274                      SDNode *Node) const;
275
276  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
277                             const MachineRegisterInfo *MRI,
278                             const MachineInstr *DefMI, unsigned DefIdx,
279                             const MachineInstr *UseMI, unsigned UseIdx) const;
280  bool hasLowDefLatency(const InstrItineraryData *ItinData,
281                        const MachineInstr *DefMI, unsigned DefIdx) const;
282
283  /// verifyInstruction - Perform target specific instruction verification.
284  bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
285
286private:
287  /// Modeling special VFP / NEON fp MLA / MLS hazards.
288
289  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
290  /// MLx table.
291  DenseMap<unsigned, unsigned> MLxEntryMap;
292
293  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
294  /// stalls when scheduled together with fp MLA / MLS opcodes.
295  SmallSet<unsigned, 16> MLxHazardOpcodes;
296
297public:
298  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
299  /// instruction.
300  bool isFpMLxInstruction(unsigned Opcode) const {
301    return MLxEntryMap.count(Opcode);
302  }
303
304  /// isFpMLxInstruction - This version also returns the multiply opcode and the
305  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
306  /// the MLX instructions with an extra lane operand.
307  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
308                          unsigned &AddSubOpc, bool &NegAcc,
309                          bool &HasLane) const;
310
311  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
312  /// will cause stalls when scheduled after (within 4-cycle window) a fp
313  /// MLA / MLS instruction.
314  bool canCauseFpMLxStall(unsigned Opcode) const {
315    return MLxHazardOpcodes.count(Opcode);
316  }
317};
318
319static inline
320const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
321  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
322}
323
324static inline
325const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
326  return MIB.addReg(0);
327}
328
329static inline
330const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
331                                          bool isDead = false) {
332  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
333}
334
335static inline
336const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
337  return MIB.addReg(0);
338}
339
340static inline
341bool isUncondBranchOpcode(int Opc) {
342  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
343}
344
345static inline
346bool isCondBranchOpcode(int Opc) {
347  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
348}
349
350static inline
351bool isJumpTableBranchOpcode(int Opc) {
352  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
353    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
354}
355
356static inline
357bool isIndirectBranchOpcode(int Opc) {
358  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
359}
360
361/// getInstrPredicate - If instruction is predicated, returns its predicate
362/// condition, otherwise returns AL. It also returns the condition code
363/// register by reference.
364ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
365
366int getMatchingCondBranchOpcode(int Opc);
367
368/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
369/// opcode of the SSA instruction representing the conditional MI.
370unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
371                                  MachineInstr *&MI,
372                                  const MachineRegisterInfo &MRI);
373
374/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
375/// the instruction is encoded with an 'S' bit is determined by the optional
376/// CPSR def operand.
377unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
378
379/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
380/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
381/// code.
382void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
383                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
384                             unsigned DestReg, unsigned BaseReg, int NumBytes,
385                             ARMCC::CondCodes Pred, unsigned PredReg,
386                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
387
388void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
389                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
390                            unsigned DestReg, unsigned BaseReg, int NumBytes,
391                            ARMCC::CondCodes Pred, unsigned PredReg,
392                            const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
393void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
394                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
395                               unsigned DestReg, unsigned BaseReg,
396                               int NumBytes, const TargetInstrInfo &TII,
397                               const ARMBaseRegisterInfo& MRI,
398                               unsigned MIFlags = 0);
399
400
401/// rewriteARMFrameIndex / rewriteT2FrameIndex -
402/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
403/// offset could not be handled directly in MI, and return the left-over
404/// portion by reference.
405bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
406                          unsigned FrameReg, int &Offset,
407                          const ARMBaseInstrInfo &TII);
408
409bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
410                         unsigned FrameReg, int &Offset,
411                         const ARMBaseInstrInfo &TII);
412
413} // End llvm namespace
414
415#endif
416