ARMBaseInstrInfo.h revision 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseRegisterInfo;
24
25/// ARMII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace ARMII {
29  enum {
30    //===------------------------------------------------------------------===//
31    // Instruction Flags.
32
33    //===------------------------------------------------------------------===//
34    // This four-bit field describes the addressing mode used.
35
36    AddrModeMask  = 0xf,
37    AddrModeNone    = 0,
38    AddrMode1       = 1,
39    AddrMode2       = 2,
40    AddrMode3       = 3,
41    AddrMode4       = 4,
42    AddrMode5       = 5,
43    AddrMode6       = 6,
44    AddrModeT1_1    = 7,
45    AddrModeT1_2    = 8,
46    AddrModeT1_4    = 9,
47    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
48    AddrModeT2_i12  = 11,
49    AddrModeT2_i8   = 12,
50    AddrModeT2_so   = 13,
51    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
52    AddrModeT2_i8s4 = 15, // i8 * 4
53
54    // Size* - Flags to keep track of the size of an instruction.
55    SizeShift     = 4,
56    SizeMask      = 7 << SizeShift,
57    SizeSpecial   = 1,   // 0 byte pseudo or special case.
58    Size8Bytes    = 2,
59    Size4Bytes    = 3,
60    Size2Bytes    = 4,
61
62    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
64    IndexModeShift = 7,
65    IndexModeMask  = 3 << IndexModeShift,
66    IndexModePre   = 1,
67    IndexModePost  = 2,
68    IndexModeUpd   = 3,
69
70    //===------------------------------------------------------------------===//
71    // Instruction encoding formats.
72    //
73    FormShift     = 9,
74    FormMask      = 0x3f << FormShift,
75
76    // Pseudo instructions
77    Pseudo        = 0  << FormShift,
78
79    // Multiply instructions
80    MulFrm        = 1  << FormShift,
81
82    // Branch instructions
83    BrFrm         = 2  << FormShift,
84    BrMiscFrm     = 3  << FormShift,
85
86    // Data Processing instructions
87    DPFrm         = 4  << FormShift,
88    DPSoRegFrm    = 5  << FormShift,
89
90    // Load and Store
91    LdFrm         = 6  << FormShift,
92    StFrm         = 7  << FormShift,
93    LdMiscFrm     = 8  << FormShift,
94    StMiscFrm     = 9  << FormShift,
95    LdStMulFrm    = 10 << FormShift,
96
97    LdStExFrm     = 11 << FormShift,
98
99    // Miscellaneous arithmetic instructions
100    ArithMiscFrm  = 12 << FormShift,
101    SatFrm        = 13 << FormShift,
102
103    // Extend instructions
104    ExtFrm        = 14 << FormShift,
105
106    // VFP formats
107    VFPUnaryFrm   = 15 << FormShift,
108    VFPBinaryFrm  = 16 << FormShift,
109    VFPConv1Frm   = 17 << FormShift,
110    VFPConv2Frm   = 18 << FormShift,
111    VFPConv3Frm   = 19 << FormShift,
112    VFPConv4Frm   = 20 << FormShift,
113    VFPConv5Frm   = 21 << FormShift,
114    VFPLdStFrm    = 22 << FormShift,
115    VFPLdStMulFrm = 23 << FormShift,
116    VFPMiscFrm    = 24 << FormShift,
117
118    // Thumb format
119    ThumbFrm      = 25 << FormShift,
120
121    // Miscelleaneous format
122    MiscFrm       = 26 << FormShift,
123
124    // NEON formats
125    NGetLnFrm     = 27 << FormShift,
126    NSetLnFrm     = 28 << FormShift,
127    NDupFrm       = 29 << FormShift,
128    NLdStFrm      = 30 << FormShift,
129    N1RegModImmFrm= 31 << FormShift,
130    N2RegFrm      = 32 << FormShift,
131    NVCVTFrm      = 33 << FormShift,
132    NVDupLnFrm    = 34 << FormShift,
133    N2RegVShLFrm  = 35 << FormShift,
134    N2RegVShRFrm  = 36 << FormShift,
135    N3RegFrm      = 37 << FormShift,
136    N3RegVShFrm   = 38 << FormShift,
137    NVExtFrm      = 39 << FormShift,
138    NVMulSLFrm    = 40 << FormShift,
139    NVTBLFrm      = 41 << FormShift,
140
141    //===------------------------------------------------------------------===//
142    // Misc flags.
143
144    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
145    // it doesn't have a Rn operand.
146    UnaryDP       = 1 << 15,
147
148    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
149    // a 16-bit Thumb instruction if certain conditions are met.
150    Xform16Bit    = 1 << 16,
151
152    //===------------------------------------------------------------------===//
153    // Code domain.
154    DomainShift   = 17,
155    DomainMask    = 3 << DomainShift,
156    DomainGeneral = 0 << DomainShift,
157    DomainVFP     = 1 << DomainShift,
158    DomainNEON    = 2 << DomainShift,
159
160    //===------------------------------------------------------------------===//
161    // Field shifts - such shifts are used to set field while generating
162    // machine instructions.
163    M_BitShift     = 5,
164    ShiftImmShift  = 5,
165    ShiftShift     = 7,
166    N_BitShift     = 7,
167    ImmHiShift     = 8,
168    SoRotImmShift  = 8,
169    RegRsShift     = 8,
170    ExtRotImmShift = 10,
171    RegRdLoShift   = 12,
172    RegRdShift     = 12,
173    RegRdHiShift   = 16,
174    RegRnShift     = 16,
175    S_BitShift     = 20,
176    W_BitShift     = 21,
177    AM3_I_BitShift = 22,
178    D_BitShift     = 22,
179    U_BitShift     = 23,
180    P_BitShift     = 24,
181    I_BitShift     = 25,
182    CondShift      = 28
183  };
184
185  /// Target Operand Flag enum.
186  enum TOF {
187    //===------------------------------------------------------------------===//
188    // ARM Specific MachineOperand flags.
189
190    MO_NO_FLAG,
191
192    /// MO_LO16 - On a symbol operand, this represents a relocation containing
193    /// lower 16 bit of the address. Used only via movw instruction.
194    MO_LO16,
195
196    /// MO_HI16 - On a symbol operand, this represents a relocation containing
197    /// higher 16 bit of the address. Used only via movt instruction.
198    MO_HI16
199  };
200}
201
202class ARMBaseInstrInfo : public TargetInstrInfoImpl {
203  const ARMSubtarget &Subtarget;
204protected:
205  // Can be only subclassed.
206  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
207public:
208  // Return the non-pre/post incrementing version of 'Opc'. Return 0
209  // if there is not such an opcode.
210  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
211
212  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
213                                              MachineBasicBlock::iterator &MBBI,
214                                              LiveVariables *LV) const;
215
216  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
217  const ARMSubtarget &getSubtarget() const { return Subtarget; }
218
219  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
220                                 MachineBasicBlock::iterator MI,
221                                 const std::vector<CalleeSavedInfo> &CSI,
222                                 const TargetRegisterInfo *TRI) const;
223
224  // Branch analysis.
225  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
226                             MachineBasicBlock *&FBB,
227                             SmallVectorImpl<MachineOperand> &Cond,
228                             bool AllowModify = false) const;
229  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
230  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
231                                MachineBasicBlock *FBB,
232                                const SmallVectorImpl<MachineOperand> &Cond,
233                                DebugLoc DL) const;
234
235  virtual
236  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
237
238  // Predication support.
239  bool isPredicated(const MachineInstr *MI) const {
240    int PIdx = MI->findFirstPredOperandIdx();
241    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
242  }
243
244  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
245    int PIdx = MI->findFirstPredOperandIdx();
246    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
247                      : ARMCC::AL;
248  }
249
250  virtual
251  bool PredicateInstruction(MachineInstr *MI,
252                            const SmallVectorImpl<MachineOperand> &Pred) const;
253
254  virtual
255  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
256                         const SmallVectorImpl<MachineOperand> &Pred2) const;
257
258  virtual bool DefinesPredicate(MachineInstr *MI,
259                                std::vector<MachineOperand> &Pred) const;
260
261  virtual bool isPredicable(MachineInstr *MI) const;
262
263  /// GetInstSize - Returns the size of the specified MachineInstr.
264  ///
265  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
266
267  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
268                                       int &FrameIndex) const;
269  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
270                                      int &FrameIndex) const;
271
272  virtual void copyPhysReg(MachineBasicBlock &MBB,
273                           MachineBasicBlock::iterator I, DebugLoc DL,
274                           unsigned DestReg, unsigned SrcReg,
275                           bool KillSrc) const;
276
277  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
278                                   MachineBasicBlock::iterator MBBI,
279                                   unsigned SrcReg, bool isKill, int FrameIndex,
280                                   const TargetRegisterClass *RC,
281                                   const TargetRegisterInfo *TRI) const;
282
283  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
284                                    MachineBasicBlock::iterator MBBI,
285                                    unsigned DestReg, int FrameIndex,
286                                    const TargetRegisterClass *RC,
287                                    const TargetRegisterInfo *TRI) const;
288
289  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
290                                                 int FrameIx,
291                                                 uint64_t Offset,
292                                                 const MDNode *MDPtr,
293                                                 DebugLoc DL) const;
294
295  virtual void reMaterialize(MachineBasicBlock &MBB,
296                             MachineBasicBlock::iterator MI,
297                             unsigned DestReg, unsigned SubIdx,
298                             const MachineInstr *Orig,
299                             const TargetRegisterInfo &TRI) const;
300
301  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
302
303  virtual bool produceSameValue(const MachineInstr *MI0,
304                                const MachineInstr *MI1) const;
305
306  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
307  /// determine if two loads are loading from the same base address. It should
308  /// only return true if the base pointers are the same and the only
309  /// differences between the two addresses is the offset. It also returns the
310  /// offsets by reference.
311  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
312                                       int64_t &Offset1, int64_t &Offset2)const;
313
314  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
315  /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
316  /// be scheduled togther. On some targets if two loads are loading from
317  /// addresses in the same cache line, it's better if they are scheduled
318  /// together. This function takes two integers that represent the load offsets
319  /// from the common base address. It returns true if it decides it's desirable
320  /// to schedule the two loads together. "NumLoads" is the number of loads that
321  /// have already been scheduled after Load1.
322  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
323                                       int64_t Offset1, int64_t Offset2,
324                                       unsigned NumLoads) const;
325
326  virtual bool isSchedulingBoundary(const MachineInstr *MI,
327                                    const MachineBasicBlock *MBB,
328                                    const MachineFunction &MF) const;
329
330  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
331                                   unsigned NumInstrs) const;
332
333  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
334                                   MachineBasicBlock &FMBB,unsigned NumF) const;
335
336  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
337                                         unsigned NumInstrs) const {
338    return NumInstrs && NumInstrs == 1;
339  }
340
341  /// AnalyzeCompare - For a comparison instruction, return the source register
342  /// in SrcReg and the value it compares against in CmpValue. Return true if
343  /// the comparison instruction can be analyzed.
344  virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
345                              int &CmpValue) const;
346
347  /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so
348  /// that we can remove a "comparison with zero".
349  virtual bool ConvertToSetZeroFlag(MachineInstr *Instr,
350                                    MachineInstr *CmpInstr) const;
351
352  virtual unsigned getNumMicroOps(const MachineInstr *MI,
353                                  const InstrItineraryData *ItinData) const;
354};
355
356static inline
357const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
358  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
359}
360
361static inline
362const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
363  return MIB.addReg(0);
364}
365
366static inline
367const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
368                                          bool isDead = false) {
369  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
370}
371
372static inline
373const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
374  return MIB.addReg(0);
375}
376
377static inline
378bool isUncondBranchOpcode(int Opc) {
379  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
380}
381
382static inline
383bool isCondBranchOpcode(int Opc) {
384  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
385}
386
387static inline
388bool isJumpTableBranchOpcode(int Opc) {
389  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
390    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
391}
392
393static inline
394bool isIndirectBranchOpcode(int Opc) {
395  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
396}
397
398/// getInstrPredicate - If instruction is predicated, returns its predicate
399/// condition, otherwise returns AL. It also returns the condition code
400/// register by reference.
401ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
402
403int getMatchingCondBranchOpcode(int Opc);
404
405/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
406/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
407/// code.
408void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
409                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
410                             unsigned DestReg, unsigned BaseReg, int NumBytes,
411                             ARMCC::CondCodes Pred, unsigned PredReg,
412                             const ARMBaseInstrInfo &TII);
413
414void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
415                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
416                            unsigned DestReg, unsigned BaseReg, int NumBytes,
417                            ARMCC::CondCodes Pred, unsigned PredReg,
418                            const ARMBaseInstrInfo &TII);
419
420
421/// rewriteARMFrameIndex / rewriteT2FrameIndex -
422/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
423/// offset could not be handled directly in MI, and return the left-over
424/// portion by reference.
425bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
426                          unsigned FrameReg, int &Offset,
427                          const ARMBaseInstrInfo &TII);
428
429bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
430                         unsigned FrameReg, int &Offset,
431                         const ARMBaseInstrInfo &TII);
432
433} // End llvm namespace
434
435#endif
436