ARMBaseInstrInfo.h revision a0792de66c8364d47b0a688c7f408efb7b10f31b
14d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===// 2fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman// 3b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// The LLVM Compiler Infrastructure 4b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman// 8b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell//===----------------------------------------------------------------------===// 94d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner// 104d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner// This file contains the Base ARM implementation of the TargetInstrInfo class. 114d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner// 124d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner//===----------------------------------------------------------------------===// 134d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 144d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner#ifndef ARMBASEINSTRUCTIONINFO_H 154d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner#define ARMBASEINSTRUCTIONINFO_H 1681ebc300891a81c305258aed980567514dff952dChris Lattner 176cc8a93c486f889c5767278508bc655942ba408eChris Lattner#include "ARM.h" 18c79e1182470ed12f1f3d0d35c1725366519a9af7Devang Patel#include "llvm/CodeGen/MachineInstrBuilder.h" 19c5f52e6da18e6e8ccb62aac2a4cb431df98e7d6dChris Lattner#include "llvm/Target/TargetInstrInfo.h" 207822c2ae077429d7bf6eb3f6ebf99d61f359b601Chris Lattner 21cf11035a6f9973d68d8eaf837d71dcf272d36b79Chris Lattnernamespace llvm { 22741c0aea08feab0ebd1932aaa8dd38836b2073eaChris Lattner class ARMSubtarget; 230a205a459884ec745df1c529396dd921f029dafdOwen Anderson class ARMBaseRegisterInfo; 24afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman 25cbbc6b74e357afbf8fb37fdeb177ed78021092d3Chris Lattner/// ARMII - This namespace holds all of the target specific flags that 26c79e1182470ed12f1f3d0d35c1725366519a9af7Devang Patel/// instruction info tracks. 27f006b183e2d2bebcf6968d1dd7350397c95b0325Victor Hernandez/// 28ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifternamespace ARMII { 299fa038dc21e966dceb23f9410351e863e3ce1114Chris Lattner enum { 30c5f52e6da18e6e8ccb62aac2a4cb431df98e7d6dChris Lattner //===------------------------------------------------------------------===// 31c5f52e6da18e6e8ccb62aac2a4cb431df98e7d6dChris Lattner // Instruction Flags. 32abbc2dd77908f146f73f4cd1abfdfe47faacf43dChris Lattner 33d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke //===------------------------------------------------------------------===// 344d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // This four-bit field describes the addressing mode used. 356cc8a93c486f889c5767278508bc655942ba408eChris Lattner 366cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeMask = 0x1f, 376cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeNone = 0, 386cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode1 = 1, 396cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode2 = 2, 406cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode3 = 3, 416cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode4 = 4, 426cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode5 = 5, 436cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrMode6 = 6, 446cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT1_1 = 7, 456cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT1_2 = 8, 466cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT1_4 = 9, 476cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data 486cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT2_i12 = 11, 496cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT2_i8 = 12, 506cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT2_so = 13, 516cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT2_pc = 14, // +/- i12 for pc relative data 526cc8a93c486f889c5767278508bc655942ba408eChris Lattner AddrModeT2_i8s4 = 15, // i8 * 4 536cc8a93c486f889c5767278508bc655942ba408eChris Lattner 546cc8a93c486f889c5767278508bc655942ba408eChris Lattner // Size* - Flags to keep track of the size of an instruction. 556cc8a93c486f889c5767278508bc655942ba408eChris Lattner SizeShift = 5, 566cc8a93c486f889c5767278508bc655942ba408eChris Lattner SizeMask = 7 << SizeShift, 576cc8a93c486f889c5767278508bc655942ba408eChris Lattner SizeSpecial = 1, // 0 byte pseudo or special case. 586cc8a93c486f889c5767278508bc655942ba408eChris Lattner Size8Bytes = 2, 596cc8a93c486f889c5767278508bc655942ba408eChris Lattner Size4Bytes = 3, 606cc8a93c486f889c5767278508bc655942ba408eChris Lattner Size2Bytes = 4, 616cc8a93c486f889c5767278508bc655942ba408eChris Lattner 626cc8a93c486f889c5767278508bc655942ba408eChris Lattner // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load 63046e78ce55a7c3d82b7b6758d2d77f2d99f970bfVictor Hernandez // and store ops only. Generic "updating" flag is used for ld/st multiple. 64046e78ce55a7c3d82b7b6758d2d77f2d99f970bfVictor Hernandez IndexModeShift = 8, 656cc8a93c486f889c5767278508bc655942ba408eChris Lattner IndexModeMask = 3 << IndexModeShift, 666cc8a93c486f889c5767278508bc655942ba408eChris Lattner IndexModePre = 1, 676cc8a93c486f889c5767278508bc655942ba408eChris Lattner IndexModePost = 2, 686cc8a93c486f889c5767278508bc655942ba408eChris Lattner IndexModeUpd = 3, 696cc8a93c486f889c5767278508bc655942ba408eChris Lattner 706cc8a93c486f889c5767278508bc655942ba408eChris Lattner //===------------------------------------------------------------------===// 716cc8a93c486f889c5767278508bc655942ba408eChris Lattner // Instruction encoding formats. 726cc8a93c486f889c5767278508bc655942ba408eChris Lattner // 736cc8a93c486f889c5767278508bc655942ba408eChris Lattner FormShift = 10, 746cc8a93c486f889c5767278508bc655942ba408eChris Lattner FormMask = 0x3f << FormShift, 756cc8a93c486f889c5767278508bc655942ba408eChris Lattner 766cc8a93c486f889c5767278508bc655942ba408eChris Lattner // Pseudo instructions 776cc8a93c486f889c5767278508bc655942ba408eChris Lattner Pseudo = 0 << FormShift, 783481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner 794d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Multiply instructions 804d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner MulFrm = 1 << FormShift, 814d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 824d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Branch instructions 834d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner BrFrm = 2 << FormShift, 844d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner BrMiscFrm = 3 << FormShift, 85abbc2dd77908f146f73f4cd1abfdfe47faacf43dChris Lattner 8676ae3445f81164aaff9f95123426109c119f27c0Chris Lattner // Data Processing instructions 87fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman DPFrm = 4 << FormShift, 884d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner DPSoRegFrm = 5 << FormShift, 894d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 904d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Load and Store 91c1bb13f1b8794aa6f3219b3ac567f569ad78a6d1Gabor Greif LdFrm = 6 << FormShift, 92c1bb13f1b8794aa6f3219b3ac567f569ad78a6d1Gabor Greif StFrm = 7 << FormShift, 934d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner LdMiscFrm = 8 << FormShift, 946b6b6ef1677fa71b1072c2911b4c1f9524a558c9Zhou Sheng StMiscFrm = 9 << FormShift, 954d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner LdStMulFrm = 10 << FormShift, 964d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 97579dca12c2cfd60bc18aaadbd5331897d48fec29Reid Spencer LdStExFrm = 11 << FormShift, 98579dca12c2cfd60bc18aaadbd5331897d48fec29Reid Spencer 994d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Miscellaneous arithmetic instructions 100fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman ArithMiscFrm = 12 << FormShift, 101fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman SatFrm = 13 << FormShift, 1024d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 1034d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Extend instructions 1044d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner ExtFrm = 14 << FormShift, 1054d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 1064d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // VFP formats 1074d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPUnaryFrm = 15 << FormShift, 1084d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPBinaryFrm = 16 << FormShift, 1094d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPConv1Frm = 17 << FormShift, 1104d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPConv2Frm = 18 << FormShift, 1114d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPConv3Frm = 19 << FormShift, 1124d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner VFPConv4Frm = 20 << FormShift, 1130a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner VFPConv5Frm = 21 << FormShift, 1140a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner VFPLdStFrm = 22 << FormShift, 1150a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner VFPLdStMulFrm = 23 << FormShift, 116fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman VFPMiscFrm = 24 << FormShift, 1174d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 1184d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Thumb format 1194d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner ThumbFrm = 25 << FormShift, 1204d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 1214d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // Miscelleaneous format 1224d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner MiscFrm = 26 << FormShift, 1234d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 1244d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner // NEON formats 1254d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner NGetLnFrm = 27 << FormShift, 1264d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner NSetLnFrm = 28 << FormShift, 1274d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner NDupFrm = 29 << FormShift, 1280a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner NLdStFrm = 30 << FormShift, 1290a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner N1RegModImmFrm= 31 << FormShift, 1300a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner N2RegFrm = 32 << FormShift, 1310a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner NVCVTFrm = 33 << FormShift, 13210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner NVDupLnFrm = 34 << FormShift, 13310b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner N2RegVShLFrm = 35 << FormShift, 13410b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner N2RegVShRFrm = 36 << FormShift, 13510b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner N3RegFrm = 37 << FormShift, 1367d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner N3RegVShFrm = 38 << FormShift, 1377d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner NVExtFrm = 39 << FormShift, 1387d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner NVMulSLFrm = 40 << FormShift, 13910b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner NVTBLFrm = 41 << FormShift, 1400a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 14110b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner //===------------------------------------------------------------------===// 14210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // Misc flags. 14310b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 14410b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // UnaryDP - Indicates this is a unary data processing instruction, i.e. 14510b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // it doesn't have a Rn operand. 14610b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner UnaryDP = 1 << 16, 14710b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 1487d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 1497d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner // a 16-bit Thumb instruction if certain conditions are met. 1507d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner Xform16Bit = 1 << 17, 1510a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 1527d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner //===------------------------------------------------------------------===// 1537d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner // Code domain. 1547d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner DomainShift = 18, 1557d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner DomainMask = 3 << DomainShift, 1567d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner DomainGeneral = 0 << DomainShift, 1577d6c24cdbf41522818ec9ae7b8d3b624660853c1Chris Lattner DomainVFP = 1 << DomainShift, 15810b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner DomainNEON = 2 << DomainShift, 15910b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 16010b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner //===------------------------------------------------------------------===// 16110b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // Field shifts - such shifts are used to set field while generating 16210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // machine instructions. 163694e37f08a7c09ccc24642532106295cf7b3a1e3Chris Lattner M_BitShift = 5, 16410b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner ShiftImmShift = 5, 16510b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner ShiftShift = 7, 16610b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner N_BitShift = 7, 16710b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner ImmHiShift = 8, 168694e37f08a7c09ccc24642532106295cf7b3a1e3Chris Lattner SoRotImmShift = 8, 169694e37f08a7c09ccc24642532106295cf7b3a1e3Chris Lattner RegRsShift = 8, 17010b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner ExtRotImmShift = 10, 17110b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner RegRdLoShift = 12, 17210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner RegRdShift = 12, 1730a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner RegRdHiShift = 16, 174051a950000e21935165db56695e35bade668193bGabor Greif RegRnShift = 16, 17510b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner S_BitShift = 20, 17610b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner W_BitShift = 21, 17710b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner AM3_I_BitShift = 22, 17810b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner D_BitShift = 22, 17910b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner U_BitShift = 23, 18010b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner P_BitShift = 24, 18110b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner I_BitShift = 25, 18210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner CondShift = 28 18310b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner }; 18410b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner} 18510b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 18610b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattnerclass ARMBaseInstrInfo : public TargetInstrInfoImpl { 1870a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner const ARMSubtarget &Subtarget; 18810b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattnerprotected: 18910b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // Can be only subclassed. 1900a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 1910a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattnerpublic: 1920a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner // Return the non-pre/post incrementing version of 'Opc'. Return 0 19310b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner // if there is not such an opcode. 19410b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 195333c40096561218bc3597cf153c0a3895274414cOwen Anderson 196333c40096561218bc3597cf153c0a3895274414cOwen Anderson virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 1970a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner MachineBasicBlock::iterator &MBBI, 198051a950000e21935165db56695e35bade668193bGabor Greif LiveVariables *LV) const; 19910b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 2000a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; 2011adec83ae84031bfa9f0bf209c5ee6c64906a1ffDan Gohman const ARMSubtarget &getSubtarget() const { return Subtarget; } 20210b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner 20310b1f5a94196f27c75c950ba7ed26bd0a62c91e9Chris Lattner bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2040a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner MachineBasicBlock::iterator MI, 2050a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner const std::vector<CalleeSavedInfo> &CSI, 2060a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner const TargetRegisterInfo *TRI) const; 2070a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 2080a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner // Branch analysis. 2090a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 2100a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner MachineBasicBlock *&FBB, 2110a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner SmallVectorImpl<MachineOperand> &Cond, 2120a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner bool AllowModify = false) const; 2130a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 2140a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2150a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner MachineBasicBlock *FBB, 2160a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner const SmallVectorImpl<MachineOperand> &Cond, 2170a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner DebugLoc DL) const; 2180a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 2190a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual 2200a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 2210a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 2220a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner // Predication support. 2230a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner bool isPredicated(const MachineInstr *MI) const { 2240a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner int PIdx = MI->findFirstPredOperandIdx(); 2250a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 2260a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner } 2270a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner 2280a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 2290a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner int PIdx = MI->findFirstPredOperandIdx(); 2300a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 2310a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner : ARMCC::AL; 2320a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner } 2334d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 2340a4c6789d5adafb6eb33080fe1833b416a152d7cChris Lattner virtual 2354d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner bool PredicateInstruction(MachineInstr *MI, 2364d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner const SmallVectorImpl<MachineOperand> &Pred) const; 2374d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 2384d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner virtual 2394d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 2404d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner const SmallVectorImpl<MachineOperand> &Pred2) const; 2414d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner 2424d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner virtual bool DefinesPredicate(MachineInstr *MI, 2433481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner std::vector<MachineOperand> &Pred) const; 2443481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner 2453481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner virtual bool isPredicable(MachineInstr *MI) const; 246abbc2dd77908f146f73f4cd1abfdfe47faacf43dChris Lattner 247ec710c5b12af647ae90f53917122726269c18738Chris Lattner /// GetInstSize - Returns the size of the specified MachineInstr. 24800b16889ab461b7ecef1c91ade101186b7f1fce2Jeff Cohen /// 249127a7936dea7b86e5cad337ad4b537bc115c2588Dale Johannesen virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 250127a7936dea7b86e5cad337ad4b537bc115c2588Dale Johannesen 251ec710c5b12af647ae90f53917122726269c18738Chris Lattner virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 2527af1c78b98d2df7d0ab9154461ca3d835706716eDuncan Sands int &FrameIndex) const; 2537af1c78b98d2df7d0ab9154461ca3d835706716eDuncan Sands virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 2547af1c78b98d2df7d0ab9154461ca3d835706716eDuncan Sands int &FrameIndex) const; 2557af1c78b98d2df7d0ab9154461ca3d835706716eDuncan Sands 256741c0aea08feab0ebd1932aaa8dd38836b2073eaChris Lattner virtual void copyPhysReg(MachineBasicBlock &MBB, 257741c0aea08feab0ebd1932aaa8dd38836b2073eaChris Lattner MachineBasicBlock::iterator I, DebugLoc DL, 258741c0aea08feab0ebd1932aaa8dd38836b2073eaChris Lattner unsigned DestReg, unsigned SrcReg, 259741c0aea08feab0ebd1932aaa8dd38836b2073eaChris Lattner bool KillSrc) const; 260ec710c5b12af647ae90f53917122726269c18738Chris Lattner 2614d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 2624d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner MachineBasicBlock::iterator MBBI, 2633481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner unsigned SrcReg, bool isKill, int FrameIndex, 2643481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner const TargetRegisterClass *RC, 2653481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner const TargetRegisterInfo *TRI) const; 26635738ac150afafe2359268d4b2169498c6c98c5fDan Gohman 2673481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 2687605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner MachineBasicBlock::iterator MBBI, 2697605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner unsigned DestReg, int FrameIndex, 2703481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner const TargetRegisterClass *RC, 2717605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner const TargetRegisterInfo *TRI) const; 2727605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner 2733481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 2747605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner int FrameIx, 275e9d87f49063cb1bd213d8e9c339b9b63393cc2d9Dan Gohman uint64_t Offset, 2762872177834d83b42cd042a37299cb7089965f36bChris Lattner const MDNode *MDPtr, 2777605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner DebugLoc DL) const; 2787605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner 2797605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner virtual void reMaterialize(MachineBasicBlock &MBB, 2807605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner MachineBasicBlock::iterator MI, 2817605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner unsigned DestReg, unsigned SubIdx, 2827605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner const MachineInstr *Orig, 2837605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner const TargetRegisterInfo &TRI) const; 2847605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner 2857605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const; 2867605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner 2877605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner virtual bool produceSameValue(const MachineInstr *MI0, 2887605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner const MachineInstr *MI1) const; 2897605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner 2907605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 2917605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner /// determine if two loads are loading from the same base address. It should 2927605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner /// only return true if the base pointers are the same and the only 2937605730ba8eaf248a8285bb2055e131f13c15b63Chris Lattner /// differences between the two addresses is the offset. It also returns the 2944d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner /// offsets by reference. 2954d1e46e7b06534cde262d32fad038135f406b6b7Chris Lattner virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 296b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int64_t &Offset1, int64_t &Offset2)const; 297afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman 298afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 299afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 300afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// be scheduled togther. On some targets if two loads are loading from 301afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// addresses in the same cache line, it's better if they are scheduled 302afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// together. This function takes two integers that represent the load offsets 30335738ac150afafe2359268d4b2169498c6c98c5fDan Gohman /// from the common base address. It returns true if it decides it's desirable 304afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// to schedule the two loads together. "NumLoads" is the number of loads that 305afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman /// have already been scheduled after Load1. 306afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 307afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman int64_t Offset1, int64_t Offset2, 308afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman unsigned NumLoads) const; 309afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman 310afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman virtual bool isSchedulingBoundary(const MachineInstr *MI, 311afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman const MachineBasicBlock *MBB, 312afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman const MachineFunction &MF) const; 3137af1c78b98d2df7d0ab9154461ca3d835706716eDuncan Sands 314afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 315afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman unsigned NumInstrs, 316afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman float Prob, float Confidence) const; 317afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman 318afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT, 319afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman MachineBasicBlock &FMBB,unsigned NumF, 3209e9a0d5fc26878e51a58a8b57900fcbf952c2691Owen Anderson float Probability, float Confidence) const; 32135738ac150afafe2359268d4b2169498c6c98c5fDan Gohman 322afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 323afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman unsigned NumInstrs, 324afc36a9520971832dfbebc0333593bf5d3098296Dan Gohman float Probability, 3253481f24c06b3c9de48bdd99c37547471ca8e761eChris Lattner float Confidence) const { 326b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner return NumInstrs && NumInstrs == 1; 327b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner } 328b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner 329b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner /// AnalyzeCompare - For a comparison instruction, return the source register 330b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner /// in SrcReg and the value it compares against in CmpValue. Return true if 331b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner /// the comparison instruction can be analyzed. 332b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 333b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int &CmpMask, int &CmpValue) const; 334b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner 335ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter /// OptimizeCompareInstr - Convert the instruction to set the zero flag so 336b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner /// that we can remove a "comparison with zero". 337b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 338b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int CmpMask, int CmpValue, 339b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner MachineBasicBlock::iterator &MII) const; 3409e9a0d5fc26878e51a58a8b57900fcbf952c2691Owen Anderson 341b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner virtual unsigned getNumMicroOps(const MachineInstr *MI, 342b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner const InstrItineraryData *ItinData) const; 343b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner 344b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner virtual 345b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int getOperandLatency(const InstrItineraryData *ItinData, 346b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner const MachineInstr *DefMI, unsigned DefIdx, 347b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner const MachineInstr *UseMI, unsigned UseIdx) const; 348b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner virtual 349b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int getOperandLatency(const InstrItineraryData *ItinData, 350b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner SDNode *DefNode, unsigned DefIdx, 351b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner SDNode *UseNode, unsigned UseIdx) const; 352b29714a10af94b6daae437e48a82ae32675f79cbChris Lattnerprivate: 353b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner int getOperandLatency(const InstrItineraryData *ItinData, 354b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner const TargetInstrDesc &DefTID, 355ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter unsigned DefIdx, unsigned DefAlign, 356ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter const TargetInstrDesc &UseTID, 357ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter unsigned UseIdx, unsigned UseAlign) const; 358ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter}; 359ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifter 360ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifterstatic inline 361ad80981a106c9d0ec83351e63ee3ac75ed646bf4Andreas Neustifterconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 362b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 363b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner} 364b29714a10af94b6daae437e48a82ae32675f79cbChris Lattner 3654afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelstatic inline 3664afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 3674afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel return MIB.addReg(0); 3684afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel} 3694afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel 3704afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelstatic inline 3714afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelconst MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 3724afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel bool isDead = false) { 3734afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 3744afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel} 3754afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel 3764afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelstatic inline 3774afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelconst MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 3784afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel return MIB.addReg(0); 3794afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel} 3804afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel 3814afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelstatic inline 3824afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelbool isUncondBranchOpcode(int Opc) { 3834afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 3844afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel} 3854afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patel 3864afc90dacf309999d8b7f6c2b4b0c56af346bab5Devang Patelstatic inline 387c79e1182470ed12f1f3d0d35c1725366519a9af7Devang Patelbool isCondBranchOpcode(int Opc) { 388 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 389} 390 391static inline 392bool isJumpTableBranchOpcode(int Opc) { 393 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 394 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 395} 396 397static inline 398bool isIndirectBranchOpcode(int Opc) { 399 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 400} 401 402/// getInstrPredicate - If instruction is predicated, returns its predicate 403/// condition, otherwise returns AL. It also returns the condition code 404/// register by reference. 405ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 406 407int getMatchingCondBranchOpcode(int Opc); 408 409/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 410/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 411/// code. 412void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 413 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 414 unsigned DestReg, unsigned BaseReg, int NumBytes, 415 ARMCC::CondCodes Pred, unsigned PredReg, 416 const ARMBaseInstrInfo &TII); 417 418void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 419 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 420 unsigned DestReg, unsigned BaseReg, int NumBytes, 421 ARMCC::CondCodes Pred, unsigned PredReg, 422 const ARMBaseInstrInfo &TII); 423 424 425/// rewriteARMFrameIndex / rewriteT2FrameIndex - 426/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 427/// offset could not be handled directly in MI, and return the left-over 428/// portion by reference. 429bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 430 unsigned FrameReg, int &Offset, 431 const ARMBaseInstrInfo &TII); 432 433bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 434 unsigned FrameReg, int &Offset, 435 const ARMBaseInstrInfo &TII); 436 437} // End llvm namespace 438 439#endif 440