ARMBaseInstrInfo.h revision b3a6817d06ab88f410012b5c5cc17fc4f07058c3 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseRegisterInfo;
24
25/// ARMII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace ARMII {
29  enum {
30    //===------------------------------------------------------------------===//
31    // Instruction Flags.
32
33    //===------------------------------------------------------------------===//
34    // This four-bit field describes the addressing mode used.
35
36    AddrModeMask  = 0x1f,
37    AddrModeNone    = 0,
38    AddrMode1       = 1,
39    AddrMode2       = 2,
40    AddrMode3       = 3,
41    AddrMode4       = 4,
42    AddrMode5       = 5,
43    AddrMode6       = 6,
44    AddrModeT1_1    = 7,
45    AddrModeT1_2    = 8,
46    AddrModeT1_4    = 9,
47    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
48    AddrModeT2_i12  = 11,
49    AddrModeT2_i8   = 12,
50    AddrModeT2_so   = 13,
51    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
52    AddrModeT2_i8s4 = 15, // i8 * 4
53
54    // Size* - Flags to keep track of the size of an instruction.
55    SizeShift     = 5,
56    SizeMask      = 7 << SizeShift,
57    SizeSpecial   = 1,   // 0 byte pseudo or special case.
58    Size8Bytes    = 2,
59    Size4Bytes    = 3,
60    Size2Bytes    = 4,
61
62    // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63    // and store ops only.  Generic "updating" flag is used for ld/st multiple.
64    IndexModeShift = 8,
65    IndexModeMask  = 3 << IndexModeShift,
66    IndexModePre   = 1,
67    IndexModePost  = 2,
68    IndexModeUpd   = 3,
69
70    //===------------------------------------------------------------------===//
71    // Instruction encoding formats.
72    //
73    FormShift     = 10,
74    FormMask      = 0x3f << FormShift,
75
76    // Pseudo instructions
77    Pseudo        = 0  << FormShift,
78
79    // Multiply instructions
80    MulFrm        = 1  << FormShift,
81
82    // Branch instructions
83    BrFrm         = 2  << FormShift,
84    BrMiscFrm     = 3  << FormShift,
85
86    // Data Processing instructions
87    DPFrm         = 4  << FormShift,
88    DPSoRegFrm    = 5  << FormShift,
89
90    // Load and Store
91    LdFrm         = 6  << FormShift,
92    StFrm         = 7  << FormShift,
93    LdMiscFrm     = 8  << FormShift,
94    StMiscFrm     = 9  << FormShift,
95    LdStMulFrm    = 10 << FormShift,
96
97    LdStExFrm     = 11 << FormShift,
98
99    // Miscellaneous arithmetic instructions
100    ArithMiscFrm  = 12 << FormShift,
101    SatFrm        = 13 << FormShift,
102
103    // Extend instructions
104    ExtFrm        = 14 << FormShift,
105
106    // VFP formats
107    VFPUnaryFrm   = 15 << FormShift,
108    VFPBinaryFrm  = 16 << FormShift,
109    VFPConv1Frm   = 17 << FormShift,
110    VFPConv2Frm   = 18 << FormShift,
111    VFPConv3Frm   = 19 << FormShift,
112    VFPConv4Frm   = 20 << FormShift,
113    VFPConv5Frm   = 21 << FormShift,
114    VFPLdStFrm    = 22 << FormShift,
115    VFPLdStMulFrm = 23 << FormShift,
116    VFPMiscFrm    = 24 << FormShift,
117
118    // Thumb format
119    ThumbFrm      = 25 << FormShift,
120
121    // Miscelleaneous format
122    MiscFrm       = 26 << FormShift,
123
124    // NEON formats
125    NGetLnFrm     = 27 << FormShift,
126    NSetLnFrm     = 28 << FormShift,
127    NDupFrm       = 29 << FormShift,
128    NLdStFrm      = 30 << FormShift,
129    N1RegModImmFrm= 31 << FormShift,
130    N2RegFrm      = 32 << FormShift,
131    NVCVTFrm      = 33 << FormShift,
132    NVDupLnFrm    = 34 << FormShift,
133    N2RegVShLFrm  = 35 << FormShift,
134    N2RegVShRFrm  = 36 << FormShift,
135    N3RegFrm      = 37 << FormShift,
136    N3RegVShFrm   = 38 << FormShift,
137    NVExtFrm      = 39 << FormShift,
138    NVMulSLFrm    = 40 << FormShift,
139    NVTBLFrm      = 41 << FormShift,
140
141    //===------------------------------------------------------------------===//
142    // Misc flags.
143
144    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
145    // it doesn't have a Rn operand.
146    UnaryDP       = 1 << 16,
147
148    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
149    // a 16-bit Thumb instruction if certain conditions are met.
150    Xform16Bit    = 1 << 17,
151
152    //===------------------------------------------------------------------===//
153    // Code domain.
154    DomainShift   = 18,
155    DomainMask    = 3 << DomainShift,
156    DomainGeneral = 0 << DomainShift,
157    DomainVFP     = 1 << DomainShift,
158    DomainNEON    = 2 << DomainShift,
159
160    //===------------------------------------------------------------------===//
161    // Field shifts - such shifts are used to set field while generating
162    // machine instructions.
163    //
164    // FIXME: This list will need adjusting/fixing as the MC code emitter
165    // takes shape and the ARMCodeEmitter.cpp bits go away.
166    ShiftTypeShift = 4,
167
168    M_BitShift     = 5,
169    ShiftImmShift  = 5,
170    ShiftShift     = 7,
171    N_BitShift     = 7,
172    ImmHiShift     = 8,
173    SoRotImmShift  = 8,
174    RegRsShift     = 8,
175    ExtRotImmShift = 10,
176    RegRdLoShift   = 12,
177    RegRdShift     = 12,
178    RegRdHiShift   = 16,
179    RegRnShift     = 16,
180    S_BitShift     = 20,
181    W_BitShift     = 21,
182    AM3_I_BitShift = 22,
183    D_BitShift     = 22,
184    U_BitShift     = 23,
185    P_BitShift     = 24,
186    I_BitShift     = 25,
187    CondShift      = 28
188  };
189}
190
191class ARMBaseInstrInfo : public TargetInstrInfoImpl {
192  const ARMSubtarget &Subtarget;
193protected:
194  // Can be only subclassed.
195  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
196public:
197  // Return the non-pre/post incrementing version of 'Opc'. Return 0
198  // if there is not such an opcode.
199  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
200
201  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
202                                              MachineBasicBlock::iterator &MBBI,
203                                              LiveVariables *LV) const;
204
205  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
206  const ARMSubtarget &getSubtarget() const { return Subtarget; }
207
208  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
209                                 MachineBasicBlock::iterator MI,
210                                 const std::vector<CalleeSavedInfo> &CSI,
211                                 const TargetRegisterInfo *TRI) const;
212
213  // Branch analysis.
214  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
215                             MachineBasicBlock *&FBB,
216                             SmallVectorImpl<MachineOperand> &Cond,
217                             bool AllowModify = false) const;
218  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
219  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
220                                MachineBasicBlock *FBB,
221                                const SmallVectorImpl<MachineOperand> &Cond,
222                                DebugLoc DL) const;
223
224  virtual
225  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
226
227  // Predication support.
228  bool isPredicated(const MachineInstr *MI) const {
229    int PIdx = MI->findFirstPredOperandIdx();
230    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
231  }
232
233  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
234    int PIdx = MI->findFirstPredOperandIdx();
235    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
236                      : ARMCC::AL;
237  }
238
239  virtual
240  bool PredicateInstruction(MachineInstr *MI,
241                            const SmallVectorImpl<MachineOperand> &Pred) const;
242
243  virtual
244  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
245                         const SmallVectorImpl<MachineOperand> &Pred2) const;
246
247  virtual bool DefinesPredicate(MachineInstr *MI,
248                                std::vector<MachineOperand> &Pred) const;
249
250  virtual bool isPredicable(MachineInstr *MI) const;
251
252  /// GetInstSize - Returns the size of the specified MachineInstr.
253  ///
254  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
255
256  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
257                                       int &FrameIndex) const;
258  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
259                                      int &FrameIndex) const;
260
261  virtual void copyPhysReg(MachineBasicBlock &MBB,
262                           MachineBasicBlock::iterator I, DebugLoc DL,
263                           unsigned DestReg, unsigned SrcReg,
264                           bool KillSrc) const;
265
266  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
267                                   MachineBasicBlock::iterator MBBI,
268                                   unsigned SrcReg, bool isKill, int FrameIndex,
269                                   const TargetRegisterClass *RC,
270                                   const TargetRegisterInfo *TRI) const;
271
272  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
273                                    MachineBasicBlock::iterator MBBI,
274                                    unsigned DestReg, int FrameIndex,
275                                    const TargetRegisterClass *RC,
276                                    const TargetRegisterInfo *TRI) const;
277
278  virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
279                                                 int FrameIx,
280                                                 uint64_t Offset,
281                                                 const MDNode *MDPtr,
282                                                 DebugLoc DL) const;
283
284  virtual void reMaterialize(MachineBasicBlock &MBB,
285                             MachineBasicBlock::iterator MI,
286                             unsigned DestReg, unsigned SubIdx,
287                             const MachineInstr *Orig,
288                             const TargetRegisterInfo &TRI) const;
289
290  MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
291
292  virtual bool produceSameValue(const MachineInstr *MI0,
293                                const MachineInstr *MI1) const;
294
295  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
296  /// determine if two loads are loading from the same base address. It should
297  /// only return true if the base pointers are the same and the only
298  /// differences between the two addresses is the offset. It also returns the
299  /// offsets by reference.
300  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
301                                       int64_t &Offset1, int64_t &Offset2)const;
302
303  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
304  /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
305  /// be scheduled togther. On some targets if two loads are loading from
306  /// addresses in the same cache line, it's better if they are scheduled
307  /// together. This function takes two integers that represent the load offsets
308  /// from the common base address. It returns true if it decides it's desirable
309  /// to schedule the two loads together. "NumLoads" is the number of loads that
310  /// have already been scheduled after Load1.
311  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
312                                       int64_t Offset1, int64_t Offset2,
313                                       unsigned NumLoads) const;
314
315  virtual bool isSchedulingBoundary(const MachineInstr *MI,
316                                    const MachineBasicBlock *MBB,
317                                    const MachineFunction &MF) const;
318
319  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
320                                   unsigned NumInstrs,
321                                   float Prob, float Confidence) const;
322
323  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
324                                   MachineBasicBlock &FMBB,unsigned NumF,
325                                   float Probability, float Confidence) const;
326
327  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
328                                         unsigned NumInstrs,
329                                         float Probability,
330                                         float Confidence) const {
331    return NumInstrs == 1;
332  }
333
334  /// AnalyzeCompare - For a comparison instruction, return the source register
335  /// in SrcReg and the value it compares against in CmpValue. Return true if
336  /// the comparison instruction can be analyzed.
337  virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
338                              int &CmpMask, int &CmpValue) const;
339
340  /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
341  /// that we can remove a "comparison with zero".
342  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
343                                    int CmpMask, int CmpValue,
344                                    const MachineRegisterInfo *MRI,
345                                    MachineBasicBlock::iterator &MII) const;
346
347  virtual unsigned getNumMicroOps(const MachineInstr *MI,
348                                  const InstrItineraryData *ItinData) const;
349
350  virtual
351  int getOperandLatency(const InstrItineraryData *ItinData,
352                        const MachineInstr *DefMI, unsigned DefIdx,
353                        const MachineInstr *UseMI, unsigned UseIdx) const;
354  virtual
355  int getOperandLatency(const InstrItineraryData *ItinData,
356                        SDNode *DefNode, unsigned DefIdx,
357                        SDNode *UseNode, unsigned UseIdx) const;
358private:
359  int getVLDMDefCycle(const InstrItineraryData *ItinData,
360                      const TargetInstrDesc &DefTID,
361                      unsigned DefClass,
362                      unsigned DefIdx, unsigned DefAlign) const;
363  int getLDMDefCycle(const InstrItineraryData *ItinData,
364                     const TargetInstrDesc &DefTID,
365                     unsigned DefClass,
366                     unsigned DefIdx, unsigned DefAlign) const;
367  int getVSTMUseCycle(const InstrItineraryData *ItinData,
368                      const TargetInstrDesc &UseTID,
369                      unsigned UseClass,
370                      unsigned UseIdx, unsigned UseAlign) const;
371  int getSTMUseCycle(const InstrItineraryData *ItinData,
372                     const TargetInstrDesc &UseTID,
373                     unsigned UseClass,
374                     unsigned UseIdx, unsigned UseAlign) const;
375  int getOperandLatency(const InstrItineraryData *ItinData,
376                        const TargetInstrDesc &DefTID,
377                        unsigned DefIdx, unsigned DefAlign,
378                        const TargetInstrDesc &UseTID,
379                        unsigned UseIdx, unsigned UseAlign) const;
380
381  bool hasHighOperandLatency(const InstrItineraryData *ItinData,
382                             const MachineRegisterInfo *MRI,
383                             const MachineInstr *DefMI, unsigned DefIdx,
384                             const MachineInstr *UseMI, unsigned UseIdx) const;
385};
386
387static inline
388const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
389  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
390}
391
392static inline
393const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
394  return MIB.addReg(0);
395}
396
397static inline
398const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
399                                          bool isDead = false) {
400  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
401}
402
403static inline
404const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
405  return MIB.addReg(0);
406}
407
408static inline
409bool isUncondBranchOpcode(int Opc) {
410  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
411}
412
413static inline
414bool isCondBranchOpcode(int Opc) {
415  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
416}
417
418static inline
419bool isJumpTableBranchOpcode(int Opc) {
420  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
421    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
422}
423
424static inline
425bool isIndirectBranchOpcode(int Opc) {
426  return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
427}
428
429/// getInstrPredicate - If instruction is predicated, returns its predicate
430/// condition, otherwise returns AL. It also returns the condition code
431/// register by reference.
432ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
433
434int getMatchingCondBranchOpcode(int Opc);
435
436/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
437/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
438/// code.
439void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
440                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
441                             unsigned DestReg, unsigned BaseReg, int NumBytes,
442                             ARMCC::CondCodes Pred, unsigned PredReg,
443                             const ARMBaseInstrInfo &TII);
444
445void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
446                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
447                            unsigned DestReg, unsigned BaseReg, int NumBytes,
448                            ARMCC::CondCodes Pred, unsigned PredReg,
449                            const ARMBaseInstrInfo &TII);
450void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
451                               MachineBasicBlock::iterator &MBBI,
452                               unsigned DestReg, unsigned BaseReg,
453                               int NumBytes, const TargetInstrInfo &TII,
454                               const ARMBaseRegisterInfo& MRI,
455                               DebugLoc dl);
456
457
458/// rewriteARMFrameIndex / rewriteT2FrameIndex -
459/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
460/// offset could not be handled directly in MI, and return the left-over
461/// portion by reference.
462bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
463                          unsigned FrameReg, int &Offset,
464                          const ARMBaseInstrInfo &TII);
465
466bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
467                         unsigned FrameReg, int &Offset,
468                         const ARMBaseInstrInfo &TII);
469
470} // End llvm namespace
471
472#endif
473