ARMBaseInstrInfo.h revision b9803a8fa65f043c96612fa9c5aeeee12739db2b 
1//===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEINSTRUCTIONINFO_H
15#define ARMBASEINSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMRegisterInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28  enum {
29    //===------------------------------------------------------------------===//
30    // Instruction Flags.
31
32    //===------------------------------------------------------------------===//
33    // This four-bit field describes the addressing mode used.
34
35    AddrModeMask  = 0xf,
36    AddrModeNone    = 0,
37    AddrMode1       = 1,
38    AddrMode2       = 2,
39    AddrMode3       = 3,
40    AddrMode4       = 4,
41    AddrMode5       = 5,
42    AddrMode6       = 6,
43    AddrModeT1_1    = 7,
44    AddrModeT1_2    = 8,
45    AddrModeT1_4    = 9,
46    AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
47    AddrModeT2_i12  = 11,
48    AddrModeT2_i8   = 12,
49    AddrModeT2_so   = 13,
50    AddrModeT2_pc   = 14, // +/- i12 for pc relative data
51    AddrModeT2_i8s4 = 15, // i8 * 4
52
53    // Size* - Flags to keep track of the size of an instruction.
54    SizeShift     = 4,
55    SizeMask      = 7 << SizeShift,
56    SizeSpecial   = 1,   // 0 byte pseudo or special case.
57    Size8Bytes    = 2,
58    Size4Bytes    = 3,
59    Size2Bytes    = 4,
60
61    // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
62    // and store ops
63    IndexModeShift = 7,
64    IndexModeMask  = 3 << IndexModeShift,
65    IndexModePre   = 1,
66    IndexModePost  = 2,
67
68    //===------------------------------------------------------------------===//
69    // Instruction encoding formats.
70    //
71    FormShift     = 9,
72    FormMask      = 0x3f << FormShift,
73
74    // Pseudo instructions
75    Pseudo        = 0  << FormShift,
76
77    // Multiply instructions
78    MulFrm        = 1  << FormShift,
79
80    // Branch instructions
81    BrFrm         = 2  << FormShift,
82    BrMiscFrm     = 3  << FormShift,
83
84    // Data Processing instructions
85    DPFrm         = 4  << FormShift,
86    DPSoRegFrm    = 5  << FormShift,
87
88    // Load and Store
89    LdFrm         = 6  << FormShift,
90    StFrm         = 7  << FormShift,
91    LdMiscFrm     = 8  << FormShift,
92    StMiscFrm     = 9  << FormShift,
93    LdStMulFrm    = 10 << FormShift,
94
95    // Miscellaneous arithmetic instructions
96    ArithMiscFrm  = 11 << FormShift,
97
98    // Extend instructions
99    ExtFrm        = 12 << FormShift,
100
101    // VFP formats
102    VFPUnaryFrm   = 13 << FormShift,
103    VFPBinaryFrm  = 14 << FormShift,
104    VFPConv1Frm   = 15 << FormShift,
105    VFPConv2Frm   = 16 << FormShift,
106    VFPConv3Frm   = 17 << FormShift,
107    VFPConv4Frm   = 18 << FormShift,
108    VFPConv5Frm   = 19 << FormShift,
109    VFPLdStFrm    = 20 << FormShift,
110    VFPLdStMulFrm = 21 << FormShift,
111    VFPMiscFrm    = 22 << FormShift,
112
113    // Thumb format
114    ThumbFrm      = 23 << FormShift,
115
116    // NEON format
117    NEONFrm       = 24 << FormShift,
118    NEONGetLnFrm  = 25 << FormShift,
119    NEONSetLnFrm  = 26 << FormShift,
120    NEONDupFrm    = 27 << FormShift,
121
122    //===------------------------------------------------------------------===//
123    // Misc flags.
124
125    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126    // it doesn't have a Rn operand.
127    UnaryDP       = 1 << 15,
128
129    // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130    // a 16-bit Thumb instruction if certain conditions are met.
131    Xform16Bit    = 1 << 16,
132
133    //===------------------------------------------------------------------===//
134    // Code domain.
135    DomainShift   = 17,
136    DomainMask    = 3 << DomainShift,
137    DomainGeneral = 0 << DomainShift,
138    DomainVFP     = 1 << DomainShift,
139    DomainNEON    = 2 << DomainShift,
140
141    //===------------------------------------------------------------------===//
142    // Field shifts - such shifts are used to set field while generating
143    // machine instructions.
144    M_BitShift     = 5,
145    ShiftImmShift  = 5,
146    ShiftShift     = 7,
147    N_BitShift     = 7,
148    ImmHiShift     = 8,
149    SoRotImmShift  = 8,
150    RegRsShift     = 8,
151    ExtRotImmShift = 10,
152    RegRdLoShift   = 12,
153    RegRdShift     = 12,
154    RegRdHiShift   = 16,
155    RegRnShift     = 16,
156    S_BitShift     = 20,
157    W_BitShift     = 21,
158    AM3_I_BitShift = 22,
159    D_BitShift     = 22,
160    U_BitShift     = 23,
161    P_BitShift     = 24,
162    I_BitShift     = 25,
163    CondShift      = 28
164  };
165}
166
167class ARMBaseInstrInfo : public TargetInstrInfoImpl {
168  const ARMSubtarget& Subtarget;
169protected:
170  // Can be only subclassed.
171  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
172public:
173  // Return the non-pre/post incrementing version of 'Opc'. Return 0
174  // if there is not such an opcode.
175  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
176
177  // Return true if the block does not fall through.
178  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
179
180  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
181                                              MachineBasicBlock::iterator &MBBI,
182                                              LiveVariables *LV) const;
183
184  virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
185  const ARMSubtarget &getSubtarget() const { return Subtarget; }
186
187  // Branch analysis.
188  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
189                             MachineBasicBlock *&FBB,
190                             SmallVectorImpl<MachineOperand> &Cond,
191                             bool AllowModify) const;
192  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
193  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
194                                MachineBasicBlock *FBB,
195                            const SmallVectorImpl<MachineOperand> &Cond) const;
196
197  virtual
198  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
199
200  // Predication support.
201  bool isPredicated(const MachineInstr *MI) const {
202    int PIdx = MI->findFirstPredOperandIdx();
203    return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
204  }
205
206  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
207    int PIdx = MI->findFirstPredOperandIdx();
208    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
209                      : ARMCC::AL;
210  }
211
212  virtual
213  bool PredicateInstruction(MachineInstr *MI,
214                            const SmallVectorImpl<MachineOperand> &Pred) const;
215
216  virtual
217  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
218                         const SmallVectorImpl<MachineOperand> &Pred2) const;
219
220  virtual bool DefinesPredicate(MachineInstr *MI,
221                                std::vector<MachineOperand> &Pred) const;
222
223  /// GetInstSize - Returns the size of the specified MachineInstr.
224  ///
225  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
226
227  /// Return true if the instruction is a register to register move and return
228  /// the source and dest operands and their sub-register indices by reference.
229  virtual bool isMoveInstr(const MachineInstr &MI,
230                           unsigned &SrcReg, unsigned &DstReg,
231                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
232
233  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
234                                       int &FrameIndex) const;
235  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
236                                      int &FrameIndex) const;
237
238  virtual bool copyRegToReg(MachineBasicBlock &MBB,
239                            MachineBasicBlock::iterator I,
240                            unsigned DestReg, unsigned SrcReg,
241                            const TargetRegisterClass *DestRC,
242                            const TargetRegisterClass *SrcRC) const;
243
244  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
245                                   MachineBasicBlock::iterator MBBI,
246                                   unsigned SrcReg, bool isKill, int FrameIndex,
247                                   const TargetRegisterClass *RC) const;
248
249  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
250                                    MachineBasicBlock::iterator MBBI,
251                                    unsigned DestReg, int FrameIndex,
252                                    const TargetRegisterClass *RC) const;
253
254  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
255                                    const SmallVectorImpl<unsigned> &Ops) const;
256
257  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
258                                              MachineInstr* MI,
259                                              const SmallVectorImpl<unsigned> &Ops,
260                                              int FrameIndex) const;
261
262  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
263                                              MachineInstr* MI,
264                                           const SmallVectorImpl<unsigned> &Ops,
265                                              MachineInstr* LoadMI) const;
266};
267
268static inline
269const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
270  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
271}
272
273static inline
274const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
275  return MIB.addReg(0);
276}
277
278static inline
279const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
280                                          bool isDead = false) {
281  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
282}
283
284static inline
285const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
286  return MIB.addReg(0);
287}
288
289static inline
290bool isUncondBranchOpcode(int Opc) {
291  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
292}
293
294static inline
295bool isCondBranchOpcode(int Opc) {
296  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
297}
298
299static inline
300bool isJumpTableBranchOpcode(int Opc) {
301  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
302    Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
303}
304
305static inline
306bool isIndirectBranchOpcode(int Opc) {
307  return Opc == ARM::BRIND || Opc == ARM::tBRIND;
308}
309
310/// getInstrPredicate - If instruction is predicated, returns its predicate
311/// condition, otherwise returns AL. It also returns the condition code
312/// register by reference.
313ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
314
315int getMatchingCondBranchOpcode(int Opc);
316
317/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
318/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
319/// code.
320void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
321                             MachineBasicBlock::iterator &MBBI, DebugLoc dl,
322                             unsigned DestReg, unsigned BaseReg, int NumBytes,
323                             ARMCC::CondCodes Pred, unsigned PredReg,
324                             const ARMBaseInstrInfo &TII);
325
326void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
327                            MachineBasicBlock::iterator &MBBI, DebugLoc dl,
328                            unsigned DestReg, unsigned BaseReg, int NumBytes,
329                            ARMCC::CondCodes Pred, unsigned PredReg,
330                            const ARMBaseInstrInfo &TII);
331
332
333/// rewriteARMFrameIndex / rewriteT2FrameIndex -
334/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
335/// offset could not be handled directly in MI, and return the left-over
336/// portion by reference.
337bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
338                          unsigned FrameReg, int &Offset,
339                          const ARMBaseInstrInfo &TII);
340
341bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
342                         unsigned FrameReg, int &Offset,
343                         const ARMBaseInstrInfo &TII);
344
345} // End llvm namespace
346
347#endif
348