1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/ADT/Statistic.h"
24#include "llvm/CodeGen/JITCodeEmitter.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineJumpTableInfo.h"
29#include "llvm/CodeGen/MachineModuleInfo.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/PassManager.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMBaseInstrInfo    *II;
50    const DataLayout          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getDataLayout()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstantToMemory(unsigned CPI, const Constant *CV);
92    void emitConstPoolInstruction(const MachineInstr &MI);
93    void emitMOVi32immInstruction(const MachineInstr &MI);
94    void emitMOVi2piecesInstruction(const MachineInstr &MI);
95    void emitLEApcrelInstruction(const MachineInstr &MI);
96    void emitLEApcrelJTInstruction(const MachineInstr &MI);
97    void emitPseudoMoveInstruction(const MachineInstr &MI);
98    void addPCLabel(unsigned LabelID);
99    void emitPseudoInstruction(const MachineInstr &MI);
100    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
101                                    const MCInstrDesc &MCID,
102                                    const MachineOperand &MO,
103                                    unsigned OpIdx);
104
105    unsigned getMachineSoImmOpValue(unsigned SoImm);
106    unsigned getAddrModeSBit(const MachineInstr &MI,
107                             const MCInstrDesc &MCID) const;
108
109    void emitDataProcessingInstruction(const MachineInstr &MI,
110                                       unsigned ImplicitRd = 0,
111                                       unsigned ImplicitRn = 0);
112
113    void emitLoadStoreInstruction(const MachineInstr &MI,
114                                  unsigned ImplicitRd = 0,
115                                  unsigned ImplicitRn = 0);
116
117    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
118                                      unsigned ImplicitRn = 0);
119
120    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121
122    void emitMulFrmInstruction(const MachineInstr &MI);
123
124    void emitExtendInstruction(const MachineInstr &MI);
125
126    void emitMiscArithInstruction(const MachineInstr &MI);
127
128    void emitSaturateInstruction(const MachineInstr &MI);
129
130    void emitBranchInstruction(const MachineInstr &MI);
131
132    void emitInlineJumpTable(unsigned JTIndex);
133
134    void emitMiscBranchInstruction(const MachineInstr &MI);
135
136    void emitVFPArithInstruction(const MachineInstr &MI);
137
138    void emitVFPConversionInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141
142    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143
144    void emitMiscInstruction(const MachineInstr &MI);
145
146    void emitNEONLaneInstruction(const MachineInstr &MI);
147    void emitNEONDupInstruction(const MachineInstr &MI);
148    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
149    void emitNEON2RegInstruction(const MachineInstr &MI);
150    void emitNEON3RegInstruction(const MachineInstr &MI);
151
152    /// getMachineOpValue - Return binary encoding of operand. If the machine
153    /// operand requires relocation, record the relocation and return zero.
154    unsigned getMachineOpValue(const MachineInstr &MI,
155                               const MachineOperand &MO) const;
156    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157      return getMachineOpValue(MI, MI.getOperand(OpIdx));
158    }
159
160    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
161    //  TableGen'erated getBinaryCodeForInstr() function to encode any
162    //  operand values, instead querying getMachineOpValue() directly for
163    //  each operand it needs to encode. Thus, any of the new encoder
164    //  helper functions can simply return 0 as the values the return
165    //  are already handled elsewhere. They are placeholders to allow this
166    //  encoder to continue to function until the MC encoder is sufficiently
167    //  far along that this one can be eliminated entirely.
168    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
169      const { return 0; }
170    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
171      const { return 0; }
172    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
173      const { return 0; }
174    unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
175      const {
176      if (IsThumb) {
177        Val &= 0x0FFFFFFF;
178        Val |= 0xE0000000;
179      }
180      return Val;
181    }
182    unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
189      const { return 0; }
190    unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
195      const { return 0; }
196    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
197      const { return 0; }
198    unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
199      unsigned Op) const { return 0; }
200    unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
201      const { return 0; }
202    unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
203      const { return 0; }
204    unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
205      const { return 0; }
206    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
207      const { return 0; }
208    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
209      const { return 0; }
210    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
211      const { return 0; }
212    unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
213      const { return 0; }
214    unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
215      const { return 0; }
216    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
217      const { return 0; }
218    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
219      const { return 0; }
220    unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
221      const { return 0; }
222    unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
223      const { return 0; }
224    unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
225      const { return 0; }
226    unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
227      const { return 0; }
228    unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
229      const { return 0; }
230    unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
231      const { return 0; }
232    unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
233      const { return 0; }
234    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
235      const { return 0; }
236    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
237      const { return 0; }
238    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
239      const { return 0; }
240    unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
241                                                 unsigned Op)
242      const { return 0; }
243    unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
244      const { return 0; }
245    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
246      const { return 0; }
247    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
248                                            unsigned Op) const { return 0; }
249    unsigned getSsatBitPosValue(const MachineInstr &MI,
250                                unsigned Op) const { return 0; }
251    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
252      const {return 0; }
253    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
254      const { return 0; }
255
256    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
257      const {
258      // {17-13} = reg
259      // {12}    = (U)nsigned (add == '1', sub == '0')
260      // {11-0}  = imm12
261      const MachineOperand &MO  = MI.getOperand(Op);
262      const MachineOperand &MO1 = MI.getOperand(Op + 1);
263      if (!MO.isReg()) {
264        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
265        return 0;
266      }
267      unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
268      int32_t Imm12 = MO1.getImm();
269      uint32_t Binary;
270      Binary = Imm12 & 0xfff;
271      if (Imm12 >= 0)
272        Binary |= (1 << 12);
273      Binary |= (Reg << 13);
274      return Binary;
275    }
276
277    unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
278      const {
279      const MCInstrDesc &MCID = MI.getDesc();
280      const MachineOperand &MO = MI.getOperand(Op);
281
282      unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
283                       ARM::reloc_arm_movw : ARM::reloc_arm_movt);
284
285      if (!MO.isImm()) {
286        emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
287        return 0;
288      }
289      unsigned Imm16 = static_cast<unsigned>(MO.getImm());
290      return Imm16;
291    }
292
293    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
294      const { return 0;}
295    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
296      const { return 0;}
297    uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
298      const { return 0;}
299    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
300      const { return 0;}
301    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
302      const { return 0; }
303    uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
304      const { return 0; }
305    uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
306      const { return 0; }
307    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
308      const { return 0; }
309    uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
310      const { return 0; }
311    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
312      // {12-9}  = reg
313      // {8}     = (U)nsigned (add == '1', sub == '0')
314      // {7-0}   = imm8
315      uint32_t Binary = 0;
316      const MachineOperand &MO  = MI.getOperand(Op);
317      const MachineOperand &MO1 = MI.getOperand(Op + 1);
318      if (!MO.isReg()) {
319        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
320        return 0;
321      }
322      unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
323      int32_t Imm12 = MO1.getImm();
324
325      // Special value for #-0
326      if (Imm12 == INT32_MIN)
327        Imm12 = 0;
328
329      // Immediate is always encoded as positive. The 'U' bit controls add vs
330      // sub.
331      bool isAdd = true;
332      if (Imm12 < 0) {
333        Imm12 = -Imm12;
334        isAdd = false;
335      }
336
337      // If immediate offset is omitted, default to +0.
338      Binary |= 1 << 8;
339      return Binary;
340    }
341    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
342      const { return 0; }
343
344    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
345      const { return 0; }
346
347    unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
348      const { return 0; }
349    unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
350      const { return 0; }
351    unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
352      const { return 0; }
353    unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
354      const { return 0; }
355
356    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
357    /// machine operand requires relocation, record the relocation and return
358    /// zero.
359    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
360                            unsigned Reloc);
361
362    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
363    ///
364    unsigned getShiftOp(unsigned Imm) const ;
365
366    /// Routines that handle operands which add machine relocations which are
367    /// fixed up by the relocation stage.
368    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
369                           bool MayNeedFarStub,  bool Indirect,
370                           intptr_t ACPV = 0) const;
371    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
372    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
373    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
374    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
375                               intptr_t JTBase = 0) const;
376    unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
377    unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
378    unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
379    unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
380    unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
381    unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
382  };
383}
384
385char ARMCodeEmitter::ID = 0;
386
387/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
388/// code to the specified MCE object.
389FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
390                                                JITCodeEmitter &JCE) {
391  return new ARMCodeEmitter(TM, JCE);
392}
393
394bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
395  TargetMachine &Target = const_cast<TargetMachine&>(MF.getTarget());
396
397  assert((Target.getRelocationModel() != Reloc::Default ||
398          Target.getRelocationModel() != Reloc::Static) &&
399         "JIT relocation model must be set to static or default!");
400
401  JTI = static_cast<ARMJITInfo*>(Target.getJITInfo());
402  II = static_cast<const ARMBaseInstrInfo*>(Target.getInstrInfo());
403  TD = Target.getDataLayout();
404
405  Subtarget = &TM.getSubtarget<ARMSubtarget>();
406  MCPEs = &MF.getConstantPool()->getConstants();
407  MJTEs = 0;
408  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
409  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
410  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
411  JTI->Initialize(MF, IsPIC);
412  MMI = &getAnalysis<MachineModuleInfo>();
413  MCE.setModuleInfo(MMI);
414
415  do {
416    DEBUG(errs() << "JITTing function '"
417          << MF.getName() << "'\n");
418    MCE.startFunction(MF);
419    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
420         MBB != E; ++MBB) {
421      MCE.StartMachineBasicBlock(MBB);
422      for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
423           I != E; ++I)
424        emitInstruction(*I);
425    }
426  } while (MCE.finishFunction(MF));
427
428  return false;
429}
430
431/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
432///
433unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
434  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
435  default: llvm_unreachable("Unknown shift opc!");
436  case ARM_AM::asr: return 2;
437  case ARM_AM::lsl: return 0;
438  case ARM_AM::lsr: return 1;
439  case ARM_AM::ror:
440  case ARM_AM::rrx: return 3;
441  }
442}
443
444/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
445/// machine operand requires relocation, record the relocation and return zero.
446unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
447                                        const MachineOperand &MO,
448                                        unsigned Reloc) {
449  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
450      && "Relocation to this function should be for movt or movw");
451
452  if (MO.isImm())
453    return static_cast<unsigned>(MO.getImm());
454  else if (MO.isGlobal())
455    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
456  else if (MO.isSymbol())
457    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
458  else if (MO.isMBB())
459    emitMachineBasicBlock(MO.getMBB(), Reloc);
460  else {
461#ifndef NDEBUG
462    errs() << MO;
463#endif
464    llvm_unreachable("Unsupported operand type for movw/movt");
465  }
466  return 0;
467}
468
469/// getMachineOpValue - Return binary encoding of operand. If the machine
470/// operand requires relocation, record the relocation and return zero.
471unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
472                                           const MachineOperand &MO) const {
473  if (MO.isReg())
474    return II->getRegisterInfo().getEncodingValue(MO.getReg());
475  else if (MO.isImm())
476    return static_cast<unsigned>(MO.getImm());
477  else if (MO.isFPImm())
478    return static_cast<unsigned>(MO.getFPImm()->getValueAPF()
479                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
480  else if (MO.isGlobal())
481    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
482  else if (MO.isSymbol())
483    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
484  else if (MO.isCPI()) {
485    const MCInstrDesc &MCID = MI.getDesc();
486    // For VFP load, the immediate offset is multiplied by 4.
487    unsigned Reloc =  ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
488      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
489    emitConstPoolAddress(MO.getIndex(), Reloc);
490  } else if (MO.isJTI())
491    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
492  else if (MO.isMBB())
493    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
494  else
495    llvm_unreachable("Unable to encode MachineOperand!");
496  return 0;
497}
498
499/// emitGlobalAddress - Emit the specified address to the code stream.
500///
501void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
502                                       bool MayNeedFarStub, bool Indirect,
503                                       intptr_t ACPV) const {
504  MachineRelocation MR = Indirect
505    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
506                                           const_cast<GlobalValue *>(GV),
507                                           ACPV, MayNeedFarStub)
508    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
509                               const_cast<GlobalValue *>(GV), ACPV,
510                               MayNeedFarStub);
511  MCE.addRelocation(MR);
512}
513
514/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
515/// be emitted to the current location in the function, and allow it to be PC
516/// relative.
517void ARMCodeEmitter::
518emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
519  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
520                                                 Reloc, ES));
521}
522
523/// emitConstPoolAddress - Arrange for the address of an constant pool
524/// to be emitted to the current location in the function, and allow it to be PC
525/// relative.
526void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
527  // Tell JIT emitter we'll resolve the address.
528  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
529                                                    Reloc, CPI, 0, true));
530}
531
532/// emitJumpTableAddress - Arrange for the address of a jump table to
533/// be emitted to the current location in the function, and allow it to be PC
534/// relative.
535void ARMCodeEmitter::
536emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
537  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
538                                                    Reloc, JTIndex, 0, true));
539}
540
541/// emitMachineBasicBlock - Emit the specified address basic block.
542void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
543                                           unsigned Reloc,
544                                           intptr_t JTBase) const {
545  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
546                                             Reloc, BB, JTBase));
547}
548
549void ARMCodeEmitter::emitWordLE(unsigned Binary) {
550  DEBUG(errs() << "  0x";
551        errs().write_hex(Binary) << "\n");
552  MCE.emitWordLE(Binary);
553}
554
555void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
556  DEBUG(errs() << "  0x";
557        errs().write_hex(Binary) << "\n");
558  MCE.emitDWordLE(Binary);
559}
560
561void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
562  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
563
564  MCE.processDebugLoc(MI.getDebugLoc(), true);
565
566  ++NumEmitted;  // Keep track of the # of mi's emitted
567  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
568  default: {
569    llvm_unreachable("Unhandled instruction encoding format!");
570  }
571  case ARMII::MiscFrm:
572    if (MI.getOpcode() == ARM::LEApcrelJT) {
573      // Materialize jumptable address.
574      emitLEApcrelJTInstruction(MI);
575      break;
576    }
577    llvm_unreachable("Unhandled instruction encoding!");
578  case ARMII::Pseudo:
579    emitPseudoInstruction(MI);
580    break;
581  case ARMII::DPFrm:
582  case ARMII::DPSoRegFrm:
583    emitDataProcessingInstruction(MI);
584    break;
585  case ARMII::LdFrm:
586  case ARMII::StFrm:
587    emitLoadStoreInstruction(MI);
588    break;
589  case ARMII::LdMiscFrm:
590  case ARMII::StMiscFrm:
591    emitMiscLoadStoreInstruction(MI);
592    break;
593  case ARMII::LdStMulFrm:
594    emitLoadStoreMultipleInstruction(MI);
595    break;
596  case ARMII::MulFrm:
597    emitMulFrmInstruction(MI);
598    break;
599  case ARMII::ExtFrm:
600    emitExtendInstruction(MI);
601    break;
602  case ARMII::ArithMiscFrm:
603    emitMiscArithInstruction(MI);
604    break;
605  case ARMII::SatFrm:
606    emitSaturateInstruction(MI);
607    break;
608  case ARMII::BrFrm:
609    emitBranchInstruction(MI);
610    break;
611  case ARMII::BrMiscFrm:
612    emitMiscBranchInstruction(MI);
613    break;
614  // VFP instructions.
615  case ARMII::VFPUnaryFrm:
616  case ARMII::VFPBinaryFrm:
617    emitVFPArithInstruction(MI);
618    break;
619  case ARMII::VFPConv1Frm:
620  case ARMII::VFPConv2Frm:
621  case ARMII::VFPConv3Frm:
622  case ARMII::VFPConv4Frm:
623  case ARMII::VFPConv5Frm:
624    emitVFPConversionInstruction(MI);
625    break;
626  case ARMII::VFPLdStFrm:
627    emitVFPLoadStoreInstruction(MI);
628    break;
629  case ARMII::VFPLdStMulFrm:
630    emitVFPLoadStoreMultipleInstruction(MI);
631    break;
632  case ARMII::VFPMiscFrm:
633    emitMiscInstruction(MI);
634    break;
635  // NEON instructions.
636  case ARMII::NGetLnFrm:
637  case ARMII::NSetLnFrm:
638    emitNEONLaneInstruction(MI);
639    break;
640  case ARMII::NDupFrm:
641    emitNEONDupInstruction(MI);
642    break;
643  case ARMII::N1RegModImmFrm:
644    emitNEON1RegModImmInstruction(MI);
645    break;
646  case ARMII::N2RegFrm:
647    emitNEON2RegInstruction(MI);
648    break;
649  case ARMII::N3RegFrm:
650    emitNEON3RegInstruction(MI);
651    break;
652  }
653  MCE.processDebugLoc(MI.getDebugLoc(), false);
654}
655
656void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) {
657  DEBUG({
658      errs() << "  ** Constant pool #" << CPI << " @ "
659             << (void*)MCE.getCurrentPCValue() << " ";
660      if (const Function *F = dyn_cast<Function>(C))
661        errs() << F->getName();
662      else
663        errs() << *C;
664      errs() << '\n';
665    });
666
667  switch (C->getValueID()) {
668  default: {
669    llvm_unreachable("Unable to handle this constantpool entry!");
670    break;
671  }
672  case Value::GlobalVariableVal: {
673    emitGlobalAddress(static_cast<const GlobalValue*>(C),
674                      ARM::reloc_arm_absolute, isa<Function>(C), false);
675    emitWordLE(0);
676    break;
677  }
678  case Value::ConstantIntVal: {
679    const ConstantInt *CI = static_cast<const ConstantInt*>(C);
680    uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
681    emitWordLE(Val);
682    break;
683  }
684  case Value::ConstantFPVal: {
685    const ConstantFP *CFP = static_cast<const ConstantFP*>(C);
686    if (CFP->getType()->isFloatTy())
687      emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
688    else if (CFP->getType()->isDoubleTy())
689      emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
690    else {
691      llvm_unreachable("Unable to handle this constantpool entry!");
692    }
693    break;
694  }
695  case Value::ConstantArrayVal: {
696    const ConstantArray *CA = static_cast<const ConstantArray*>(C);
697    for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
698      emitConstantToMemory(CPI, CA->getOperand(i));
699    break;
700  }
701  }
702
703  return;
704}
705
706void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
707  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
708  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
709  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
710
711  // Remember the CONSTPOOL_ENTRY address for later relocation.
712  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
713
714  // Emit constpool island entry. In most cases, the actual values will be
715  // resolved and relocated after code emission.
716  if (MCPE.isMachineConstantPoolEntry()) {
717    ARMConstantPoolValue *ACPV =
718      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
719
720    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
721          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
722
723    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
724    const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
725    if (GV) {
726      Reloc::Model RelocM = TM.getRelocationModel();
727      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
728                        isa<Function>(GV),
729                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
730                        (intptr_t)ACPV);
731    } else  {
732      const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
733      emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
734    }
735    emitWordLE(0);
736  } else {
737    emitConstantToMemory(CPI, MCPE.Val.ConstVal);
738  }
739}
740
741void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
742  const MachineOperand &MO0 = MI.getOperand(0);
743  const MachineOperand &MO1 = MI.getOperand(1);
744
745  // Emit the 'movw' instruction.
746  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
747
748  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
749
750  // Set the conditional execution predicate.
751  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
752
753  // Encode Rd.
754  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
755
756  // Encode imm16 as imm4:imm12
757  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
758  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
759  emitWordLE(Binary);
760
761  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
762  // Emit the 'movt' instruction.
763  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
764
765  // Set the conditional execution predicate.
766  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
767
768  // Encode Rd.
769  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
770
771  // Encode imm16 as imm4:imm1, same as movw above.
772  Binary |= Hi16 & 0xFFF;
773  Binary |= ((Hi16 >> 12) & 0xF) << 16;
774  emitWordLE(Binary);
775}
776
777void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
778  const MachineOperand &MO0 = MI.getOperand(0);
779  const MachineOperand &MO1 = MI.getOperand(1);
780  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
781                                                  "Not a valid so_imm value!");
782  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
783  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
784
785  // Emit the 'mov' instruction.
786  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
787
788  // Set the conditional execution predicate.
789  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
790
791  // Encode Rd.
792  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
793
794  // Encode so_imm.
795  // Set bit I(25) to identify this is the immediate form of <shifter_op>
796  Binary |= 1 << ARMII::I_BitShift;
797  Binary |= getMachineSoImmOpValue(V1);
798  emitWordLE(Binary);
799
800  // Now the 'orr' instruction.
801  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
802
803  // Set the conditional execution predicate.
804  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
805
806  // Encode Rd.
807  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
808
809  // Encode Rn.
810  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
811
812  // Encode so_imm.
813  // Set bit I(25) to identify this is the immediate form of <shifter_op>
814  Binary |= 1 << ARMII::I_BitShift;
815  Binary |= getMachineSoImmOpValue(V2);
816  emitWordLE(Binary);
817}
818
819void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
820  // It's basically add r, pc, (LCPI - $+8)
821  const MCInstrDesc &MCID = MI.getDesc();
822
823  unsigned Binary = 0;
824
825  // Set the conditional execution predicate
826  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
827
828  // Encode S bit if MI modifies CPSR.
829  Binary |= getAddrModeSBit(MI, MCID);
830
831  // Encode Rd.
832  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
833
834  // Encode Rn which is PC.
835  Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
836
837  // Encode the displacement which is a so_imm.
838  // Set bit I(25) to identify this is the immediate form of <shifter_op>
839  Binary |= 1 << ARMII::I_BitShift;
840  emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry);
841
842  emitWordLE(Binary);
843}
844
845void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
846  // It's basically add r, pc, (LJTI - $+8)
847
848  const MCInstrDesc &MCID = MI.getDesc();
849
850  // Emit the 'add' instruction.
851  unsigned Binary = 0x4 << 21;  // add: Insts{24-21} = 0b0100
852
853  // Set the conditional execution predicate
854  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
855
856  // Encode S bit if MI modifies CPSR.
857  Binary |= getAddrModeSBit(MI, MCID);
858
859  // Encode Rd.
860  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
861
862  // Encode Rn which is PC.
863  Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
864
865  // Encode the displacement.
866  Binary |= 1 << ARMII::I_BitShift;
867  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
868
869  emitWordLE(Binary);
870}
871
872void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
873  unsigned Opcode = MI.getDesc().Opcode;
874
875  // Part of binary is determined by TableGn.
876  unsigned Binary = getBinaryCodeForInstr(MI);
877
878  // Set the conditional execution predicate
879  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
880
881  // Encode S bit if MI modifies CPSR.
882  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
883    Binary |= 1 << ARMII::S_BitShift;
884
885  // Encode register def if there is one.
886  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
887
888  // Encode the shift operation.
889  switch (Opcode) {
890  default: break;
891  case ARM::RRX:
892    // rrx
893    Binary |= 0x6 << 4;
894    break;
895  case ARM::MOVsrl_flag:
896    // lsr #1
897    Binary |= (0x2 << 4) | (1 << 7);
898    break;
899  case ARM::MOVsra_flag:
900    // asr #1
901    Binary |= (0x4 << 4) | (1 << 7);
902    break;
903  }
904
905  // Encode register Rm.
906  Binary |= getMachineOpValue(MI, 1);
907
908  emitWordLE(Binary);
909}
910
911void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
912  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
913        << (void*)MCE.getCurrentPCValue() << '\n');
914  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
915}
916
917void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
918  unsigned Opcode = MI.getDesc().Opcode;
919  switch (Opcode) {
920  default:
921    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
922  case ARM::B:
923    emitBranchInstruction(MI);
924    break;
925  case ARM::BR_JTr:
926  case ARM::BR_JTm:
927  case ARM::BR_JTadd:
928    emitMiscBranchInstruction(MI);
929    break;
930  case ARM::BX_CALL:
931  case ARM::BMOVPCRX_CALL: {
932    // First emit mov lr, pc
933    unsigned Binary = 0x01a0e00f;
934    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
935    emitWordLE(Binary);
936
937    // and then emit the branch.
938    emitMiscBranchInstruction(MI);
939    break;
940  }
941  case TargetOpcode::INLINEASM: {
942    // We allow inline assembler nodes with empty bodies - they can
943    // implicitly define registers, which is ok for JIT.
944    if (MI.getOperand(0).getSymbolName()[0]) {
945      report_fatal_error("JIT does not support inline asm!");
946    }
947    break;
948  }
949  case TargetOpcode::PROLOG_LABEL:
950  case TargetOpcode::EH_LABEL:
951    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
952    break;
953  case TargetOpcode::IMPLICIT_DEF:
954  case TargetOpcode::KILL:
955    // Do nothing.
956    break;
957  case ARM::CONSTPOOL_ENTRY:
958    emitConstPoolInstruction(MI);
959    break;
960  case ARM::LDMIA_RET:
961    emitLoadStoreMultipleInstruction(MI);
962    break;
963  case ARM::PICADD: {
964    // Remember of the address of the PC label for relocation later.
965    addPCLabel(MI.getOperand(2).getImm());
966    // PICADD is just an add instruction that implicitly read pc.
967    emitDataProcessingInstruction(MI, 0, ARM::PC);
968    break;
969  }
970  case ARM::PICLDR:
971  case ARM::PICLDRB:
972  case ARM::PICSTR:
973  case ARM::PICSTRB: {
974    // Remember of the address of the PC label for relocation later.
975    addPCLabel(MI.getOperand(2).getImm());
976    // These are just load / store instructions that implicitly read pc.
977    emitLoadStoreInstruction(MI, 0, ARM::PC);
978    break;
979  }
980  case ARM::PICLDRH:
981  case ARM::PICLDRSH:
982  case ARM::PICLDRSB:
983  case ARM::PICSTRH: {
984    // Remember of the address of the PC label for relocation later.
985    addPCLabel(MI.getOperand(2).getImm());
986    // These are just load / store instructions that implicitly read pc.
987    emitMiscLoadStoreInstruction(MI, ARM::PC);
988    break;
989  }
990
991  case ARM::MOVi32imm:
992    // Two instructions to materialize a constant.
993    if (Subtarget->hasV6T2Ops())
994      emitMOVi32immInstruction(MI);
995    else
996      emitMOVi2piecesInstruction(MI);
997    break;
998  case ARM::LEApcrel:
999    // Materialize constantpool index address.
1000    emitLEApcrelInstruction(MI);
1001    break;
1002  case ARM::LEApcrelJT:
1003    // Materialize jumptable address.
1004    emitLEApcrelJTInstruction(MI);
1005    break;
1006  case ARM::RRX:
1007  case ARM::MOVsrl_flag:
1008  case ARM::MOVsra_flag:
1009    emitPseudoMoveInstruction(MI);
1010    break;
1011  }
1012}
1013
1014unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
1015                                                const MCInstrDesc &MCID,
1016                                                const MachineOperand &MO,
1017                                                unsigned OpIdx) {
1018  unsigned Binary = getMachineOpValue(MI, MO);
1019
1020  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
1021  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1022  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1023
1024  // Encode the shift opcode.
1025  unsigned SBits = 0;
1026  unsigned Rs = MO1.getReg();
1027  if (Rs) {
1028    // Set shift operand (bit[7:4]).
1029    // LSL - 0001
1030    // LSR - 0011
1031    // ASR - 0101
1032    // ROR - 0111
1033    // RRX - 0110 and bit[11:8] clear.
1034    switch (SOpc) {
1035    default: llvm_unreachable("Unknown shift opc!");
1036    case ARM_AM::lsl: SBits = 0x1; break;
1037    case ARM_AM::lsr: SBits = 0x3; break;
1038    case ARM_AM::asr: SBits = 0x5; break;
1039    case ARM_AM::ror: SBits = 0x7; break;
1040    case ARM_AM::rrx: SBits = 0x6; break;
1041    }
1042  } else {
1043    // Set shift operand (bit[6:4]).
1044    // LSL - 000
1045    // LSR - 010
1046    // ASR - 100
1047    // ROR - 110
1048    switch (SOpc) {
1049    default: llvm_unreachable("Unknown shift opc!");
1050    case ARM_AM::lsl: SBits = 0x0; break;
1051    case ARM_AM::lsr: SBits = 0x2; break;
1052    case ARM_AM::asr: SBits = 0x4; break;
1053    case ARM_AM::ror: SBits = 0x6; break;
1054    }
1055  }
1056  Binary |= SBits << 4;
1057  if (SOpc == ARM_AM::rrx)
1058    return Binary;
1059
1060  // Encode the shift operation Rs or shift_imm (except rrx).
1061  if (Rs) {
1062    // Encode Rs bit[11:8].
1063    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1064    return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
1065  }
1066
1067  // Encode shift_imm bit[11:7].
1068  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
1069}
1070
1071unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
1072  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
1073  assert(SoImmVal != -1 && "Not a valid so_imm value!");
1074
1075  // Encode rotate_imm.
1076  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
1077    << ARMII::SoRotImmShift;
1078
1079  // Encode immed_8.
1080  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
1081  return Binary;
1082}
1083
1084unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
1085                                         const MCInstrDesc &MCID) const {
1086  for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
1087    const MachineOperand &MO = MI.getOperand(i-1);
1088    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1089      return 1 << ARMII::S_BitShift;
1090  }
1091  return 0;
1092}
1093
1094void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1095                                                   unsigned ImplicitRd,
1096                                                   unsigned ImplicitRn) {
1097  const MCInstrDesc &MCID = MI.getDesc();
1098
1099  // Part of binary is determined by TableGn.
1100  unsigned Binary = getBinaryCodeForInstr(MI);
1101
1102  if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
1103      emitWordLE(Binary);
1104      return;
1105  }
1106
1107  // Set the conditional execution predicate
1108  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1109
1110  // Encode S bit if MI modifies CPSR.
1111  Binary |= getAddrModeSBit(MI, MCID);
1112
1113  // Encode register def if there is one.
1114  unsigned NumDefs = MCID.getNumDefs();
1115  unsigned OpIdx = 0;
1116  if (NumDefs)
1117    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1118  else if (ImplicitRd)
1119    // Special handling for implicit use (e.g. PC).
1120    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1121
1122  if (MCID.Opcode == ARM::MOVi16) {
1123      // Get immediate from MI.
1124      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1125                      ARM::reloc_arm_movw);
1126      // Encode imm which is the same as in emitMOVi32immInstruction().
1127      Binary |= Lo16 & 0xFFF;
1128      Binary |= ((Lo16 >> 12) & 0xF) << 16;
1129      emitWordLE(Binary);
1130      return;
1131  } else if(MCID.Opcode == ARM::MOVTi16) {
1132      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1133                       ARM::reloc_arm_movt) >> 16);
1134      Binary |= Hi16 & 0xFFF;
1135      Binary |= ((Hi16 >> 12) & 0xF) << 16;
1136      emitWordLE(Binary);
1137      return;
1138  } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1139      uint32_t v = ~MI.getOperand(2).getImm();
1140      int32_t lsb = CountTrailingZeros_32(v);
1141      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1142      // Instr{20-16} = msb, Instr{11-7} = lsb
1143      Binary |= (msb & 0x1F) << 16;
1144      Binary |= (lsb & 0x1F) << 7;
1145      emitWordLE(Binary);
1146      return;
1147  } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1148      // Encode Rn in Instr{0-3}
1149      Binary |= getMachineOpValue(MI, OpIdx++);
1150
1151      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1152      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1153
1154      // Instr{20-16} = widthm1, Instr{11-7} = lsb
1155      Binary |= (widthm1 & 0x1F) << 16;
1156      Binary |= (lsb & 0x1F) << 7;
1157      emitWordLE(Binary);
1158      return;
1159  }
1160
1161  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1162  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1163    ++OpIdx;
1164
1165  // Encode first non-shifter register operand if there is one.
1166  bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1167  if (!isUnary) {
1168    if (ImplicitRn)
1169      // Special handling for implicit use (e.g. PC).
1170      Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1171    else {
1172      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1173      ++OpIdx;
1174    }
1175  }
1176
1177  // Encode shifter operand.
1178  const MachineOperand &MO = MI.getOperand(OpIdx);
1179  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1180    // Encode SoReg.
1181    emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1182    return;
1183  }
1184
1185  if (MO.isReg()) {
1186    // Encode register Rm.
1187    emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg()));
1188    return;
1189  }
1190
1191  // Encode so_imm.
1192  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1193
1194  emitWordLE(Binary);
1195}
1196
1197void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1198                                              unsigned ImplicitRd,
1199                                              unsigned ImplicitRn) {
1200  const MCInstrDesc &MCID = MI.getDesc();
1201  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1202  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1203
1204  // Part of binary is determined by TableGn.
1205  unsigned Binary = getBinaryCodeForInstr(MI);
1206
1207  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1208  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1209      MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 ||
1210      MI.getOpcode() == ARM::STRBi12) {
1211    emitWordLE(Binary);
1212    return;
1213  }
1214
1215  if (MI.getOpcode() == ARM::BR_JTm)
1216    Binary = 0x710F000;
1217  else if (MI.getOpcode() == ARM::BR_JTr)
1218    Binary = 0x1A0F000;
1219
1220  // Set the conditional execution predicate
1221  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1222
1223  unsigned OpIdx = 0;
1224
1225  // Operand 0 of a pre- and post-indexed store is the address base
1226  // writeback. Skip it.
1227  bool Skipped = false;
1228  if (IsPrePost && Form == ARMII::StFrm) {
1229    ++OpIdx;
1230    Skipped = true;
1231  }
1232
1233  // Set first operand
1234  if (ImplicitRd)
1235    // Special handling for implicit use (e.g. PC).
1236    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1237  else
1238    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1239
1240  // Set second operand
1241  if (ImplicitRn)
1242    // Special handling for implicit use (e.g. PC).
1243    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1244  else
1245    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1246
1247  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1248  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1249    ++OpIdx;
1250
1251  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1252  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1253    ? 0 : MI.getOperand(OpIdx+1).getImm();
1254
1255  // Set bit U(23) according to sign of immed value (positive or negative).
1256  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1257             ARMII::U_BitShift);
1258  if (!MO2.getReg()) { // is immediate
1259    if (ARM_AM::getAM2Offset(AM2Opc))
1260      // Set the value of offset_12 field
1261      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1262    emitWordLE(Binary);
1263    return;
1264  }
1265
1266  // Set bit I(25), because this is not in immediate encoding.
1267  Binary |= 1 << ARMII::I_BitShift;
1268  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1269  // Set bit[3:0] to the corresponding Rm register
1270  Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1271
1272  // If this instr is in scaled register offset/index instruction, set
1273  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1274  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1275    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1276    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1277  }
1278
1279  emitWordLE(Binary);
1280}
1281
1282void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1283                                                  unsigned ImplicitRn) {
1284  const MCInstrDesc &MCID = MI.getDesc();
1285  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1286  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1287
1288  // Part of binary is determined by TableGn.
1289  unsigned Binary = getBinaryCodeForInstr(MI);
1290
1291  // Set the conditional execution predicate
1292  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1293
1294  unsigned OpIdx = 0;
1295
1296  // Operand 0 of a pre- and post-indexed store is the address base
1297  // writeback. Skip it.
1298  bool Skipped = false;
1299  if (IsPrePost && Form == ARMII::StMiscFrm) {
1300    ++OpIdx;
1301    Skipped = true;
1302  }
1303
1304  // Set first operand
1305  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1306
1307  // Skip LDRD and STRD's second operand.
1308  if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1309    ++OpIdx;
1310
1311  // Set second operand
1312  if (ImplicitRn)
1313    // Special handling for implicit use (e.g. PC).
1314    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1315  else
1316    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1317
1318  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1319  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1320    ++OpIdx;
1321
1322  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1323  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1324    ? 0 : MI.getOperand(OpIdx+1).getImm();
1325
1326  // Set bit U(23) according to sign of immed value (positive or negative)
1327  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1328             ARMII::U_BitShift);
1329
1330  // If this instr is in register offset/index encoding, set bit[3:0]
1331  // to the corresponding Rm register.
1332  if (MO2.getReg()) {
1333    Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1334    emitWordLE(Binary);
1335    return;
1336  }
1337
1338  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1339  Binary |= 1 << ARMII::AM3_I_BitShift;
1340  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1341    // Set operands
1342    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1343    Binary |= (ImmOffs & 0xF);                      // immedL
1344  }
1345
1346  emitWordLE(Binary);
1347}
1348
1349static unsigned getAddrModeUPBits(unsigned Mode) {
1350  unsigned Binary = 0;
1351
1352  // Set addressing mode by modifying bits U(23) and P(24)
1353  // IA - Increment after  - bit U = 1 and bit P = 0
1354  // IB - Increment before - bit U = 1 and bit P = 1
1355  // DA - Decrement after  - bit U = 0 and bit P = 0
1356  // DB - Decrement before - bit U = 0 and bit P = 1
1357  switch (Mode) {
1358  default: llvm_unreachable("Unknown addressing sub-mode!");
1359  case ARM_AM::da:                                     break;
1360  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1361  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1362  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1363  }
1364
1365  return Binary;
1366}
1367
1368void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1369  const MCInstrDesc &MCID = MI.getDesc();
1370  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1371
1372  // Part of binary is determined by TableGn.
1373  unsigned Binary = getBinaryCodeForInstr(MI);
1374
1375  if (MCID.getOpcode() == ARM::LDMIA_RET) {
1376    IsUpdating = true;
1377    Binary |= 0x8B00000;
1378  }
1379
1380  // Set the conditional execution predicate
1381  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1382
1383  // Skip operand 0 of an instruction with base register update.
1384  unsigned OpIdx = 0;
1385  if (IsUpdating)
1386    ++OpIdx;
1387
1388  // Set base address operand
1389  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1390
1391  // Set addressing mode by modifying bits U(23) and P(24)
1392  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1393  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1394
1395  // Set bit W(21)
1396  if (IsUpdating)
1397    Binary |= 0x1 << ARMII::W_BitShift;
1398
1399  // Set registers
1400  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1401    const MachineOperand &MO = MI.getOperand(i);
1402    if (!MO.isReg() || MO.isImplicit())
1403      break;
1404    unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg());
1405    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1406           RegNum < 16);
1407    Binary |= 0x1 << RegNum;
1408  }
1409
1410  emitWordLE(Binary);
1411}
1412
1413void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1414  const MCInstrDesc &MCID = MI.getDesc();
1415
1416  // Part of binary is determined by TableGn.
1417  unsigned Binary = getBinaryCodeForInstr(MI);
1418
1419  // Set the conditional execution predicate
1420  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1421
1422  // Encode S bit if MI modifies CPSR.
1423  Binary |= getAddrModeSBit(MI, MCID);
1424
1425  // 32x32->64bit operations have two destination registers. The number
1426  // of register definitions will tell us if that's what we're dealing with.
1427  unsigned OpIdx = 0;
1428  if (MCID.getNumDefs() == 2)
1429    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1430
1431  // Encode Rd
1432  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1433
1434  // Encode Rm
1435  Binary |= getMachineOpValue(MI, OpIdx++);
1436
1437  // Encode Rs
1438  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1439
1440  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1441  // it as Rn (for multiply, that's in the same offset as RdLo.
1442  if (MCID.getNumOperands() > OpIdx &&
1443      !MCID.OpInfo[OpIdx].isPredicate() &&
1444      !MCID.OpInfo[OpIdx].isOptionalDef())
1445    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1446
1447  emitWordLE(Binary);
1448}
1449
1450void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1451  const MCInstrDesc &MCID = MI.getDesc();
1452
1453  // Part of binary is determined by TableGn.
1454  unsigned Binary = getBinaryCodeForInstr(MI);
1455
1456  // Set the conditional execution predicate
1457  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1458
1459  unsigned OpIdx = 0;
1460
1461  // Encode Rd
1462  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1463
1464  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1465  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1466  if (MO2.isReg()) {
1467    // Two register operand form.
1468    // Encode Rn.
1469    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1470
1471    // Encode Rm.
1472    Binary |= getMachineOpValue(MI, MO2);
1473    ++OpIdx;
1474  } else {
1475    Binary |= getMachineOpValue(MI, MO1);
1476  }
1477
1478  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1479  if (MI.getOperand(OpIdx).isImm() &&
1480      !MCID.OpInfo[OpIdx].isPredicate() &&
1481      !MCID.OpInfo[OpIdx].isOptionalDef())
1482    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1483
1484  emitWordLE(Binary);
1485}
1486
1487void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1488  const MCInstrDesc &MCID = MI.getDesc();
1489
1490  // Part of binary is determined by TableGn.
1491  unsigned Binary = getBinaryCodeForInstr(MI);
1492
1493  // Set the conditional execution predicate
1494  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1495
1496  // PKH instructions are finished at this point
1497  if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1498    emitWordLE(Binary);
1499    return;
1500  }
1501
1502  unsigned OpIdx = 0;
1503
1504  // Encode Rd
1505  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1506
1507  const MachineOperand &MO = MI.getOperand(OpIdx++);
1508  if (OpIdx == MCID.getNumOperands() ||
1509      MCID.OpInfo[OpIdx].isPredicate() ||
1510      MCID.OpInfo[OpIdx].isOptionalDef()) {
1511    // Encode Rm and it's done.
1512    Binary |= getMachineOpValue(MI, MO);
1513    emitWordLE(Binary);
1514    return;
1515  }
1516
1517  // Encode Rn.
1518  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1519
1520  // Encode Rm.
1521  Binary |= getMachineOpValue(MI, OpIdx++);
1522
1523  // Encode shift_imm.
1524  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1525  if (MCID.Opcode == ARM::PKHTB) {
1526    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1527    if (ShiftAmt == 32)
1528      ShiftAmt = 0;
1529  }
1530  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1531  Binary |= ShiftAmt << ARMII::ShiftShift;
1532
1533  emitWordLE(Binary);
1534}
1535
1536void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1537  const MCInstrDesc &MCID = MI.getDesc();
1538
1539  // Part of binary is determined by TableGen.
1540  unsigned Binary = getBinaryCodeForInstr(MI);
1541
1542  // Set the conditional execution predicate
1543  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1544
1545  // Encode Rd
1546  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1547
1548  // Encode saturate bit position.
1549  unsigned Pos = MI.getOperand(1).getImm();
1550  if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1551    Pos -= 1;
1552  assert((Pos < 16 || (Pos < 32 &&
1553                       MCID.Opcode != ARM::SSAT16 &&
1554                       MCID.Opcode != ARM::USAT16)) &&
1555         "saturate bit position out of range");
1556  Binary |= Pos << 16;
1557
1558  // Encode Rm
1559  Binary |= getMachineOpValue(MI, 2);
1560
1561  // Encode shift_imm.
1562  if (MCID.getNumOperands() == 4) {
1563    unsigned ShiftOp = MI.getOperand(3).getImm();
1564    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1565    if (Opc == ARM_AM::asr)
1566      Binary |= (1 << 6);
1567    unsigned ShiftAmt = MI.getOperand(3).getImm();
1568    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1569      ShiftAmt = 0;
1570    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1571    Binary |= ShiftAmt << ARMII::ShiftShift;
1572  }
1573
1574  emitWordLE(Binary);
1575}
1576
1577void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1578  const MCInstrDesc &MCID = MI.getDesc();
1579
1580  if (MCID.Opcode == ARM::TPsoft) {
1581    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1582  }
1583
1584  // Part of binary is determined by TableGn.
1585  unsigned Binary = getBinaryCodeForInstr(MI);
1586
1587  if (MCID.Opcode == ARM::B) {
1588    Binary = 0xEA000000;
1589  }
1590
1591  // Set the conditional execution predicate
1592  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1593
1594  // Set signed_immed_24 field
1595  Binary |= getMachineOpValue(MI, 0);
1596
1597  emitWordLE(Binary);
1598}
1599
1600void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1601  // Remember the base address of the inline jump table.
1602  uintptr_t JTBase = MCE.getCurrentPCValue();
1603  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1604  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1605               << '\n');
1606
1607  // Now emit the jump table entries.
1608  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1609  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1610    if (IsPIC)
1611      // DestBB address - JT base.
1612      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1613    else
1614      // Absolute DestBB address.
1615      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1616    emitWordLE(0);
1617  }
1618}
1619
1620void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1621  const MCInstrDesc &MCID = MI.getDesc();
1622
1623  // Handle jump tables.
1624  if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1625    // First emit a ldr pc, [] instruction.
1626    emitDataProcessingInstruction(MI, ARM::PC);
1627
1628    // Then emit the inline jump table.
1629    unsigned JTIndex =
1630      (MCID.Opcode == ARM::BR_JTr)
1631      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1632    emitInlineJumpTable(JTIndex);
1633    return;
1634  } else if (MCID.Opcode == ARM::BR_JTm) {
1635    // First emit a ldr pc, [] instruction.
1636    emitLoadStoreInstruction(MI, ARM::PC);
1637
1638    // Then emit the inline jump table.
1639    emitInlineJumpTable(MI.getOperand(3).getIndex());
1640    return;
1641  }
1642
1643  // Part of binary is determined by TableGn.
1644  unsigned Binary = getBinaryCodeForInstr(MI);
1645
1646  // Set the conditional execution predicate
1647  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1648
1649  if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1650    // The return register is LR.
1651    Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR);
1652  else
1653    // otherwise, set the return register
1654    Binary |= getMachineOpValue(MI, 0);
1655
1656  emitWordLE(Binary);
1657}
1658
1659unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
1660                                     unsigned OpIdx) const {
1661  unsigned RegD = MI.getOperand(OpIdx).getReg();
1662  unsigned Binary = 0;
1663  bool isSPVFP = ARM::SPRRegClass.contains(RegD);
1664  RegD = II->getRegisterInfo().getEncodingValue(RegD);
1665  if (!isSPVFP) {
1666    Binary |=  (RegD & 0x0F)       << ARMII::RegRdShift;
1667    Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift;
1668  } else {
1669    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1670    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1671  }
1672  return Binary;
1673}
1674
1675unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
1676                                     unsigned OpIdx) const {
1677  unsigned RegN = MI.getOperand(OpIdx).getReg();
1678  unsigned Binary = 0;
1679  bool isSPVFP = ARM::SPRRegClass.contains(RegN);
1680  RegN = II->getRegisterInfo().getEncodingValue(RegN);
1681  if (!isSPVFP) {
1682    Binary |=  (RegN & 0x0F)       << ARMII::RegRnShift;
1683    Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift;
1684  } else {
1685    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1686    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1687  }
1688  return Binary;
1689}
1690
1691unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
1692                                     unsigned OpIdx) const {
1693  unsigned RegM = MI.getOperand(OpIdx).getReg();
1694  unsigned Binary = 0;
1695  bool isSPVFP = ARM::SPRRegClass.contains(RegM);
1696  RegM = II->getRegisterInfo().getEncodingValue(RegM);
1697  if (!isSPVFP) {
1698    Binary |=  (RegM & 0x0F);
1699    Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift;
1700  } else {
1701    Binary |= ((RegM & 0x1E) >> 1);
1702    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1703  }
1704  return Binary;
1705}
1706
1707void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1708  const MCInstrDesc &MCID = MI.getDesc();
1709
1710  // Part of binary is determined by TableGn.
1711  unsigned Binary = getBinaryCodeForInstr(MI);
1712
1713  // Set the conditional execution predicate
1714  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1715
1716  unsigned OpIdx = 0;
1717
1718  // Encode Dd / Sd.
1719  Binary |= encodeVFPRd(MI, OpIdx++);
1720
1721  // If this is a two-address operand, skip it, e.g. FMACD.
1722  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1723    ++OpIdx;
1724
1725  // Encode Dn / Sn.
1726  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1727    Binary |= encodeVFPRn(MI, OpIdx++);
1728
1729  if (OpIdx == MCID.getNumOperands() ||
1730      MCID.OpInfo[OpIdx].isPredicate() ||
1731      MCID.OpInfo[OpIdx].isOptionalDef()) {
1732    // FCMPEZD etc. has only one operand.
1733    emitWordLE(Binary);
1734    return;
1735  }
1736
1737  // Encode Dm / Sm.
1738  Binary |= encodeVFPRm(MI, OpIdx);
1739
1740  emitWordLE(Binary);
1741}
1742
1743void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1744  const MCInstrDesc &MCID = MI.getDesc();
1745  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1746
1747  // Part of binary is determined by TableGn.
1748  unsigned Binary = getBinaryCodeForInstr(MI);
1749
1750  // Set the conditional execution predicate
1751  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1752
1753  switch (Form) {
1754  default: break;
1755  case ARMII::VFPConv1Frm:
1756  case ARMII::VFPConv2Frm:
1757  case ARMII::VFPConv3Frm:
1758    // Encode Dd / Sd.
1759    Binary |= encodeVFPRd(MI, 0);
1760    break;
1761  case ARMII::VFPConv4Frm:
1762    // Encode Dn / Sn.
1763    Binary |= encodeVFPRn(MI, 0);
1764    break;
1765  case ARMII::VFPConv5Frm:
1766    // Encode Dm / Sm.
1767    Binary |= encodeVFPRm(MI, 0);
1768    break;
1769  }
1770
1771  switch (Form) {
1772  default: break;
1773  case ARMII::VFPConv1Frm:
1774    // Encode Dm / Sm.
1775    Binary |= encodeVFPRm(MI, 1);
1776    break;
1777  case ARMII::VFPConv2Frm:
1778  case ARMII::VFPConv3Frm:
1779    // Encode Dn / Sn.
1780    Binary |= encodeVFPRn(MI, 1);
1781    break;
1782  case ARMII::VFPConv4Frm:
1783  case ARMII::VFPConv5Frm:
1784    // Encode Dd / Sd.
1785    Binary |= encodeVFPRd(MI, 1);
1786    break;
1787  }
1788
1789  if (Form == ARMII::VFPConv5Frm)
1790    // Encode Dn / Sn.
1791    Binary |= encodeVFPRn(MI, 2);
1792  else if (Form == ARMII::VFPConv3Frm)
1793    // Encode Dm / Sm.
1794    Binary |= encodeVFPRm(MI, 2);
1795
1796  emitWordLE(Binary);
1797}
1798
1799void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1800  // Part of binary is determined by TableGn.
1801  unsigned Binary = getBinaryCodeForInstr(MI);
1802
1803  // Set the conditional execution predicate
1804  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1805
1806  if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD ||
1807      MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){
1808    emitWordLE(Binary);
1809    return;
1810  }
1811
1812  unsigned OpIdx = 0;
1813
1814  // Encode Dd / Sd.
1815  Binary |= encodeVFPRd(MI, OpIdx++);
1816
1817  // Encode address base.
1818  const MachineOperand &Base = MI.getOperand(OpIdx++);
1819  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1820
1821  // If there is a non-zero immediate offset, encode it.
1822  if (Base.isReg()) {
1823    const MachineOperand &Offset = MI.getOperand(OpIdx);
1824    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1825      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1826        Binary |= 1 << ARMII::U_BitShift;
1827      Binary |= ImmOffs;
1828      emitWordLE(Binary);
1829      return;
1830    }
1831  }
1832
1833  // If immediate offset is omitted, default to +0.
1834  Binary |= 1 << ARMII::U_BitShift;
1835
1836  emitWordLE(Binary);
1837}
1838
1839void
1840ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1841  const MCInstrDesc &MCID = MI.getDesc();
1842  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1843
1844  // Part of binary is determined by TableGn.
1845  unsigned Binary = getBinaryCodeForInstr(MI);
1846
1847  // Set the conditional execution predicate
1848  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1849
1850  // Skip operand 0 of an instruction with base register update.
1851  unsigned OpIdx = 0;
1852  if (IsUpdating)
1853    ++OpIdx;
1854
1855  // Set base address operand
1856  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1857
1858  // Set addressing mode by modifying bits U(23) and P(24)
1859  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1860  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1861
1862  // Set bit W(21)
1863  if (IsUpdating)
1864    Binary |= 0x1 << ARMII::W_BitShift;
1865
1866  // First register is encoded in Dd.
1867  Binary |= encodeVFPRd(MI, OpIdx+2);
1868
1869  // Count the number of registers.
1870  unsigned NumRegs = 1;
1871  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1872    const MachineOperand &MO = MI.getOperand(i);
1873    if (!MO.isReg() || MO.isImplicit())
1874      break;
1875    ++NumRegs;
1876  }
1877  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1878  // Otherwise, it will be 0, in the case of 32-bit registers.
1879  if(Binary & 0x100)
1880    Binary |= NumRegs * 2;
1881  else
1882    Binary |= NumRegs;
1883
1884  emitWordLE(Binary);
1885}
1886
1887void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1888  unsigned Opcode = MI.getDesc().Opcode;
1889  // Part of binary is determined by TableGn.
1890  unsigned Binary = getBinaryCodeForInstr(MI);
1891
1892  if (Opcode == ARM::FCONSTS) {
1893    unsigned Imm = getMachineOpValue(MI, 1);
1894    Binary &= ~(0x780000 >> 19);
1895    Binary |= (Imm & 0x780000) >> 19;
1896    Binary &= ~(0x3800000 >> 7);
1897    Binary |= (Imm & 0x3800000) >> 7;
1898    Binary = VFPThumb2PostEncoder(MI, Binary);
1899  }
1900
1901  // Set the conditional execution predicate
1902  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1903
1904  emitWordLE(Binary);
1905}
1906
1907unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
1908                                      unsigned OpIdx) const {
1909  unsigned RegD = MI.getOperand(OpIdx).getReg();
1910  unsigned Binary = 0;
1911  RegD = II->getRegisterInfo().getEncodingValue(RegD);
1912  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1913  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1914  return Binary;
1915}
1916
1917unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI,
1918                                      unsigned OpIdx) const {
1919  unsigned RegN = MI.getOperand(OpIdx).getReg();
1920  unsigned Binary = 0;
1921  RegN = II->getRegisterInfo().getEncodingValue(RegN);
1922  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1923  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1924  return Binary;
1925}
1926
1927unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI,
1928                                      unsigned OpIdx) const {
1929  unsigned RegM = MI.getOperand(OpIdx).getReg();
1930  unsigned Binary = 0;
1931  RegM = II->getRegisterInfo().getEncodingValue(RegM);
1932  Binary |= (RegM & 0xf);
1933  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1934  return Binary;
1935}
1936
1937/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1938/// data-processing instruction to the corresponding Thumb encoding.
1939static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1940  assert((Binary & 0xfe000000) == 0xf2000000 &&
1941         "not an ARM NEON data-processing instruction");
1942  unsigned UBit = (Binary >> 24) & 1;
1943  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1944}
1945
1946void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1947  unsigned Binary = getBinaryCodeForInstr(MI);
1948
1949  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1950  const MCInstrDesc &MCID = MI.getDesc();
1951  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1952    RegTOpIdx = 0;
1953    RegNOpIdx = 1;
1954    LnOpIdx = 2;
1955  } else { // ARMII::NSetLnFrm
1956    RegTOpIdx = 2;
1957    RegNOpIdx = 0;
1958    LnOpIdx = 3;
1959  }
1960
1961  // Set the conditional execution predicate
1962  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1963
1964  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1965  RegT = II->getRegisterInfo().getEncodingValue(RegT);
1966  Binary |= (RegT << ARMII::RegRdShift);
1967  Binary |= encodeNEONRn(MI, RegNOpIdx);
1968
1969  unsigned LaneShift;
1970  if ((Binary & (1 << 22)) != 0)
1971    LaneShift = 0; // 8-bit elements
1972  else if ((Binary & (1 << 5)) != 0)
1973    LaneShift = 1; // 16-bit elements
1974  else
1975    LaneShift = 2; // 32-bit elements
1976
1977  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1978  unsigned Opc1 = Lane >> 2;
1979  unsigned Opc2 = Lane & 3;
1980  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1981  Binary |= (Opc1 << 21);
1982  Binary |= (Opc2 << 5);
1983
1984  emitWordLE(Binary);
1985}
1986
1987void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1988  unsigned Binary = getBinaryCodeForInstr(MI);
1989
1990  // Set the conditional execution predicate
1991  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1992
1993  unsigned RegT = MI.getOperand(1).getReg();
1994  RegT = II->getRegisterInfo().getEncodingValue(RegT);
1995  Binary |= (RegT << ARMII::RegRdShift);
1996  Binary |= encodeNEONRn(MI, 0);
1997  emitWordLE(Binary);
1998}
1999
2000void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
2001  unsigned Binary = getBinaryCodeForInstr(MI);
2002  // Destination register is encoded in Dd.
2003  Binary |= encodeNEONRd(MI, 0);
2004  // Immediate fields: Op, Cmode, I, Imm3, Imm4
2005  unsigned Imm = MI.getOperand(1).getImm();
2006  unsigned Op = (Imm >> 12) & 1;
2007  unsigned Cmode = (Imm >> 8) & 0xf;
2008  unsigned I = (Imm >> 7) & 1;
2009  unsigned Imm3 = (Imm >> 4) & 0x7;
2010  unsigned Imm4 = Imm & 0xf;
2011  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
2012  if (IsThumb)
2013    Binary = convertNEONDataProcToThumb(Binary);
2014  emitWordLE(Binary);
2015}
2016
2017void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
2018  const MCInstrDesc &MCID = MI.getDesc();
2019  unsigned Binary = getBinaryCodeForInstr(MI);
2020  // Destination register is encoded in Dd; source register in Dm.
2021  unsigned OpIdx = 0;
2022  Binary |= encodeNEONRd(MI, OpIdx++);
2023  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2024    ++OpIdx;
2025  Binary |= encodeNEONRm(MI, OpIdx);
2026  if (IsThumb)
2027    Binary = convertNEONDataProcToThumb(Binary);
2028  // FIXME: This does not handle VDUPfdf or VDUPfqf.
2029  emitWordLE(Binary);
2030}
2031
2032void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
2033  const MCInstrDesc &MCID = MI.getDesc();
2034  unsigned Binary = getBinaryCodeForInstr(MI);
2035  // Destination register is encoded in Dd; source registers in Dn and Dm.
2036  unsigned OpIdx = 0;
2037  Binary |= encodeNEONRd(MI, OpIdx++);
2038  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2039    ++OpIdx;
2040  Binary |= encodeNEONRn(MI, OpIdx++);
2041  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2042    ++OpIdx;
2043  Binary |= encodeNEONRm(MI, OpIdx);
2044  if (IsThumb)
2045    Binary = convertNEONDataProcToThumb(Binary);
2046  // FIXME: This does not handle VMOVDneon or VMOVQ.
2047  emitWordLE(Binary);
2048}
2049
2050#include "ARMGenCodeEmitter.inc"
2051