1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARM.h" 19#include "ARMSubtarget.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/FastISel.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetRegisterInfo.h" 25#include <vector> 26 27namespace llvm { 28 class ARMConstantPoolValue; 29 30 namespace ARMISD { 31 // ARM Specific DAG Nodes 32 enum NodeType { 33 // Start the numbering where the builtin ops and target ops leave off. 34 FIRST_NUMBER = ISD::BUILTIN_OP_END, 35 36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 37 // TargetExternalSymbol, and TargetGlobalAddress. 38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 39 // DYN mode. 40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 41 // PIC mode. 42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 43 44 // Add pseudo op to model memcpy for struct byval. 45 COPY_STRUCT_BYVAL, 46 47 CALL, // Function call. 48 CALL_PRED, // Function call that's predicable. 49 CALL_NOLINK, // Function call with branch not branch-and-link. 50 tCALL, // Thumb function call. 51 BRCOND, // Conditional branch. 52 BR_JT, // Jumptable branch. 53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 54 RET_FLAG, // Return with a flag operand. 55 56 PIC_ADD, // Add with a PC operand and a PIC label. 57 58 CMP, // ARM compare instructions. 59 CMN, // ARM CMN instructions. 60 CMPZ, // ARM compare that sets only Z flag. 61 CMPFP, // ARM VFP compare instruction, sets FPSCR. 62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 63 FMSTAT, // ARM fmstat instruction. 64 65 CMOV, // ARM conditional move instructions. 66 67 BCC_i64, 68 69 RBIT, // ARM bitreverse instruction 70 71 FTOSI, // FP to sint within a FP register. 72 FTOUI, // FP to uint within a FP register. 73 SITOF, // sint to FP within a FP register. 74 UITOF, // uint to FP within a FP register. 75 76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 77 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 79 80 ADDC, // Add with carry 81 ADDE, // Add using carry 82 SUBC, // Sub with carry 83 SUBE, // Sub using carry 84 85 VMOVRRD, // double to two gprs. 86 VMOVDRR, // Two gprs to double. 87 88 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 89 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 90 91 TC_RETURN, // Tail call return pseudo. 92 93 THREAD_POINTER, 94 95 DYN_ALLOC, // Dynamic allocation on the stack. 96 97 MEMBARRIER, // Memory barrier (DMB) 98 MEMBARRIER_MCR, // Memory barrier (MCR) 99 100 PRELOAD, // Preload 101 102 VCEQ, // Vector compare equal. 103 VCEQZ, // Vector compare equal to zero. 104 VCGE, // Vector compare greater than or equal. 105 VCGEZ, // Vector compare greater than or equal to zero. 106 VCLEZ, // Vector compare less than or equal to zero. 107 VCGEU, // Vector compare unsigned greater than or equal. 108 VCGT, // Vector compare greater than. 109 VCGTZ, // Vector compare greater than zero. 110 VCLTZ, // Vector compare less than zero. 111 VCGTU, // Vector compare unsigned greater than. 112 VTST, // Vector test bits. 113 114 // Vector shift by immediate: 115 VSHL, // ...left 116 VSHRs, // ...right (signed) 117 VSHRu, // ...right (unsigned) 118 VSHLLs, // ...left long (signed) 119 VSHLLu, // ...left long (unsigned) 120 VSHLLi, // ...left long (with maximum shift count) 121 VSHRN, // ...right narrow 122 123 // Vector rounding shift by immediate: 124 VRSHRs, // ...right (signed) 125 VRSHRu, // ...right (unsigned) 126 VRSHRN, // ...right narrow 127 128 // Vector saturating shift by immediate: 129 VQSHLs, // ...left (signed) 130 VQSHLu, // ...left (unsigned) 131 VQSHLsu, // ...left (signed to unsigned) 132 VQSHRNs, // ...right narrow (signed) 133 VQSHRNu, // ...right narrow (unsigned) 134 VQSHRNsu, // ...right narrow (signed to unsigned) 135 136 // Vector saturating rounding shift by immediate: 137 VQRSHRNs, // ...right narrow (signed) 138 VQRSHRNu, // ...right narrow (unsigned) 139 VQRSHRNsu, // ...right narrow (signed to unsigned) 140 141 // Vector shift and insert: 142 VSLI, // ...left 143 VSRI, // ...right 144 145 // Vector get lane (VMOV scalar to ARM core register) 146 // (These are used for 8- and 16-bit element types only.) 147 VGETLANEu, // zero-extend vector extract element 148 VGETLANEs, // sign-extend vector extract element 149 150 // Vector move immediate and move negated immediate: 151 VMOVIMM, 152 VMVNIMM, 153 154 // Vector move f32 immediate: 155 VMOVFPIMM, 156 157 // Vector duplicate: 158 VDUP, 159 VDUPLANE, 160 161 // Vector shuffles: 162 VEXT, // extract 163 VREV64, // reverse elements within 64-bit doublewords 164 VREV32, // reverse elements within 32-bit words 165 VREV16, // reverse elements within 16-bit halfwords 166 VZIP, // zip (interleave) 167 VUZP, // unzip (deinterleave) 168 VTRN, // transpose 169 VTBL1, // 1-register shuffle with mask 170 VTBL2, // 2-register shuffle with mask 171 172 // Vector multiply long: 173 VMULLs, // ...signed 174 VMULLu, // ...unsigned 175 176 UMLAL, // 64bit Unsigned Accumulate Multiply 177 SMLAL, // 64bit Signed Accumulate Multiply 178 179 // Operands of the standard BUILD_VECTOR node are not legalized, which 180 // is fine if BUILD_VECTORs are always lowered to shuffles or other 181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 182 // operands need to be legalized. Define an ARM-specific version of 183 // BUILD_VECTOR for this purpose. 184 BUILD_VECTOR, 185 186 // Floating-point max and min: 187 FMAX, 188 FMIN, 189 190 // Bit-field insert 191 BFI, 192 193 // Vector OR with immediate 194 VORRIMM, 195 // Vector AND with NOT of immediate 196 VBICIMM, 197 198 // Vector bitwise select 199 VBSL, 200 201 // Vector load N-element structure to all lanes: 202 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 203 VLD3DUP, 204 VLD4DUP, 205 206 // NEON loads with post-increment base updates: 207 VLD1_UPD, 208 VLD2_UPD, 209 VLD3_UPD, 210 VLD4_UPD, 211 VLD2LN_UPD, 212 VLD3LN_UPD, 213 VLD4LN_UPD, 214 VLD2DUP_UPD, 215 VLD3DUP_UPD, 216 VLD4DUP_UPD, 217 218 // NEON stores with post-increment base updates: 219 VST1_UPD, 220 VST2_UPD, 221 VST3_UPD, 222 VST4_UPD, 223 VST2LN_UPD, 224 VST3LN_UPD, 225 VST4LN_UPD, 226 227 // 64-bit atomic ops (value split into two registers) 228 ATOMADD64_DAG, 229 ATOMSUB64_DAG, 230 ATOMOR64_DAG, 231 ATOMXOR64_DAG, 232 ATOMAND64_DAG, 233 ATOMNAND64_DAG, 234 ATOMSWAP64_DAG, 235 ATOMCMPXCHG64_DAG, 236 ATOMMIN64_DAG, 237 ATOMUMIN64_DAG, 238 ATOMMAX64_DAG, 239 ATOMUMAX64_DAG 240 }; 241 } 242 243 /// Define some predicates that are used for node matching. 244 namespace ARM { 245 bool isBitFieldInvertedMask(unsigned v); 246 } 247 248 //===--------------------------------------------------------------------===// 249 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 250 251 class ARMTargetLowering : public TargetLowering { 252 public: 253 explicit ARMTargetLowering(TargetMachine &TM); 254 255 virtual unsigned getJumpTableEncoding() const; 256 257 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 258 259 /// ReplaceNodeResults - Replace the results of node with an illegal result 260 /// type with new values built out of custom code. 261 /// 262 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 263 SelectionDAG &DAG) const; 264 265 virtual const char *getTargetNodeName(unsigned Opcode) const; 266 267 virtual bool isSelectSupported(SelectSupportKind Kind) const { 268 // ARM does not support scalar condition selects on vectors. 269 return (Kind != ScalarCondVectorVal); 270 } 271 272 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 273 virtual EVT getSetCCResultType(EVT VT) const; 274 275 virtual MachineBasicBlock * 276 EmitInstrWithCustomInserter(MachineInstr *MI, 277 MachineBasicBlock *MBB) const; 278 279 virtual void 280 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 281 282 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 283 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 284 285 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 286 287 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 288 /// unaligned memory accesses of the specified type. Returns whether it 289 /// is "fast" by reference in the second argument. 290 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 291 292 virtual EVT getOptimalMemOpType(uint64_t Size, 293 unsigned DstAlign, unsigned SrcAlign, 294 bool IsMemset, bool ZeroMemset, 295 bool MemcpyStrSrc, 296 MachineFunction &MF) const; 297 298 using TargetLowering::isZExtFree; 299 virtual bool isZExtFree(SDValue Val, EVT VT2) const; 300 301 /// isLegalAddressingMode - Return true if the addressing mode represented 302 /// by AM is legal for this target, for a load/store of the specified type. 303 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 305 306 /// isLegalICmpImmediate - Return true if the specified immediate is legal 307 /// icmp immediate, that is the target has icmp instructions which can 308 /// compare a register against the immediate without having to materialize 309 /// the immediate into a register. 310 virtual bool isLegalICmpImmediate(int64_t Imm) const; 311 312 /// isLegalAddImmediate - Return true if the specified immediate is legal 313 /// add immediate, that is the target has add instructions which can 314 /// add a register and the immediate without having to materialize 315 /// the immediate into a register. 316 virtual bool isLegalAddImmediate(int64_t Imm) const; 317 318 /// getPreIndexedAddressParts - returns true by value, base pointer and 319 /// offset pointer and addressing mode by reference if the node's address 320 /// can be legally represented as pre-indexed load / store address. 321 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 322 SDValue &Offset, 323 ISD::MemIndexedMode &AM, 324 SelectionDAG &DAG) const; 325 326 /// getPostIndexedAddressParts - returns true by value, base pointer and 327 /// offset pointer and addressing mode by reference if this node can be 328 /// combined with a load / store to form a post-indexed load / store. 329 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 330 SDValue &Base, SDValue &Offset, 331 ISD::MemIndexedMode &AM, 332 SelectionDAG &DAG) const; 333 334 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 335 APInt &KnownZero, 336 APInt &KnownOne, 337 const SelectionDAG &DAG, 338 unsigned Depth) const; 339 340 341 virtual bool ExpandInlineAsm(CallInst *CI) const; 342 343 ConstraintType getConstraintType(const std::string &Constraint) const; 344 345 /// Examine constraint string and operand type and determine a weight value. 346 /// The operand object must already have been set up with the operand type. 347 ConstraintWeight getSingleConstraintMatchWeight( 348 AsmOperandInfo &info, const char *constraint) const; 349 350 std::pair<unsigned, const TargetRegisterClass*> 351 getRegForInlineAsmConstraint(const std::string &Constraint, 352 EVT VT) const; 353 354 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 355 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 356 /// true it means one of the asm constraint of the inline asm instruction 357 /// being processed is 'm'. 358 virtual void LowerAsmOperandForConstraint(SDValue Op, 359 std::string &Constraint, 360 std::vector<SDValue> &Ops, 361 SelectionDAG &DAG) const; 362 363 const ARMSubtarget* getSubtarget() const { 364 return Subtarget; 365 } 366 367 /// getRegClassFor - Return the register class that should be used for the 368 /// specified value type. 369 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const; 370 371 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 372 /// be used for loads / stores from the global. 373 virtual unsigned getMaximalGlobalOffset() const; 374 375 /// createFastISel - This method returns a target specific FastISel object, 376 /// or null if the target does not support "fast" ISel. 377 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 378 const TargetLibraryInfo *libInfo) const; 379 380 Sched::Preference getSchedulingPreference(SDNode *N) const; 381 382 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 383 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 384 385 /// isFPImmLegal - Returns true if the target can instruction select the 386 /// specified FP immediate natively. If false, the legalizer will 387 /// materialize the FP immediate as a load from a constant pool. 388 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 389 390 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 391 const CallInst &I, 392 unsigned Intrinsic) const; 393 protected: 394 std::pair<const TargetRegisterClass*, uint8_t> 395 findRepresentativeClass(MVT VT) const; 396 397 private: 398 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 399 /// make the right decision when generating code for different targets. 400 const ARMSubtarget *Subtarget; 401 402 const TargetRegisterInfo *RegInfo; 403 404 const InstrItineraryData *Itins; 405 406 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 407 /// 408 unsigned ARMPCLabelIndex; 409 410 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 411 void addDRTypeForNEON(MVT VT); 412 void addQRTypeForNEON(MVT VT); 413 414 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 415 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 416 SDValue Chain, SDValue &Arg, 417 RegsToPassVector &RegsToPass, 418 CCValAssign &VA, CCValAssign &NextVA, 419 SDValue &StackPtr, 420 SmallVector<SDValue, 8> &MemOpChains, 421 ISD::ArgFlagsTy Flags) const; 422 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 423 SDValue &Root, SelectionDAG &DAG, 424 DebugLoc dl) const; 425 426 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 427 bool isVarArg) const; 428 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 429 DebugLoc dl, SelectionDAG &DAG, 430 const CCValAssign &VA, 431 ISD::ArgFlagsTy Flags) const; 432 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 433 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 434 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 435 const ARMSubtarget *Subtarget) const; 436 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 437 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 438 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 439 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 440 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 441 SelectionDAG &DAG) const; 442 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 443 SelectionDAG &DAG, 444 TLSModel::Model model) const; 445 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 447 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 448 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 449 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 450 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 451 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 452 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 453 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 454 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 455 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 456 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 457 const ARMSubtarget *ST) const; 458 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 459 const ARMSubtarget *ST) const; 460 461 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 462 463 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 464 CallingConv::ID CallConv, bool isVarArg, 465 const SmallVectorImpl<ISD::InputArg> &Ins, 466 DebugLoc dl, SelectionDAG &DAG, 467 SmallVectorImpl<SDValue> &InVals) const; 468 469 virtual SDValue 470 LowerFormalArguments(SDValue Chain, 471 CallingConv::ID CallConv, bool isVarArg, 472 const SmallVectorImpl<ISD::InputArg> &Ins, 473 DebugLoc dl, SelectionDAG &DAG, 474 SmallVectorImpl<SDValue> &InVals) const; 475 476 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 477 DebugLoc dl, SDValue &Chain, 478 const Value *OrigArg, 479 unsigned OffsetFromOrigArg, 480 unsigned ArgOffset, 481 bool ForceMutable = false) 482 const; 483 484 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 485 unsigned &VARegSize, unsigned &VARegSaveSize) const; 486 487 virtual SDValue 488 LowerCall(TargetLowering::CallLoweringInfo &CLI, 489 SmallVectorImpl<SDValue> &InVals) const; 490 491 /// HandleByVal - Target-specific cleanup for ByVal support. 492 virtual void HandleByVal(CCState *, unsigned &, unsigned) const; 493 494 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 495 /// for tail call optimization. Targets which want to do tail call 496 /// optimization should implement this function. 497 bool IsEligibleForTailCallOptimization(SDValue Callee, 498 CallingConv::ID CalleeCC, 499 bool isVarArg, 500 bool isCalleeStructRet, 501 bool isCallerStructRet, 502 const SmallVectorImpl<ISD::OutputArg> &Outs, 503 const SmallVectorImpl<SDValue> &OutVals, 504 const SmallVectorImpl<ISD::InputArg> &Ins, 505 SelectionDAG& DAG) const; 506 507 virtual bool CanLowerReturn(CallingConv::ID CallConv, 508 MachineFunction &MF, bool isVarArg, 509 const SmallVectorImpl<ISD::OutputArg> &Outs, 510 LLVMContext &Context) const; 511 512 virtual SDValue 513 LowerReturn(SDValue Chain, 514 CallingConv::ID CallConv, bool isVarArg, 515 const SmallVectorImpl<ISD::OutputArg> &Outs, 516 const SmallVectorImpl<SDValue> &OutVals, 517 DebugLoc dl, SelectionDAG &DAG) const; 518 519 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 520 521 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 522 523 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 524 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 525 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 526 SelectionDAG &DAG, DebugLoc dl) const; 527 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 528 529 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 530 531 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 532 MachineBasicBlock *BB, 533 unsigned Size) const; 534 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 535 MachineBasicBlock *BB, 536 unsigned Size, 537 unsigned BinOpcode) const; 538 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 539 MachineBasicBlock *BB, 540 unsigned Op1, 541 unsigned Op2, 542 bool NeedsCarry = false, 543 bool IsCmpxchg = false, 544 bool IsMinMax = false, 545 ARMCC::CondCodes CC = ARMCC::AL) const; 546 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 547 MachineBasicBlock *BB, 548 unsigned Size, 549 bool signExtend, 550 ARMCC::CondCodes Cond) const; 551 552 void SetupEntryBlockForSjLj(MachineInstr *MI, 553 MachineBasicBlock *MBB, 554 MachineBasicBlock *DispatchBB, int FI) const; 555 556 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 557 MachineBasicBlock *MBB) const; 558 559 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 560 561 MachineBasicBlock *EmitStructByval(MachineInstr *MI, 562 MachineBasicBlock *MBB) const; 563 }; 564 565 enum NEONModImmType { 566 VMOVModImm, 567 VMVNModImm, 568 OtherModImm 569 }; 570 571 572 namespace ARM { 573 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 574 const TargetLibraryInfo *libInfo); 575 } 576} 577 578#endif // ARMISELLOWERING_H 579